WO2008025057A1 - Thin-film diode structure using a sacrificial doped dielectric layer - Google Patents

Thin-film diode structure using a sacrificial doped dielectric layer Download PDF

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WO2008025057A1
WO2008025057A1 PCT/AU2007/001205 AU2007001205W WO2008025057A1 WO 2008025057 A1 WO2008025057 A1 WO 2008025057A1 AU 2007001205 W AU2007001205 W AU 2007001205W WO 2008025057 A1 WO2008025057 A1 WO 2008025057A1
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layer
semiconductor
amorphous
doped
undoped
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PCT/AU2007/001205
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French (fr)
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Per Ingemar Widenborg
Armin Gerhard Aberle
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Newsouth Innovations Pty Limited
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Publication of WO2008025057A1 publication Critical patent/WO2008025057A1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66113—Avalanche diodes
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • H01L31/077—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells the devices comprising monocrystalline or polycrystalline materials
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1872—Recrystallisation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates broadly to a method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate, and to a thin-film crystalline semiconductor 3-layer diode structure.
  • Thin-film crystalline semiconductor device structures on foreign supporting materials such as glass are becoming increasingly important in the electronics industry, for example in thin-film solar cells and in flat panel displays.
  • thin-films have the potential to dramatically reduce the cost of manufacture of solar modules due to the fact that they only require a fraction of the semiconductor material as compared to traditional, silicon wafer based modules.
  • Thin-film solar cells furthermore, have the advantage that it is possible to manufacture them on large-area supporting materials ( ⁇ 1 m 2 ), streamlining the production process and further reducing processing costs.
  • a crystalline semiconductor diode typically is a 3-layer device of the structure n + ⁇ p + or p + ⁇ n + , whereby the superscript "+" indicates heavy doping and ⁇ is either p (for light p-type doping), n (for light n-type doping) or i (for intrinsic, i.e. undoped material).
  • the heavy doping of both surface layers allows the formation of low-resistance ohmic contacts and also is beneficial for reducing carrier recombination rates in the diode.
  • glass is a particularly important supporting foreign material in electronics, enabling e.g. flat panel displays based on liquid crystals and thin-film solar modules in superstrate configuration (i.e., the sunlight enters the solar cell through the glass sheet).
  • flat panel displays based on liquid crystals and thin-film solar modules in superstrate configuration
  • the formation of device-quality crystalline semiconductor materials on glass presents a daunting challenge.
  • One of the most successful methods for low temperature poly-Si solar cells developed so far is the "partial doping method" of Matsuyama et alia ["High-quality polycrystalline silicon thin film prepared by a solid phase crystallisation method", Journal of Non-Crystalline Solids, Vol. 198-200, pp.
  • a 2-layer stack of amorphous silicon material (thickness in the range 1-20 microns) is crystallised during several hours at about 600 0 C by means of solid-phase crystallisation (SPC).
  • SPC solid-phase crystallisation
  • Excellent- quality crystalline silicon material can be obtained by SPC if the 2-layer amorphous stack consists of a thin, heavily n-type (phosphorus) doped layer and a much thicker, undoped or lightly doped layer.
  • the reason for the excellent material quality produced by this method is the directional crystallisation of the entire stack, starting in the n + doped layer ("nucleation layer”) and then progressing through the remainder of the structure (“crystallisation layer”).
  • Matsuyama et alia have shown that a heavily phosphorus-doped amorphous silicon layer crystallises much more rapidly than a lightly doped (or undoped) silicon layer, and hence acts as an excellent nucleation layer in a n + n (or n + i) structure.
  • Matsuyama et alia deposited a heavily p + doped hydrogenated amorphous silicon layer onto the structure at low temperature, giving a heterojunction diode consisting of both crystalline and amorphous silicon.
  • Measurements under standard test conditions revealed that such low-temperature fabricated heterojunction diodes exhibit good solar cell efficiencies of over 9% on metal substrates, with a minority carrier diffusion length in the absorber region ("base”) of about 10 microns.
  • a method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate comprising depositing a sacrificial dielectric overlayer containing n or p-type dopant atoms on an exposed amorphous lightly doped or undoped semiconductor layer of a 2-layer semiconductor structure formed on the substrate or superstrate; crystallising the amorphous lightly doped or undoped semiconductor layer; forming a heavily doped semiconductor layer by diffusing the n or p-type atoms from the sacrificial dielectric overlayer into a portion of the crystallised lightly doped or undoped semiconductor layer, whereby the 3-layer diode structure is formed; and removing the sacrificial dielectric overlayer from the 3-layer diode structure.
  • the 2-layer semiconductor structure may comprise the amorphous lightly doped or undoped semiconductor layer and an amorphous heavily doped buried semiconductor layer, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises crystallising the heavily doped buried semiconductor layer via solid phase crystallisation.
  • the solid phase crystallisation may be performed during about 6-48 hours at temperatures in the range of about 500 to 650 0 C.
  • the method may further comprise forming the 2-layer semiconductor structure by forming a crystalline semiconductor seed layer on the substrate or superstrate, preparing a hydrogen-terminated seed layer surface on the crystalline semiconductor seed layer, and depositing the lightly doped or undoped amorphous layer on the seed layer surface, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises solid phase epitaxy.
  • the crystalline semiconductor seed layer may be heavily doped with a polarity of the opposite type compared to the heavily doped semiconductor layer.
  • the crystalline semiconductor seed layer may be undoped or doped with a same polarity as the heavily doped semiconductor layer
  • forming the 2-layer semiconductor structure comprises depositing an amorphous semiconductor film on the seed layer surface such that a first portion of the amorphous semiconductor film adjacent the crystalline semiconductor seed layer is heavily doped with a polarity of an opposite type compared to the heavily doped semiconductor layer, and such that a second portion of the amorphous semiconductor film is the amorphous lightly doped or undoped semiconductor layer, and the step of forming the heavily doped semiconductor layer further comprises diffusing dopant atoms from the first portion of the amorphous semiconductor film into the crystalline semiconductor seed layer to form a heavily doped buried semiconductor layer of the 3-layer semiconductor structure.
  • the solid phase epitaxy may be performed during about 6-48 hours at temperatures in the range of about 500 to 65O 0 C.
  • the seed layer may be fabricated with a method chosen from a group consisting of aluminium-induced crystallisation, metal-induced crystallisation, solid-phase crystallisation or laser-induced crystallisation.
  • the method may comprise forming a dielectric barrier layer on the substrate or superstrate, and forming the 3-layer diode structure on the dielectric barrier layer.
  • the dielectric barrier layer may comprise a material chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
  • the 3-layer diode structure may comprise a material chosen from a group consisting of silicon, germanium, or an alloy of silicon and germanium.
  • the sacrificial dielectric overlayer may be chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
  • the sacrificial dielectric overlayer may be deposited using a method chosen from a group consisting of PECVD, sputtering and evaporation.
  • the heavily doped semiconductor layer may be formed by diffusing the n or p-type atoms from the sacrificial dielectric overlayer using rapid thermal annealing performed in a temperature range of about 800-1050 0 C for periods in the range of about 1 sec to 15 minutes.
  • the method may further comprise exposing the 3-layer diode structure to atomic hydrogen after the removal of the sacrificial dielectric overlayer at a temperature in the range of about 350 to 650 0 C.
  • the sacrificial dielectric overlayer may be deposited in-situ without breaking the vacuum after the final step of the formation of the lightly or undoped amorphous semiconductor structure.
  • the doping of the lightly doped or undoped semiconductor layer may be lower than about 10 18 cm "3 , and the doping of the heavily doped buried semiconductor layer is greater than about 10 18 cm "3 .
  • a surface on which the 3-layer semiconductor structure may be supported is textured to assist light trapping in the 3-layer semiconductor structure.
  • a thin-film crystalline semiconductor 3-layer diode structure formed on a foreign supporting substrate or superstrate using a method as defined in the first aspect.
  • Figs. 1 to 5 are schematic cross-sectional drawings illustrating manufacture of devices utilizing solid phase crystallisation (SPC).
  • Figs. 6 to 10 are schematic cross-sectional drawings illustrating manufacture of devices utilizing solid phase epitaxy (SPE).
  • One described method uses a sacrificial doped dielectric overlayer on an amorphous n + ⁇ (or p + ⁇ ) 2-layer structure with a subsequent crystallisation of the amorphous 2-layer stack by SPC at about 600 0 C.
  • the third, heavily doped layer of the n + ⁇ p + (or p + ⁇ n + ) thin-film crystalline diode structure is generated by dopant diffusion from the doped overlayer into the underlying crystalline silicon layer during a separate rapid thermal anneal (RTA) at high temperatures in the about 800-1050 0 C range.
  • RTA rapid thermal anneal
  • the RTA is followed by a defect passivation treatment using atomic hydrogen in the about 500-620 0 C range, whereby the doped overlayer (doped silicon oxide) is removed with a hydrofluoric acid dip just prior to the hydrogenation treatment.
  • a large fraction of the dopants in the third layer is electronically active after the hydrogenation treatment.
  • a single layer of ⁇ -type (i.e., lightly doped or undoped) amorphous silicon is deposited onto a hydrogen-terminated heavily doped crystalline silicon seed layer on a glass sheet, followed by the deposition of the sacrificial doped dielectric overlayer.
  • the crystallisation of the amorphous silicon layer in this case occurs via solid-phase epitaxy (SPE).
  • SPE solid-phase epitaxy
  • the required third, heavily doped layer is again created by dopant diffusion from the sacrificial doped overlayer into the underlying crystalline silicon layer during a rapid thermal anneal (RTA) at high temperatures in the about 800-1050 0 C range.
  • the sacrificial doped overlayer (doped silicon oxide) is removed with a hydrofluoric acid dip just prior to a treatment with atomic hydrogen in the about 500-620 0 C range. A large fraction of the dopants in the third layer is electronically active after the hydrogenation treatment.
  • a thin dielectric barrier layer 12 is deposited onto a foreign supporting material 11 , as shown in Fig. 1.
  • the foreign supporting material 11 can be suitably textured to assist light trapping in the finished 3-layer semiconductor structure.
  • the dielectric barrier layer 12 comprises a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials.
  • a SiN film with a thickness of about 70 nm can be deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) methods using a gas mixture of silane, ammonia and nitrogen.
  • PECVD Plasma Enhanced Chemical Vapour Deposition
  • a 2-layer stack (13, 14) of amorphous semiconductor material is deposited onto the thin dielectric layer 12, where the first layer 13 is heavily doped whereas the second layer 14 is lightly doped or intrinsic, as shown in Fig. 2.
  • the layers 13 and 14 may comprise amorphous semiconductor material such as silicon, germanium or an alloy of silicon and germanium.
  • amorphous silicon can be deposited by PECVD methods using a gas mixture of silane and doped hydrogen with a deposition temperature of about 375 - 425 0 C range, where the first layer 13 is heavily doped, in the range of about 1x10 18 to 1x10 21 cm “3 phosphorus atoms, with a preferred phosphorus concentration of about 1x10 20 cm “3 and a preferred thickness of about 50 nm.
  • the second layer 14 may be lightly p-type doped by boron in the range of about 1x10 15 to 1x10 18 cm "3 , with a preferred boron concentration of about 5x10 16 and a preferred thickness of about 1500 nm.
  • the dielectric layer 15 is then deposited onto the amorphous semiconductor layer 14, as shown in Fig. 3.
  • the dielectric layer 15 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials.
  • the dielectric layer 15 can be deposited utilising deposition techniques such as plasma enhanced chemical vapour deposition (PECVD), sputtering or evaporation.
  • PECVD plasma enhanced chemical vapour deposition
  • the dielectric layer 15, with a thickness of about 70 nm comprises a boron doped (p-type) silicon oxide containing trace amount of carbon, deposited via radio-frequency (13.56 MHz) PECVD (RF PECVD), in a standard parallel-plate configuration, at a substrate temperature of 300-350 0 C.
  • RF PECVD radio-frequency PECVD
  • the gas mixture used in one example consists of (gas flow in brackets): silane (about 1 seem), 0.5% trimethylboron in hydrogen (about 2 seem), nitrous oxide (about 150 seem), and nitrogen (about 150 seem).
  • the deposition pressure was about 150 mTorr and the power density was about 0.025 W/cm 2 .
  • the resulting deposition rate was about 10 nm/min.
  • the dielectric layer 15 is deposited in-situ without breaking the vacuum in a vacuum deposition chamber after the amorphous semiconductor deposition step (compare Fig. 2).
  • the device 20 is then subjected to a thermal anneal where the amorphous semiconductor layers 13 and 14 crystallise via SPC and where the doping atoms in the exposed thin dielectric layer 15 do not diffuse significantly into the semiconductor layers 13 and 14.
  • the crystallisation is performed during about 6-48 hours at temperatures in the range of about 500-650 0 C.
  • this thermal annealing step is performed in a nitrogen-purged atmospheric-pressure furnace.
  • RTA rapid thermal anneal
  • the RTA is performed in a temperature range of about 800-1050 0 C for a period in the range of about 1 second to 15 minutes.
  • the thin doped dielectric layer 15 is removed and the device 21 subjected to an atomic hydrogen treatment, as shown in Fig. 5.
  • the exposure to atomic hydrogen is performed at a temperature in the range of about 350- 650°C.
  • Several 1.5 micron thick silicon solar cell devices fabricated using the method described above with reference to Figs. 1 to 5 have been fabricated by PECVD (plasma- enhanced chemical vapour deposition), utilising a borosilicate glass sheet 11, a silicon nitride layer 12, a heavily phosphorus doped amorphous-Si:H layer 13, a lightly boron doped amorphous-Si:H layer 14, and a heavily boron doped silicon (carbon) oxide layer 15 which was deposited in-situ on the base layer 14.
  • PECVD plasma- enhanced chemical vapour deposition
  • the devices were then subjected to an RTA treatment at about 900 0 C for 5 minutes, during which the third, heavily doped layer 16 was created by dopant diffusion.
  • the sacrificial boron-doped silicon (carbon) oxide layer 15 was then removed by etching in hydrofluoric acid, followed by a hydrogenation process at about 610 0 C glass temperature for about 15 min duration.
  • the resulting p + layer (layer 16) is heavily doped with boron, as confirmed by measured sheet resistances as low as 1000 Ohms/square and hot probe measurements for determination of the doping polarity.
  • Electrical characterization of the fabricated p-n junction solar cells showed that the described sacrificial doped dielectric overlayer method for forming the heavily doped back surface layer ("back surface field" (BSF) layer) has a superior quality compared to devices with a conventionally grown BSF layer.
  • BSF back surface field
  • the open circuit voltage difference between solar cells with the described diffused BSF layer and an equivalent device where the only difference is a conventionally grown BSF layer was a significant 40-50 mV, with a higher voltage for the described diffused BSF layer.
  • One metallised solar cell with a diffused BSF layer obtained a fill factor of over 70%, which is an excellent value for poly-Si solar cells on glass.
  • a thin dielectric barrier layer 112 is deposited onto a foreign supporting material 111 and a thin, large-grained heavily doped (>10 18 cm “3 ) crystalline semiconductor layer 117 is formed on the layer 112, as shown in Fig. 6.
  • the foreign supporting material 112 can be suitably textured to assist light trapping in the finished 3- layer semiconductor structure.
  • the texture has been omitted in Figs 6 to 10. It will be appreciated by the person skilled in the art that formation of a thin ( « 1 micron) crystalline semiconductor layer on a foreign substrate is much easier than the formation of a thick (> 1 micron) crystalline layer using existing deposition techniques.
  • the crystalline semiconductor layer or seed layer 117 can be fabricated utilising techniques such as aluminium-induced crystallisation, metal-induced crystallisation, solid-phase crystallisation, or laser-induced crystallisation.
  • the dielectric barrier layer 112 comprises a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials.
  • a SiN film with a thickness of 70 nm ⁇ 10 nm can be deposited by PECVD methods using a gas mixture of silane, ammonia and nitrogen.
  • a clean and hydrogen-terminated seed layer surface is created, followed by the deposition of a lightly doped amorphous semiconductor layer 118, as shown in Fig. 7.
  • a clean hydrogen-terminated silicon surface is, for example, realised by the steps of: (i) immersing the silicon surface for 10 minutes in a fresh 1 :1 mixture of hydrogen peroxide and sulfuric acid; (ii) rinsing the surface in de-ionized water; (iii) immersing the surface of the crystalline silicon layer 117 into a 5% hydrofluoric acid solution until the surface is hydrophobic followed by a rinse in deionized water.
  • the crystalline silicon layer 117 with the clean hydrogen-terminated silicon surface and its supporting layer 111 and 112 is loaded into the vacuum machine within about 60 minutes of completion of the cleaning step.
  • the layer 118 may comprise amorphous semiconductor material such as silicon, germanium or an alloy of silicon and germanium.
  • amorphous silicon can be deposited by PECVD methods using a gas mixture of silane and doped hydrogen with a deposition temperature of about 375 - 425°C range, where the layer 118 is lightly p-type doped with boron in the range of about 1x10 15 to 1x10 18 cm "3 , with a preferred boron concentration of about 5x10 16 and a preferred thickness of about 1500 nm.
  • a thin doped dielectric layer 119 is then deposited onto the amorphous semiconductor layer 118, as shown in Fig. 8.
  • the dielectric layer 119 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials.
  • the dielectric layer 119 can be deposited utilising deposition techniques such as PECVD, sputtering or evaporation.
  • the dielectric layer 119 with a thickness of about 70 nm, comprises a boron doped (p-type) silicon oxide, containing trace amount of carbon, deposited via radio frequency (13.56
  • the dielectric layer (gas flow in brackets): silane (about 1 seem), 0.5% trimethylboron in hydrogen (about 2 seem), nitrous oxide (about 150 seem), and nitrogen (about 150 seem).
  • the deposition pressure was about 150 mTorr and the RF power density was about 0.025 W/cm 2 , resulting in a deposition rate of about 10 nm/min.
  • the dielectric layer (gas flow in brackets): silane (about 1 seem), 0.5% trimethylboron in hydrogen (about 2 seem), nitrous oxide (about 150 seem), and nitrogen (about 150 seem).
  • 119 is deposited in-situ without breaking the vacuum in a vacuum deposition chamber after the amorphous semiconductor deposition step (compare Fig. 7).
  • the device 121 is then subjected to a thermal anneal where the amorphous semiconductor layer 118 crystallises via SPE and where the doping atoms in the exposed thin dielectric layer 119 do not diffuse significantly into the semiconductor layer 118.
  • the crystallisation is performed during about 6-48 hours at temperatures in the range of about 500-650 0 C.
  • RTA rapid thermal anneal
  • the RTA is performed in a temperature range of about 800-1050 0 C for period in the range of about 1 second to 15 minutes.
  • the thin doped dielectric layer 119 is removed and the device 122 subjected to an atomic hydrogen treatment, as shown in Fig. 10.
  • the exposure to atomic hydrogen is performed at a temperature in the range of about 350- 65O 0 C.
  • an intrinsic (i.e. undoped) seed layer, or a seed layer with low doping level and/or undesirable doping polarity is formed.
  • the amorphous semiconductor layer 118 can be deposited as a 2 doping level structure in the modified embodiment, whereas a thin region (thickness about 50nm ⁇ 20 nm) of layer 118 adjacent to the seed layer contains an excess of the doping atoms (n or p-type with a concentration in the range of 5x10 19 to 1x10 21 cm "3 ) dedicated for the seed layer.
  • the excess dopants from the adjacent region in layer 118 diffuses into the seed layer 117 and form the desired doping level and polarity in the seed layer, simultaneously as the formation of the heavily doped BSF layer 120 as described above.
  • the excess doping in layer 118 adjacent to the seed layer has opposite doping polarity to the BSF layer 120.
  • the described methods provide fabrication of a 3-layer stack (n + ⁇ p + or p + ⁇ n + ) of crystalline semiconductor material, via SPC or SPE, where the crystallisation of the entire stack occurs only from one side. This can provide an improved grain size and lower defect density compared to crystallisation of the entire 3-layer stack from both sides. Also, enhanced dopant diffusion from the doped dielectric along preferred regions, for example grain boundaries, in the crystalline layer may provide a reduced recombination rate in the fabricated diodes.
  • the doped dielectric layer deposited on the amorphous semiconductor also functions as a protective diffusion barrier against atmospheric contamination during the crystallisation and sample handling.
  • the doped dielectric layer prevents contaminants from the RTA chamber to diffuse into the crystalline semiconductor during the RTA process, which usually is a large source of contamination due to the very high temperature used during the RTA process.
  • the described methods enable the realisation of n + ⁇ p + (or p + ⁇ n + ) homojunction crystalline thin-film diode structures on glass with a streamlined manufacturing process while maintaining a high material quality. This offers significant potential for the realisation of more cost-effective and yet efficient thin-film solar cells and modules.

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Abstract

A method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate, and a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate are disclosed. A sacrificial dielectric overlayer (15) containing n or p-type dopant atoms is deposited on an exposed amorphous lightly doped or undoped semiconductor layer of a 2-layer semiconductor structure (13, 14) formed on the substrate or superstrate (11 ). The amorphous lightly doped or undoped semiconductor layer (13, 14) is crystalised. A heavily doped semiconductor layer is formed by diffusing the n or p-type atoms from the sacrificial dielectric overlayer into a portion of the crystallised lightly doped or undoped semiconductor layer, whereby the 3-layer diode structure (21) is formed. The sacrificial dielectric overlayer (15) is removed from the 3-layer diode structure.

Description

Thin-Film Diode Structure Using A Sacrificial Doped Dielectric Layer
FIELD OF THE INVENTION
The present invention relates broadly to a method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate, and to a thin-film crystalline semiconductor 3-layer diode structure.
BACKGROUND
Thin-film crystalline semiconductor device structures on foreign supporting materials such as glass are becoming increasingly important in the electronics industry, for example in thin-film solar cells and in flat panel displays. In the case of solar cells, thin-films have the potential to dramatically reduce the cost of manufacture of solar modules due to the fact that they only require a fraction of the semiconductor material as compared to traditional, silicon wafer based modules. Thin-film solar cells, furthermore, have the advantage that it is possible to manufacture them on large-area supporting materials (~1 m2), streamlining the production process and further reducing processing costs.
A crystalline semiconductor diode typically is a 3-layer device of the structure n+πp+ or p+πn+, whereby the superscript "+" indicates heavy doping and π is either p (for light p-type doping), n (for light n-type doping) or i (for intrinsic, i.e. undoped material). The heavy doping of both surface layers allows the formation of low-resistance ohmic contacts and also is beneficial for reducing carrier recombination rates in the diode.
Owing to transparency and low cost, glass is a particularly important supporting foreign material in electronics, enabling e.g. flat panel displays based on liquid crystals and thin-film solar modules in superstrate configuration (i.e., the sunlight enters the solar cell through the glass sheet). However, due to the limited thermal stability of glass, the formation of device-quality crystalline semiconductor materials on glass presents a formidable challenge. One of the most successful methods for low temperature poly-Si solar cells developed so far is the "partial doping method" of Matsuyama et alia ["High-quality polycrystalline silicon thin film prepared by a solid phase crystallisation method", Journal of Non-Crystalline Solids, Vol. 198-200, pp. 940-944 (1996)] where a 2-layer stack of amorphous silicon material (thickness in the range 1-20 microns) is crystallised during several hours at about 6000C by means of solid-phase crystallisation (SPC). Excellent- quality crystalline silicon material can be obtained by SPC if the 2-layer amorphous stack consists of a thin, heavily n-type (phosphorus) doped layer and a much thicker, undoped or lightly doped layer. The reason for the excellent material quality produced by this method is the directional crystallisation of the entire stack, starting in the n+ doped layer ("nucleation layer") and then progressing through the remainder of the structure ("crystallisation layer"). Matsuyama et alia have shown that a heavily phosphorus-doped amorphous silicon layer crystallises much more rapidly than a lightly doped (or undoped) silicon layer, and hence acts as an excellent nucleation layer in a n+n (or n+i) structure. To realise a diode structure from the SPC-made n+n structure, Matsuyama et alia deposited a heavily p+ doped hydrogenated amorphous silicon layer onto the structure at low temperature, giving a heterojunction diode consisting of both crystalline and amorphous silicon. Measurements under standard test conditions revealed that such low-temperature fabricated heterojunction diodes exhibit good solar cell efficiencies of over 9% on metal substrates, with a minority carrier diffusion length in the absorber region ("base") of about 10 microns.
While the efficiencies obtained by Matsuyama et alia are reasonable for a thin- film crystalline silicon solar cell on a foreign substrate, there is the disadvantage that the formation of the heavily p+ doped hydrogenated amorphous silicon requires a separate semiconductor deposition step (whereby the surface of the n or i-type. silicon layer needs to be cleaned in a careful, and possibly expensive, way) and that contacting of the p+ amorphous silicon layer cannot be realised, due to low lateral conductance of amorphous silicon, by simply putting down a metal grid but instead requires the additional deposition of a transparent conductive oxide (TCO) with a low sheet resistance (< 1000 Ω/square), significantly adding to the cost of manufacture of the device. Another method for realising a thin-film crystalline silicon diode structure on a foreign substrate has been suggested by Basore ["Simplified processing and improved efficiency of crystalline silicon on glass modules", Conf. Record 19th European Photovoltaic Solar Energy Conference, Paris, June 2004, pp. 455-458 (WIP, Munich, 2004)]. A n+pp+ stack of amorphous silicon is deposited onto a glass superstrate and then the entire 3-layer stack is crystallised during several hours at about 6000C by SPC. Again, the purpose of the n+ layer is to act as the nucleation layer and thus to provide a directional crystallisation of the entire amorphous stack. The benefit of this approach is a more streamlined, and hence very likely more cost-effective, manufacturing process. However, due to the presence of the heavily p-doped (boron) layer at the surface, nucleation will not only start in the buried n+ layer but also in the p+ layer. Hence, the crystallisation of the entire stack occurs from both sides, resulting in a significantly reduced grain size and a significantly larger defect density compared to the Sanyo method.
A need therefore exists to provide a method for realising a thin-film crystalline silicon diode structure that seeks to address at least one of the abovementioned disadvantages.
SUMMARY
In accordance with a first aspect of the present invention there is provided a method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate, the method comprising depositing a sacrificial dielectric overlayer containing n or p-type dopant atoms on an exposed amorphous lightly doped or undoped semiconductor layer of a 2-layer semiconductor structure formed on the substrate or superstrate; crystallising the amorphous lightly doped or undoped semiconductor layer; forming a heavily doped semiconductor layer by diffusing the n or p-type atoms from the sacrificial dielectric overlayer into a portion of the crystallised lightly doped or undoped semiconductor layer, whereby the 3-layer diode structure is formed; and removing the sacrificial dielectric overlayer from the 3-layer diode structure. The 2-layer semiconductor structure may comprise the amorphous lightly doped or undoped semiconductor layer and an amorphous heavily doped buried semiconductor layer, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises crystallising the heavily doped buried semiconductor layer via solid phase crystallisation.
The solid phase crystallisation may be performed during about 6-48 hours at temperatures in the range of about 500 to 6500C.
The method may further comprise forming the 2-layer semiconductor structure by forming a crystalline semiconductor seed layer on the substrate or superstrate, preparing a hydrogen-terminated seed layer surface on the crystalline semiconductor seed layer, and depositing the lightly doped or undoped amorphous layer on the seed layer surface, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises solid phase epitaxy.
The crystalline semiconductor seed layer may be heavily doped with a polarity of the opposite type compared to the heavily doped semiconductor layer.
The crystalline semiconductor seed layer may be undoped or doped with a same polarity as the heavily doped semiconductor layer, and forming the 2-layer semiconductor structure comprises depositing an amorphous semiconductor film on the seed layer surface such that a first portion of the amorphous semiconductor film adjacent the crystalline semiconductor seed layer is heavily doped with a polarity of an opposite type compared to the heavily doped semiconductor layer, and such that a second portion of the amorphous semiconductor film is the amorphous lightly doped or undoped semiconductor layer, and the step of forming the heavily doped semiconductor layer further comprises diffusing dopant atoms from the first portion of the amorphous semiconductor film into the crystalline semiconductor seed layer to form a heavily doped buried semiconductor layer of the 3-layer semiconductor structure.
The solid phase epitaxy may be performed during about 6-48 hours at temperatures in the range of about 500 to 65O0C. The seed layer may be fabricated with a method chosen from a group consisting of aluminium-induced crystallisation, metal-induced crystallisation, solid-phase crystallisation or laser-induced crystallisation.
The method may comprise forming a dielectric barrier layer on the substrate or superstrate, and forming the 3-layer diode structure on the dielectric barrier layer.
The dielectric barrier layer may comprise a material chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
The 3-layer diode structure may comprise a material chosen from a group consisting of silicon, germanium, or an alloy of silicon and germanium.
The sacrificial dielectric overlayer may be chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
The sacrificial dielectric overlayer may be deposited using a method chosen from a group consisting of PECVD, sputtering and evaporation.
The heavily doped semiconductor layer may be formed by diffusing the n or p-type atoms from the sacrificial dielectric overlayer using rapid thermal annealing performed in a temperature range of about 800-1050 0C for periods in the range of about 1 sec to 15 minutes.
The method may further comprise exposing the 3-layer diode structure to atomic hydrogen after the removal of the sacrificial dielectric overlayer at a temperature in the range of about 350 to 6500C.
The sacrificial dielectric overlayer may be deposited in-situ without breaking the vacuum after the final step of the formation of the lightly or undoped amorphous semiconductor structure. The doping of the lightly doped or undoped semiconductor layer may be lower than about 1018 cm"3, and the doping of the heavily doped buried semiconductor layer is greater than about 1018 cm"3.
A surface on which the 3-layer semiconductor structure may be supported is textured to assist light trapping in the 3-layer semiconductor structure.
In accordance with a second aspect of the present invention there is provided a thin-film crystalline semiconductor 3-layer diode structure formed on a foreign supporting substrate or superstrate using a method as defined in the first aspect.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:
Figs. 1 to 5 are schematic cross-sectional drawings illustrating manufacture of devices utilizing solid phase crystallisation (SPC). Figs. 6 to 10 are schematic cross-sectional drawings illustrating manufacture of devices utilizing solid phase epitaxy (SPE).
DETAILED DESCRIPTION One described method uses a sacrificial doped dielectric overlayer on an amorphous n+π (or p+π) 2-layer structure with a subsequent crystallisation of the amorphous 2-layer stack by SPC at about 6000C. The third, heavily doped layer of the n+πp+ (or p+πn+) thin-film crystalline diode structure is generated by dopant diffusion from the doped overlayer into the underlying crystalline silicon layer during a separate rapid thermal anneal (RTA) at high temperatures in the about 800-1050 0C range. The RTA is followed by a defect passivation treatment using atomic hydrogen in the about 500-620 0C range, whereby the doped overlayer (doped silicon oxide) is removed with a hydrofluoric acid dip just prior to the hydrogenation treatment. A large fraction of the dopants in the third layer is electronically active after the hydrogenation treatment. In another described method, a single layer of π-type (i.e., lightly doped or undoped) amorphous silicon is deposited onto a hydrogen-terminated heavily doped crystalline silicon seed layer on a glass sheet, followed by the deposition of the sacrificial doped dielectric overlayer. Due to the presence of the crystalline seed layer (which provides the nucleation surface), the crystallisation of the amorphous silicon layer in this case occurs via solid-phase epitaxy (SPE). For a detailed description of SPE of amorphous silicon layers reference is made to Widenborg et alia ["Epitaxial thickening of AIC poly-Si seed layers on glass by solid phase epitaxy", Journal of Crystal Growth, Vol. 276, pp. 19-28 (2005)], the content of which is hereby incorporated by cross reference. The required third, heavily doped layer is again created by dopant diffusion from the sacrificial doped overlayer into the underlying crystalline silicon layer during a rapid thermal anneal (RTA) at high temperatures in the about 800-1050 0C range. The sacrificial doped overlayer (doped silicon oxide) is removed with a hydrofluoric acid dip just prior to a treatment with atomic hydrogen in the about 500-620 0C range. A large fraction of the dopants in the third layer is electronically active after the hydrogenation treatment.
Manufacture of devices utilising SPC will now be described with reference to Figs. 1 to 5.
A thin dielectric barrier layer 12 is deposited onto a foreign supporting material 11 , as shown in Fig. 1. It should be noted that the foreign supporting material 11 can be suitably textured to assist light trapping in the finished 3-layer semiconductor structure. For the sake of clarity the texture has been omitted in Figs 1 to 5. The dielectric barrier layer 12 comprises a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials. For example, in the case of glass superstrates, a SiN film with a thickness of about 70 nm can be deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) methods using a gas mixture of silane, ammonia and nitrogen. Next, a 2-layer stack (13, 14) of amorphous semiconductor material is deposited onto the thin dielectric layer 12, where the first layer 13 is heavily doped whereas the second layer 14 is lightly doped or intrinsic, as shown in Fig. 2. The layers 13 and 14 may comprise amorphous semiconductor material such as silicon, germanium or an alloy of silicon and germanium. For example, amorphous silicon can be deposited by PECVD methods using a gas mixture of silane and doped hydrogen with a deposition temperature of about 375 - 4250C range, where the first layer 13 is heavily doped, in the range of about 1x1018 to 1x1021 cm"3 phosphorus atoms, with a preferred phosphorus concentration of about 1x1020 cm"3 and a preferred thickness of about 50 nm. The second layer 14 may be lightly p-type doped by boron in the range of about 1x1015 to 1x1018 cm"3, with a preferred boron concentration of about 5x1016 and a preferred thickness of about 1500 nm.
A thin doped dielectric layer 15 is then deposited onto the amorphous semiconductor layer 14, as shown in Fig. 3. The dielectric layer 15 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials. The dielectric layer 15 can be deposited utilising deposition techniques such as plasma enhanced chemical vapour deposition (PECVD), sputtering or evaporation. In one example, the dielectric layer 15, with a thickness of about 70 nm, comprises a boron doped (p-type) silicon oxide containing trace amount of carbon, deposited via radio-frequency (13.56 MHz) PECVD (RF PECVD), in a standard parallel-plate configuration, at a substrate temperature of 300-3500C. The gas mixture used in one example consists of (gas flow in brackets): silane (about 1 seem), 0.5% trimethylboron in hydrogen (about 2 seem), nitrous oxide (about 150 seem), and nitrogen (about 150 seem). The deposition pressure was about 150 mTorr and the power density was about 0.025 W/cm2. The resulting deposition rate was about 10 nm/min. In one example, the dielectric layer 15 is deposited in-situ without breaking the vacuum in a vacuum deposition chamber after the amorphous semiconductor deposition step (compare Fig. 2).
The device 20 is then subjected to a thermal anneal where the amorphous semiconductor layers 13 and 14 crystallise via SPC and where the doping atoms in the exposed thin dielectric layer 15 do not diffuse significantly into the semiconductor layers 13 and 14. In one example, the crystallisation is performed during about 6-48 hours at temperatures in the range of about 500-6500C. In the described example, this thermal annealing step is performed in a nitrogen-purged atmospheric-pressure furnace. This is followed by subjecting the device 20 to a rapid thermal anneal (RTA) treatment at high temperature whereby doping atoms in the exposed thin dielectric layer 15 diffuse significantly into the crystalline semiconductor layer 14 and thereby create a third doped layer 16 located between layers 15 and 14, as shown in Fig. 4. In one example, the RTA is performed in a temperature range of about 800-10500C for a period in the range of about 1 second to 15 minutes.
Subsequently, the thin doped dielectric layer 15 is removed and the device 21 subjected to an atomic hydrogen treatment, as shown in Fig. 5. In one example, the exposure to atomic hydrogen is performed at a temperature in the range of about 350- 650°C.
Several 1.5 micron thick silicon solar cell devices fabricated using the method described above with reference to Figs. 1 to 5 have been fabricated by PECVD (plasma- enhanced chemical vapour deposition), utilising a borosilicate glass sheet 11, a silicon nitride layer 12, a heavily phosphorus doped amorphous-Si:H layer 13, a lightly boron doped amorphous-Si:H layer 14, and a heavily boron doped silicon (carbon) oxide layer 15 which was deposited in-situ on the base layer 14. The amorphous silicon layers 13 and 14 were then crystallised during about 15 hours at about 6000C. The devices were then subjected to an RTA treatment at about 9000C for 5 minutes, during which the third, heavily doped layer 16 was created by dopant diffusion. The sacrificial boron-doped silicon (carbon) oxide layer 15 was then removed by etching in hydrofluoric acid, followed by a hydrogenation process at about 6100C glass temperature for about 15 min duration.
The resulting p+ layer (layer 16) is heavily doped with boron, as confirmed by measured sheet resistances as low as 1000 Ohms/square and hot probe measurements for determination of the doping polarity. Electrical characterization of the fabricated p-n junction solar cells showed that the described sacrificial doped dielectric overlayer method for forming the heavily doped back surface layer ("back surface field" (BSF) layer) has a superior quality compared to devices with a conventionally grown BSF layer. The open circuit voltage difference between solar cells with the described diffused BSF layer and an equivalent device where the only difference is a conventionally grown BSF layer, was a significant 40-50 mV, with a higher voltage for the described diffused BSF layer. Solar cells with the described BSF layer formed via the sacrificial doped dielectric overlayer method had a 1-sun open circuit voltage of over 500 mV and the cells were negligibly affected by parasitic ideality factor n = 2 recombination, enabling potentially very high fill factor (and hence high solar energy conversion efficiency). One metallised solar cell with a diffused BSF layer obtained a fill factor of over 70%, which is an excellent value for poly-Si solar cells on glass.
Manufacture of devices utilising SPE will now be described with reference to Figs. 6 to 10.
A thin dielectric barrier layer 112 is deposited onto a foreign supporting material 111 and a thin, large-grained heavily doped (>1018 cm"3) crystalline semiconductor layer 117 is formed on the layer 112, as shown in Fig. 6. It should be noted that the foreign supporting material 112 can be suitably textured to assist light trapping in the finished 3- layer semiconductor structure. For the sake of clarity the texture has been omitted in Figs 6 to 10. It will be appreciated by the person skilled in the art that formation of a thin (« 1 micron) crystalline semiconductor layer on a foreign substrate is much easier than the formation of a thick (> 1 micron) crystalline layer using existing deposition techniques. Specifically, the crystalline semiconductor layer or seed layer 117 can be fabricated utilising techniques such as aluminium-induced crystallisation, metal-induced crystallisation, solid-phase crystallisation, or laser-induced crystallisation. The dielectric barrier layer 112 comprises a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials. For example, a SiN film with a thickness of 70 nm ± 10 nm can be deposited by PECVD methods using a gas mixture of silane, ammonia and nitrogen. Next, a clean and hydrogen-terminated seed layer surface is created, followed by the deposition of a lightly doped amorphous semiconductor layer 118, as shown in Fig. 7. A clean hydrogen-terminated silicon surface is, for example, realised by the steps of: (i) immersing the silicon surface for 10 minutes in a fresh 1 :1 mixture of hydrogen peroxide and sulfuric acid; (ii) rinsing the surface in de-ionized water; (iii) immersing the surface of the crystalline silicon layer 117 into a 5% hydrofluoric acid solution until the surface is hydrophobic followed by a rinse in deionized water. The crystalline silicon layer 117 with the clean hydrogen-terminated silicon surface and its supporting layer 111 and 112 is loaded into the vacuum machine within about 60 minutes of completion of the cleaning step. The layer 118 may comprise amorphous semiconductor material such as silicon, germanium or an alloy of silicon and germanium. For example, amorphous silicon can be deposited by PECVD methods using a gas mixture of silane and doped hydrogen with a deposition temperature of about 375 - 425°C range, where the layer 118 is lightly p-type doped with boron in the range of about 1x1015 to 1x1018 cm"3, with a preferred boron concentration of about 5x1016 and a preferred thickness of about 1500 nm.
A thin doped dielectric layer 119 is then deposited onto the amorphous semiconductor layer 118, as shown in Fig. 8. The dielectric layer 119 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon carbide or a combination or an alloy of those materials. The dielectric layer 119 can be deposited utilising deposition techniques such as PECVD, sputtering or evaporation. In one example, the dielectric layer 119, with a thickness of about 70 nm, comprises a boron doped (p-type) silicon oxide, containing trace amount of carbon, deposited via radio frequency (13.56
MHz) PECVD (RF PECVD), in a standard parallel-plate configuration, at a substrate temperature of about 300-3500C. The gas mixture used in our experiments consisted of
(gas flow in brackets): silane (about 1 seem), 0.5% trimethylboron in hydrogen (about 2 seem), nitrous oxide (about 150 seem), and nitrogen (about 150 seem). The deposition pressure was about 150 mTorr and the RF power density was about 0.025 W/cm2, resulting in a deposition rate of about 10 nm/min. In one example, the dielectric layer
119 is deposited in-situ without breaking the vacuum in a vacuum deposition chamber after the amorphous semiconductor deposition step (compare Fig. 7).
The device 121 is then subjected to a thermal anneal where the amorphous semiconductor layer 118 crystallises via SPE and where the doping atoms in the exposed thin dielectric layer 119 do not diffuse significantly into the semiconductor layer 118. In one example, the crystallisation is performed during about 6-48 hours at temperatures in the range of about 500-6500C.
This is followed by subjecting the device 121 to a rapid thermal anneal (RTA) treatment at high temperature whereby doping atoms in the thin dielectric layer 119 diffuse significantly into the crystalline semiconductor layer 118 and create a third, heavily doped layer 120 located between layers 119 and 118, as shown in Fig. 9. In one example, the RTA is performed in a temperature range of about 800-10500C for period in the range of about 1 second to 15 minutes.
Subsequently, the thin doped dielectric layer 119 is removed and the device 122 subjected to an atomic hydrogen treatment, as shown in Fig. 10. In one example, the exposure to atomic hydrogen is performed at a temperature in the range of about 350- 65O0C.
Solar cells on glass fabricated using the method described above with reference to Figs. 6 to 10 have also been fabricated and have also demonstrated superior open circuit voltages compared to the conventional approach for forming the back surface field (BSF) layer.
In modification of the embodiment described above with reference to Figures 6 to 10, instead of a heavily doped (>1018 cm"3) crystalline semiconductor seed layer, an intrinsic (i.e. undoped) seed layer, or a seed layer with low doping level and/or undesirable doping polarity is formed. The amorphous semiconductor layer 118 can be deposited as a 2 doping level structure in the modified embodiment, whereas a thin region (thickness about 50nm± 20 nm) of layer 118 adjacent to the seed layer contains an excess of the doping atoms (n or p-type with a concentration in the range of 5x1019 to 1x1021 cm"3) dedicated for the seed layer. During the RTA step, the excess dopants from the adjacent region in layer 118 diffuses into the seed layer 117 and form the desired doping level and polarity in the seed layer, simultaneously as the formation of the heavily doped BSF layer 120 as described above. The excess doping in layer 118 adjacent to the seed layer has opposite doping polarity to the BSF layer 120.
The described methods provide fabrication of a 3-layer stack (n+πp+ or p+πn+) of crystalline semiconductor material, via SPC or SPE, where the crystallisation of the entire stack occurs only from one side. This can provide an improved grain size and lower defect density compared to crystallisation of the entire 3-layer stack from both sides. Also, enhanced dopant diffusion from the doped dielectric along preferred regions, for example grain boundaries, in the crystalline layer may provide a reduced recombination rate in the fabricated diodes.
As amorphous silicon is significantly more sensitive than crystalline silicon with regards to exposure to contamination, an additional benefit of the described methods is that the doped dielectric layer deposited on the amorphous semiconductor also functions as a protective diffusion barrier against atmospheric contamination during the crystallisation and sample handling.
Furthermore, the doped dielectric layer prevents contaminants from the RTA chamber to diffuse into the crystalline semiconductor during the RTA process, which usually is a large source of contamination due to the very high temperature used during the RTA process.
The described methods enable the realisation of n+πp+ (or p+πn+) homojunction crystalline thin-film diode structures on glass with a streamlined manufacturing process while maintaining a high material quality. This offers significant potential for the realisation of more cost-effective and yet efficient thin-film solar cells and modules.
It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.

Claims

1. A method of fabricating a thin-film crystalline semiconductor 3-layer diode structure on a foreign supporting substrate or superstrate, the method comprising: depositing a sacrificial dielectric overlayer containing n or p-type dopant atoms on an exposed amorphous lightly doped or undoped semiconductor layer of a 2-layer semiconductor structure formed on the substrate or superstrate; crystallising the amorphous lightly doped or undoped semiconductor layer, forming a heavily doped semiconductor layer by diffusing the n or p-type atoms from the sacrificial dielectric overlayer into a portion of the crystallised lightly doped or undoped semiconductor layer, whereby the 3-layer diode structure is formed; and removing the sacrificial dielectric overlayer from the 3-layer diode structure.
2. The method as claimed in claim 1 , wherein the 2-layer semiconductor structure comprises the amorphous lightly doped or undoped semiconductor layer and an amorphous heavily doped buried semiconductor layer, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises crystallising the heavily doped buried semiconductor layer via solid phase crystallisation.
3. The method as claimed in claim 2, wherein the solid phase crystallisation is performed during about 6-48 hours at temperatures in the range of about 500 to 6500C.
4. The method as claimed in claim 1 , further comprising forming the 2- layer semiconductor structure by forming a crystalline semiconductor seed layer on the substrate or superstrate, preparing a hydrogen-terminated seed layer surface on the crystalline semiconductor seed layer, and depositing the lightly doped or undoped amorphous layer on the seed layer surface, and the step of crystallising the amorphous lightly doped or undoped semiconductor layer comprises solid phase epitaxy.
5. The method as claimed in claim 4, wherein the crystalline semiconductor seed layer is heavily doped with a polarity of the opposite type compared to the heavily doped semiconductor layer.
6. The method as claimed in claim 4, wherein the crystalline semiconductor seed layer is undoped or doped with a same polarity as the heavily doped semiconductor layer, and forming the 2-layer semiconductor structure comprises depositing an amorphous semiconductor film on the seed layer surface such that a first portion of the amorphous semiconductor film adjacent the crystalline semiconductor seed layer is heavily doped with a polarity of an opposite type compared to the heavily doped semiconductor layer, and such that a second portion of the amorphous semiconductor film is the amorphous lightly doped or undoped semiconductor layer, and the step of forming the heavily doped semiconductor layer further comprises diffusing dopant atoms from the first portion of the amorphous semiconductor film into the crystalline semiconductor seed layer to form a heavily doped buried semiconductor layer of the 3-layer semiconductor structure.
7. The method as claimed in any one of claims 4 to 6, wherein the solid phase epitaxy is performed during about 6-48 hours at temperatures in the range of about 500 to 6500C.
8. The method as claimed in any one of claims 4 to 7, wherein the seed layer is fabricated with a method chosen from a group consisting of aluminium-induced crystallisation, metal-induced crystallisation, solid-phase crystallisation or laser-induced crystallisation.
9. The method as claimed in any one of the preceding claims, comprising forming a dielectric barrier layer on the substrate or superstrate, and forming the 3-layer diode structure on the dielectric barrier layer.
10. The method as claimed in claim 9, wherein the dielectric barrier layer comprises a material chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
11. The method as claimed in any one of the preceding claims, wherein the 3-layer diode structure comprises a material chosen from a group consisting of silicon, germanium, or an alloy of silicon and germanium.
12. The method as claimed in any one of the preceding claims, wherein the sacrificial dielectric overlayer is chosen from a group consisting of silicon nitride, silicon oxide, silicon carbide and a combination or an alloy thereof.
13. The method as claimed in any one of the preceding claims, wherein the sacrificial dielectric overlayer is deposited using a method chosen from a group consisting of PECVD, sputtering and evaporation.
14. The method as claimed in any one of the preceding claims, wherein the heavily doped semiconductor layer is formed by diffusing the n or p-type atoms from the sacrificial dielectric overlayer using rapid thermal annealing performed in a temperature range of about 800-1050 0C for periods in the range of about 1 sec to 15 minutes.
15. The method as claimed in any one of the preceding claims, further comprising exposing the 3-layer diode structure to atomic hydrogen after the removal of the sacrificial dielectric overlayer at a temperature in the range of about 350 to 65O0C.
16. The method as claimed in any one of the preceding claims, wherein the sacrificial dielectric overlayer is deposited in-situ without breaking the vacuum after the final step of the formation of the lightly or undoped amorphous semiconductor structure.
17. The method as claimed in any one of the preceding claims, wherein the doping of the lightly doped or undoped semiconductor layer is lower than about 1018 cm'3, and the doping of the heavily doped buried semiconductor layer is greater than about 1018 cm"3.
18. The method as claimed in any one of the preceding claims, wherein a surface on which the 3-layer semiconductor structure is supported is textured to assist light trapping in the 3-layer semiconductor structure.
19. A thin-film crystalline semiconductor 3-layer diode structure formed on a foreign supporting substrate or superstrate using a method as claimed in any one of claims 1 to 18.
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US9911781B2 (en) 2009-09-17 2018-03-06 Sionyx, Llc Photosensitive imaging devices and associated methods
US9673243B2 (en) 2009-09-17 2017-06-06 Sionyx, Llc Photosensitive imaging devices and associated methods
CN102947953A (en) 2010-03-24 2013-02-27 西奥尼克斯公司 Devices having enhanced electromagnetic radiation detection and associated methods
US8692198B2 (en) 2010-04-21 2014-04-08 Sionyx, Inc. Photosensitive imaging devices and associated methods
CN106449684B (en) 2010-06-18 2019-09-27 西奥尼克斯公司 High speed photosensitive device and correlation technique
US9496308B2 (en) 2011-06-09 2016-11-15 Sionyx, Llc Process module for increasing the response of backside illuminated photosensitive imagers and associated methods
WO2013010127A2 (en) 2011-07-13 2013-01-17 Sionyx, Inc. Biometric imaging devices and associated methods
US9064764B2 (en) 2012-03-22 2015-06-23 Sionyx, Inc. Pixel isolation elements, devices, and associated methods
WO2014151093A1 (en) 2013-03-15 2014-09-25 Sionyx, Inc. Three dimensional imaging utilizing stacked imager devices and associated methods
US9209345B2 (en) 2013-06-29 2015-12-08 Sionyx, Inc. Shallow trench textured regions and associated methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998057372A1 (en) * 1997-06-10 1998-12-17 The Board Of Trustees Of The Leland Stanford Junior University LATERALLY CRYSTALLIZED TFTs AND METHODS FOR MAKING LATERALLY CRYSTALLIZED TFTs
US20040102057A1 (en) * 2002-11-26 2004-05-27 Liu Mark Y. Sacrificial annealing layer for a semiconductor device and a method of fabrication
WO2005119782A1 (en) * 2004-06-04 2005-12-15 Newsouth Innovations Pty Limited Thin-film solar cell interconnection

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998057372A1 (en) * 1997-06-10 1998-12-17 The Board Of Trustees Of The Leland Stanford Junior University LATERALLY CRYSTALLIZED TFTs AND METHODS FOR MAKING LATERALLY CRYSTALLIZED TFTs
US20040102057A1 (en) * 2002-11-26 2004-05-27 Liu Mark Y. Sacrificial annealing layer for a semiconductor device and a method of fabrication
WO2005119782A1 (en) * 2004-06-04 2005-12-15 Newsouth Innovations Pty Limited Thin-film solar cell interconnection

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ABERLE A.G. ET AL.: "Recent advances in polycrystalline silicon thin-film solar cells on glass at UNSW", PHOTOVOLTAIC SPECIALISTS CONFERENCE, 2005. CONFERENCE RECORD OF THE THIRTY-FIRST IEEE, 3 January 2005 (2005-01-03) - 7 January 2005 (2005-01-07), Retrieved from the Internet <URL:http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1488272> *
ABERLE A.G.: "Progress with polycrystalline silicon thin-film solar cells on glass at UNSW", JOURNAL OF CRYSTAL GROWTH, vol. 287, no. 2, 25 January 2006 (2006-01-25), pages 386 - 390, XP028016246, DOI: doi:10.1016/j.jcrysgro.2005.11.050 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011029706A3 (en) * 2009-09-09 2011-09-15 International Business Machines Corporation Method of controlling the composition of a photovoltaic thin film
GB2485494A (en) * 2009-09-09 2012-05-16 Ibm Method of controlling the composition of a photovoltaic thin film
CN102484169A (en) * 2009-09-09 2012-05-30 国际商业机器公司 Method Of Controlling The Composition Of A Photovoltaic Thin Film
GB2485494B (en) * 2009-09-09 2014-01-15 Ibm Method of controlling the composition of a photovoltaic thin film

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