WO2007146970A3 - Page processing circuits, devices, methods and systems for secure demand paging and other operations - Google Patents

Page processing circuits, devices, methods and systems for secure demand paging and other operations Download PDF

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Publication number
WO2007146970A3
WO2007146970A3 PCT/US2007/071058 US2007071058W WO2007146970A3 WO 2007146970 A3 WO2007146970 A3 WO 2007146970A3 US 2007071058 W US2007071058 W US 2007071058W WO 2007146970 A3 WO2007146970 A3 WO 2007146970A3
Authority
WO
WIPO (PCT)
Prior art keywords
systems
devices
operations
methods
page processing
Prior art date
Application number
PCT/US2007/071058
Other languages
French (fr)
Other versions
WO2007146970A8 (en
WO2007146970A2 (en
Inventor
Gregory Remi Phillippe Conti
Steven C Goss
Original Assignee
Texas Instruments Inc
Gregory Remi Phillippe Conti
Steven C Goss
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP06291006A external-priority patent/EP1870813B1/en
Application filed by Texas Instruments Inc, Gregory Remi Phillippe Conti, Steven C Goss filed Critical Texas Instruments Inc
Publication of WO2007146970A2 publication Critical patent/WO2007146970A2/en
Publication of WO2007146970A8 publication Critical patent/WO2007146970A8/en
Publication of WO2007146970A3 publication Critical patent/WO2007146970A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transceivers (AREA)

Abstract

A page processing circuit (Fig. 9, 1040) includes a memory (Fig. 9, 1034) for pages, a processor (Fig. 9, 1030) coupled to the memory, and a page wiping advisor circuit coupled to the processor and operable to prioritize pages based both on page type and usage statistics (Fig. 9, 2730). Processes of manufacture, processes of operation, circuits, devices, telecommunications products, wireless handsets and systems are also disclosed.
PCT/US2007/071058 2006-06-16 2007-06-13 Page processing circuits, devices, methods and systems for secure demand paging and other operations WO2007146970A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP06291006.2 2006-06-16
EP06291006A EP1870813B1 (en) 2006-06-19 2006-06-19 Page processing circuits, devices, methods and systems for secure demand paging and other operations
US11/426,598 2006-06-27
US11/426,598 US20070294494A1 (en) 2006-06-16 2006-06-27 Page processing circuits, devices, methods and systems for secure demand paging and other operations

Publications (3)

Publication Number Publication Date
WO2007146970A2 WO2007146970A2 (en) 2007-12-21
WO2007146970A8 WO2007146970A8 (en) 2008-08-21
WO2007146970A3 true WO2007146970A3 (en) 2008-11-13

Family

ID=38832984

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/071058 WO2007146970A2 (en) 2006-06-16 2007-06-13 Page processing circuits, devices, methods and systems for secure demand paging and other operations

Country Status (1)

Country Link
WO (1) WO2007146970A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128713A (en) * 1997-09-24 2000-10-03 Microsoft Corporation Application programming interface enabling application programs to control allocation of physical memory in a virtual memory system
US6834329B2 (en) * 2001-07-10 2004-12-21 Nec Corporation Cache control method and cache apparatus
US6910106B2 (en) * 2002-10-04 2005-06-21 Microsoft Corporation Methods and mechanisms for proactive memory management

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128713A (en) * 1997-09-24 2000-10-03 Microsoft Corporation Application programming interface enabling application programs to control allocation of physical memory in a virtual memory system
US6834329B2 (en) * 2001-07-10 2004-12-21 Nec Corporation Cache control method and cache apparatus
US6910106B2 (en) * 2002-10-04 2005-06-21 Microsoft Corporation Methods and mechanisms for proactive memory management

Also Published As

Publication number Publication date
WO2007146970A8 (en) 2008-08-21
WO2007146970A2 (en) 2007-12-21

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