WO2007113091A1

WO2007113091A1 - Control device having microcontrollers for simultaneously processing tasks

Info

Publication number: WO2007113091A1
Application number: PCT/EP2007/052437
Authority: WO
Inventors: Uwe Hartmann; Klaus-Peter Mattern; Dirk Ortlinghaus; Bernd Kuehner; Nils Grunwald
Original assignee: Robert Bosch Gmbh
Priority date: 2006-03-30
Filing date: 2007-03-15
Publication date: 2007-10-11
Also published as: DE102006015219A1

Abstract

The control device according to the invention has at least one first microcontroller (2) and at least one second microcontroller (4). In this case, the at least one second microcontroller (4) is connected to the at least one first microcontroller (2) in order to simultaneously process tasks and is thus connected in a task-synchronous manner, wherein software is swapped between the at least one first microcontroller (2) and the at least one second microcontroller (4) for temporally staggered tasks.

Description

description

title

CONTROL UNIT WITH MICROCONTROLLERS FOR TEMPORARILY TASKS

The invention relates to a control device, a method for operating a control device, a computer program and a computer program product.

State of the art

The increasing demands on the functionality of high-quality systems for electronic stability programs (ESP) can not be fulfilled with currently available microcontrollers. The largest and most powerful control device currently offers only 768 KB read-only memory (ROM). However, there is a project with a stability program controller that will require a storage capacity of up to 1206 kB. A known control device offers only a storage capacity of 1024 kB and will be available in the future. Thus, it is necessary to develop concepts with two microcontrollers covering the read-write requirements for the project.

For linking microcontrollers, the so-called VAFS concept is known, whereby VAFS stands for "Value Added Function Server", a value-added functional server. When implementing the VASF concept, it has hitherto been preferred to provide a swapping of functions in the 20 ms task. A rearrangement of existing or new functions to the VAFS concept should be a requirement for a distribution of software between an AS (Algorithm Server) and a VAFS-trained microcontroller. Additional relocation of variant coded parameters from the AS to the VASF should reduce the memory requirements of the AS's microcontroller. A main objective is therefore that transfer functions or transfer parameters from the AS to the VAFS have no influence on the functions of a system designed as a controller, for example, and the time behavior of signals for functions do not change.

Disclosure of the invention

The invention relates to a control device having the features of patent claim 1, a method having the features of patent claim 7, a computer program having the features of patent claim 10 and a computer program product having the features of patent claim 11.

The control unit according to the invention has at least one first microcontroller and at least one second microcontroller. In this case, the at least one second microcontroller is connected to the at least one first microcontroller for the simultaneous processing of tasks and thus task synchronously, whereby a software rearrangement takes place between the at least one first microcontroller and the at least one second microcontroller for time-shifted tasks.

The method according to the invention is provided for operating a control device which has at least one first microcontroller and at least one second microcontroller, wherein the at least one second microcontroller is connected to the at least one first microcontroller for simultaneous processing of tasks and thus in a task-synchronous manner. When performing the procedure, a software migration is performed between the micro-controllers for time-shifted tasks.

The invention further relates to a computer program with program code means in order to carry out all the steps of a method according to the invention when the computer program is executed on a computer or a corresponding computing unit, in particular a control unit according to the invention.

The invention also relates to a computer program product with program code means which are stored on a computer-readable data carrier in order to perform all the steps of a method according to the invention when the computer program on a computer or a corresponding computing unit, in particular a control device according to the invention, is executed.

The invention provides a concept for the functional transfer or so-called swapping of functions of software, in particular software modules, which can be designed as tasks or processes or tasks with different time periods, between at least two microcontrollers or corresponding arithmetic units.

With this software function transfer concept, in the following short SWFS concept, a disadvantage of the VAFS concept, namely a delay by one task cycle, can be avoided. The SWFS concept supports a 20 ms task in the first microcontroller, in particular an AS or algorithm server, and a 40 ms task in the second microcontroller, which is preferably designed here as VAFS or Value Added Function Server. A 20 ms task within the VAFS should be used for functions that run as VAFS tasks in the VAFS concept. The 40 ms task should be used for the functions of the software that can run in the 40 ms task. This corresponds to a migration of the complete 40 ms task of the software.

The SWFS concept can use the same communication infrastructure as the VAFS concept. However, unlike the VAFS concept, rearrangement of the 40 ms tasks from the AS to the VAFS has no effect on a time span and / or timing of signals of the functions. Because of this advantageous timing, there is no change in the timing of the 40 ms task with respect to other tasks. Nor does the timing of the functions in the VAFS change as compared to the VAFS concept.

The rearrangement of the functions only affects software that is independent of the hardware and has clear interfaces to other software parts within other tasks. Within ESP ECUs (ESP: Electronic Stability Program for Vehicles), this allows a simple relocation of all software functions of the 40 ms tasks without changing the time periods and / or time divisions. - A -

In an embodiment, all codes of the functions that run in the 40 ms task are assigned to the VAFS. Variables of a task copy, which in the present example may be interface variables between the 40 ms task and other tasks, can be transferred from the AS to the second microcontroller designed as a VASF via a so-called SPI (Serial Peripheral Interface) and thus via a serial interface copied back and forth and thus also be relocated. The VAS F communications interface software (VAFSCIF) already in use is capable of such copies if all the data of a task copy of the 40 ms task is available in one cycle. In addition, a first variable structure is provided for communication from the AS to the VASF and a second variable structure for communication from the VASF to the AS. Such structures are referred to in this context as data transfer functions.

A software execution sequence may be split into 40-ms periods, each referred to as a cycle. In each cycle 5-ms-tasks (k to k + 7) are performed eight times. 10 ms tasks are executed four times (k to k + 3), accordingly, 20 ms tasks are performed twice (k, k + 1) and the 40 ms tasks are performed only once. Data for a task copy of the 40 ms task is executed by a first task execution of a faster task within each cycle. This means that the data is formed by the first 5 ms task (k), the first 10 ms task (k) and the first 20 ms task (k). At the end of the first 20 ms task, the 40 ms task starts, if assigned to the AS. This is the earliest time that transmission of data to the VAFS can begin. However, depending on the execution time of the 5 ms, 10 ms and 20 ms tasks, this can also happen very early in the cycle, so it is conceivable that a previous 20 ms task within the VAFS is not yet completed is. In this case, the SPI is not yet available for data transfer. The last time the first 20 ms task must be completed is the start of the fourth 5 ms task (k + 3) as soon as the task copy data of the first 20 ms task reaches the 40 ms Task are copied.

Thus, the beginning of a data transfer and thus triggering of the 40 ms task in the VAFS task should take place during the fourth 5 ms task (k + 3). To these At this time, the data transfer of the last VAFS tasks and the first 20 ms task must be completed.

In the VAFS, an execution of the 40 ms task is started as soon as the data transfer via the SPI is completed by the first microcontroller designed as AS. A task copy routine reads the data from the first 5 ms task, the first 10 ms task and the first 20 ms task of the current cycle (k). As soon as the 40 ms task is completed, the data for the first 5 ms task, the first 10 ms task and the first 20 ms task of the next ASW (or algorithm software) cycle are stored in written a data transfer buffer. After the data has been transmitted to the AS via the SPI, each first task of the subsequent cycle may read the associated data at the same time as if the 40 ms task had run on the AS. Thus, there are no time differences.

In order to incorporate the existing VAFS concept into the present invention, which requires a 20 ms task in the VAFS for OEM functions, ie functions of a manufacturer of original equipment, the additions described below are necessary. The 40 ms task in the VAFS runs completely concurrently with a second part of a cycle in the AS. This means that the 40 ms task starts at the beginning of the fourth 5 ms task and must be completed before the first 5 ms task of the next cycle begins. Thus, a 20 ms period remains in the first half of this cycle. In order to use this 20 ms period for the 20 ms task in the VAFS, especially in the first 5 ms task, data transmission to the VAFS is also started. It only updates data for the functions in the 20 ms VAFS task. Once the data transfer is complete, the 20 ms task is started in the VAFS.

Once completed, the data is transferred back to the AS via the SPI. This sequence must be completed before the fourth 5 ms task begins. In the fourth 5 ms task, the data of the 20 ms task in the VAFS is read and new data is provided for the next 20 ms task in the VAFS. This data is stored in the data transfer buffer along with the task copy data of the 40 ms task. When the fourth 5 ms task transfers the data to the VAFS, it transfers the data for the 20 ms task as well as for the 40 ms task. ms task at the same time. On the VAFS side, the 40 ms task is executed first followed by the 20 ms tasks. At the end of the 20 ms task, both the output data of the 40 ms task and the output data of the 20 ms VAFS task are transmitted back to the AS via the SPI.

Within the VAFS, the following sequence is then executed repetitively every 40 seconds per cycle:

20 ms VAFS task => paged 40 ms task of the AS => 20 ms VAFS task.

The present invention provides further computer resources in a further embodiment when a second 40 ms task is installed on the AS. This is phase shifted 20 ms to the first 40 ms ASW task. In this case, the second 40 ms task will be executed before the first 20 ms task in the VAFS so that the following sequence will be executed repetitively every 40 ms:

40 ms VAFS task => 20 ms VAFS task => 40 ms paged 40 ms task of the AS => 20 ms VAFS task.

In a device or a system with software function redistribution, a software version that can be executed on two microcontrollers can be provided with the invention. Accordingly, in the control device or in general a device in which functional transfer of software is implemented, the software for the AS and the VAFS must be coordinated or match each other.

In a further embodiment, different actions can be performed in each software cycle. For example, the first 5 ms task can read data from the last 20 ms VAFS task and the last 40 ms task. In addition, the first 5 ms task can begin data transfer to the VAFS with data for 20 ms VAFS task functions and 40 ms VAFS task functions. The fourth 5 ms task can read data from the last 20 ms VAFS task and the last 40 ms VAFS task. Furthermore, the fourth 5 ms task may begin data transmission to the VAFS with data for functions of the 20 ms VAFS task and the 40 ms task. It should be emphasized that the overlay tion of the functions of the 40 ms task from the AS to the VAFS has no influence on the time response of the signal of the functions.

Brief description of the drawings

FIG. 1 shows a schematic representation of the time behavior of an embodiment of two microcontrollers when carrying out a first variant of the method according to the invention.

Figure 2 shows a schematic representation of the memory space allocation of an embodiment of two microcontrollers within an embodiment of a control device according to the invention when carrying out a second variant of the method according to the invention.

Embodiments of the invention

FIG. 1 shows a schematic representation of the time behavior of a first microcontroller 2 embodied as an algorithm server (AS) and a second microcontroller 4 designed as a function server with additional values (Value Added Function Server, VASF), which are interconnected via a serial peripheral interface 6 (SPI) , The components of FIG. 1 are plotted along a time axis 8, which in this embodiment is subdivided into 5 ms intervals. Within a current cycle, which lasts 40 ms in this exemplary embodiment, different, interconnected software modules are executed in the microcontrollers 2, 4. The software modules interact by transferring task copies and swapping software and / or functions.

Such software modules are each represented from left to right and thus executed within the current cycle in succession to tasks that comprise different time periods. In a first row, these are a first 5 ms task 10, a second 5 ms task 12, a third 5 ms task 14, a fourth 5 ms task 16, a fifth 5 ms task 18 , a sixth 5 ms task 20, a seventh 5 ms task 22 and an eighth 5 ms task 24, a ninth 5 ms task 26 is the first 5 ms task of the next Cycle. In addition to the eight 5 ms tasks 10, 12, 14, 16, 18, 20, 22, 24 are shown during the current cycle, here in the second row, a first 10 ms task 28, a second 10 ms task 30, a third 10 ms task 32 and a fourth 10 ms task 34 executed. A fifth 10 ms task 36, shown only partially, is the first 10 ms task 36 of the subsequent cycle. In the third row of the first microcontroller 2, a first 20 ms task 38 and a second 20 ms task 40 of the current cycle are shown, in the fourth row a 40 ms task 42 of the current cycle is shown. In the fifth row, the current cycle of the first microcontroller 2 includes two VAFSCIF receive buffers 44 and two VASFCIF transmit buffers 46. The second microcontroller 4 comprises a 20 ms VASF task 48, a 20 ms scan during the current cycle. ms VASF task 49 and a 40 ms VASF task 50. A 20 ms VASF task 52 of the subsequent cycle is only partially shown.

It is envisaged that, starting from individual tasks, task copies are transmitted to other software modules. Such transmissions are represented by arrows between the respective software modules.

A function transfer between the two microcontrollers 2, 4 takes place via the interface 6. In this case, data is transmitted from the first 5 ms task 10 to the 20 ms VASF task 48. From the 20 ms VASF task 48 via the interface 6, a function rearrangement to the first VAFSCIF receive buffer 44. In the first VASFCIF transmission buffer 46 task copies of the first 5-ms task 10, the first 10-ms Tasks 28 and the first 20 ms task 38 received. Via the interface 6 takes place to the 40 ms VASF task 50, a transfer of data. From this 40 ms VASF task 50 via the interface 6 to the second VAFSCIF receive buffer 44, a transfer of the data.

FIG. 2 shows a schematic representation of a control unit 60 which has a first microcontroller 62 embodied as an algorithm server (AS) and a second microcontroller 64 designed as a function server with additional values (Value Added Function Server, VASF). Both microcontrollers 62, 64 each have the following in Figure 2 tabular structured modules: a read memory (ROM) 66 (first column) and a random access memory (RAM) 68, each in an internal sector 70 (second column), an AS-VASF Sector 72 (third column) for relocating data from the first microcontroller 62 to the second microcontroller 64 and a VASF-AS sector 74 (fourth column) for the rearrangement of data from the second microcontroller 64 to the first microcontroller 62.

Software for 5 ms tasks "BSC TASK_5" 76, software for 10 ms tasks "HIM TASK_10" 78 and software for 20 ms tasks "SIF TASK 20" 80 are stored in the read memory 66 of the first microcontroller 62. It is contemplated that upon operation of the first microcontroller 62 from the software "BSC TASK_5" 76 for the internal sector 70 of the random access memory 70, 5 ms tasks "vBscTδ" 82, "vBscT5x20" 84 and "vBscT5x40" 86 are provided. In addition, the internal sector 70 will be out of software

"HIM TASK_10" 78 provided 10-ms tasks "vHimTlOxδ" 88, "vHimTIO" 90 and ^M vHiml0x40 "92. From the software for 20-ms tasks" SIF TASK_20 "80 become 20-ms tasks" vSifT20x5 "94 , "vSifT20x20" 96 and "vSifT20x40" 98.

The read memory 66 of the second microcontroller 64 comprises software for 40 ms tasks "FZR Task_40", with which the internal sector 70 of the read memory 68 40 ms- tasks "vFzrT40x5" 102 and "vFzrT40x20" 104 are provided.

Within the microcontroller 62, 64 task copies are provided, which are represented by dotted-solid arrows. In the first microcontroller 62, a task copy is made from the 5 ms task "vBscT5x40" 86 to a 5 ms task "vBsc5T40c40" 106 in the AS-VASF sector 72, a task copy from the 10 ms task "vHimT10x40" 92 to a 10 ms task "vHimT10x40c40" 108 in the AS-VASF sector 72. Also, a task copy from the 40 ms task "vSifT20x40" 98 to a 40 ms task "vSifT20x40c40" 110 in the AS- VASF sector 72 is provided.

For the 5 ms task "vBsc5T40c40" 106, the 10 ms task "vHimT10x40c40" 108 and the 40 ms task "vSifT20x40c40" 110, the AS-VASF sector 72 of the first microcontroller transmits data shown by an arrow 112 in the AS-VASF sector 72 of the second microcontroller 64 performed. It is provided that only data of the tasks are read from the AS-VASF sector 72 of the second microcontroller 64 (dashed double-headed arrow). Furthermore, task copies are made for the 5 ms task "vBsc5T40c40" 106, the 10 ms task "vHimT10x40c40" 108 and the 40 ms task "vSifT20x40c40" 110 from the AS-VASF sector 72 into the internal sector 70 of the second microcontroller 64.

For the two 40 ms tasks "vFzrT40x5" 102 and "vFzrT40x20" 104 from the internal sector 70 of the second microcontroller 64, respectively, task copies in the VAFS-AS sector 74 to the 40 ms tasks ^M vFzrT40x5c5 "114 or ^M vFzrT40x20c20 "116 is provided. For these two 40 ms tasks "vFzrT40x5c5" 114 or "vFzrT40x20c20" 116, a data transmission 118 (arrow) from the VAFS-AS sector 74 of the second microcontroller 64 to the VAFS-AS sector of the first microcontroller 62 takes place. The VASF AS sector of the first microcontroller 62 is provided for reading the tasks stored therein (dashed double-headed arrow). For the 40 ms tasks "vFzrT40x5c5" 114 and "vFzrT40x20c20" 116, task copies are provided in the internal sector of the first microcontroller 62.

Claims

claims

1. Control unit having at least a first microcontroller (2, 62) and at least one second microcontroller (4, 64), wherein the at least one second microcontroller (4, 64) to the at least one first microcontroller (2, 62) for simultaneous processing of tasks is connected, wherein a software rearrangement takes place between the at least one first microcontroller (2, 62) and the at least one second microcontroller (4, 64) for time-shifted tasks.

2. Control device according to claim 1, wherein the at least one first microcontroller (2, 62) as an algorithm server and the at least one second microcontroller (4, 64) is designed as a server for performing additional functions.

3. Control device according to claim 1 or 2, wherein the at least one first microcontroller (2, 62) and the at least one second microcontroller (4, 64) via at least one serial interface (6) are connected.

4. Control device according to one of the preceding claims, wherein the at least one first microcontroller (2, 62) and the at least one second microcontroller (4, 64) are adapted to during a cycle tasks for different

Time periods to edit.

5. Control device according to one of the preceding claims, wherein it is provided to provide task copies of the data for individual tasks.

6. Control device according to one of the preceding claims, which is designed to carry out a stability program of a vehicle.

7. A method for operating a control device (60) having at least a first microcontroller (2, 62) and at least one second microcontroller (4, 64), wherein the at least one second microcontroller (4, 64) to the at least one first microcontroller (2, 62) is connected for the simultaneous processing of tasks, wherein a software migration is performed between the microcontrollers (2, 4, 64, 64) for time-shifted tasks.

8. The method of claim 7, wherein during one cycle of the at least one first microcontroller (2, 62) and the at least one second microcontroller (4, 64), tasks are processed for different periods of time.

9. The method of claim 7 or 8, wherein for individual tasks task copies of the data are provided.

10. Computer program with program code means to perform all the steps of a method according to one of claims 7 to 9, when the computer program on a computer or a corresponding processing unit, in particular a control device (60) according to one of claims 1 to 6, is executed.

11. Computer program product with program code means which are stored on a computer-readable data carrier in order to carry out all the steps of a method according to one of claims 7 to 9, when the computer program is stored on a computer or a corresponding arithmetic unit, in particular a control device (60) according to one of claims 1 to 6, is executed.