WO2007049198A1

WO2007049198A1 - A system for driving a constant current load

Info

Publication number: WO2007049198A1
Application number: PCT/IB2006/053854
Authority: WO
Inventors: Frans Pansier
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-10-27
Filing date: 2006-10-19
Publication date: 2007-05-03

Abstract

A system for driving a constant current load comprises the constant current load (LEi) and a down-converter (1). The down-converter (1) comprises a series arrangement of a switch (Sl; S2) and an inductor (Ll; L2). This series arrangement is arranged in series with the constant current load (LEi). The series arrangement of the switch (Sl; S2), the inductor (Ll; L2), and the constant current load (LEi) is arranged for receiving a DC input voltage (VI). A controller (10) receives a peak current set level (IP) for: (i) opening the switch (Sl; S2) when an inductor current (ILl; IL2) through the inductor (Ll; L2) reaches a peak current value indicated by the peak current set level (IP), and (ii) closing the switch (Sl; S2) at a substantially zero level of the inductor current (ILl; IL2). The system further comprises a processor (12) for supplying the peak current set level (IP) having a predetermined non-zero value independent on an output voltage (VO) across said load (LEi).

Description

A system for driving a constant current load

Field of the invention

The invention relates to a system for driving a constant current load, to a display apparatus comprising a display device, and to a display apparatus comprising a display device having N>1 groups of differently colored pixels and a backlight unit which comprises N such systems.

Background of the invention

The Power Integrations LinkSwitch-TN Design Guide Application Note AN- 37 of December 2004 discloses the LinkSwitch-TN which combines a high voltage power MOSFET switch with an ON/OFF controller in one device. This application note discloses a constant current circuit configuration which is ideal for driving constant current loads such as LEDs. To generate a constant current output in a buck-boost converter, the average output current is converted into a feedback voltage by a resistor through which the load current flows. To regulate the output, an ON/OFF control scheme is used. At the beginning of each cycle, the feedback pin is sampled. If the current into the feedback pin is smaller than a predetermined value, the next cycle occurs, if not, the next cycle is skipped. Thus, the decision to switch is made on a cycle-by-cycle basis. Consequently, at a high load only a few cycles are skipped, and at a low load many cycles are skipped. The resultant power supply has an extremely good transient response. During each cycle, the switch is switched off when a predetermined peak value of the current is reached. The cycles have a fixed duration.

However, a disadvantage of this prior art is that the current can not be directly set. A separate sensing has to be incorporated to obtain a desired current. This sensing deteriorates the transient response, and provides a system which is not able to decide cycle by cycle whether a next switching cycle will be started or not.

Summary of the invention

It is an object of the invention to provide an improved system for supplying a controllable average output current to a constant current load. A first aspect of the invention provides a system as claimed in claim 1. A second aspect of the invention provides a display apparatus as claimed in claim 11. A third aspect of the invention provides a display apparatus as claimed in claim 12. Advantageous embodiments are defined in the dependent claims. A system in accordance with the first aspect of the invention comprises a constant current load and a down-converter. The down-converter comprises a series arrangement of a switch and an inductor, which series arrangement is arranged in series with the load. A DC input voltage is supplied to the series arrangement of the switch, the inductor, and the load. The down-converter further comprises a controller which receives a peak current set level. The controller opens the switch when an inductor current through the inductor reaches a peak value corresponding to the peak current set level.

The controller closes the switch at a substantially zero level of the inductor current. Consequently, the down-converter operates in a substantially critical conduction mode wherein the peak current through the inductor is substantially twice the average current supplied to the load. Thus, the average current through the load has a substantially one to one relation with the peak current set level, and thus can be directly set by the peak current set level. Because of the use of the substantially critical conduction mode in a down-converter instead of the prior art discontinuous conduction mode in a buck-boost converter, the prior art voltage feedback is not required. This simplifies the power converter and improves the control behavior of the power converter.

The substantial critical conduction mode has the further advantage that the inductor current in the down-converter is substantially zero at the end of the off-period of the switch. If the switch is not closed, no or almost no current is flowing in the inductor and the current supplied to the load immediately stops flowing. Consequently, an extremely good transient response is obtained.

The peak current set level has a predetermined non-zero value which is independent of the output voltage across the load. This non-zero value directly determines the average current through the load. It has to be noted that in the well known voltage stabilized current-mode controlled down-converters, the peak current set level is not a predetermined level but is varied in response to the difference between the output voltage across the load and a reference level.

In an embodiment as claimed in claim 2, the processor supplies the peak current set level with the predetermined non-zero value during an active period of said down- converter. The peak current set level has a zero value during an inactive period of said down- converter. The average current through the load is determined by both the peak current set level and the ratio of the active period in time and the complete period in time which is the sum of the active period and the inactive period. The average current during the active period has a one to one relation with the level of the peak current set level during the active period. The average current during one complete period, which comprises one active period and one inactive period, is the average current during the active period multiplied by the ratio of the active period and the complete period. The active period and the inactive period both have a duration of at least one switching cycle which comprises a consecutive on-period and off- period of the switch. In an embodiment as claimed in claim 3, the processor changes the peak current set level from the predetermined non-zero value to the zero value when the switch is open. This to prevent a switch off of the switch before the current through the inductor is zero.

In an embodiment as claimed in claim 4, the constant current load comprises a light emitting element or a series arrangement of light emitting elements. The brightness of the light emitting elements is defined by the average current flowing through the light emitting elements. Also the color is somewhat influenced by the actual value of the current. It is therefore of utmost importance that this average current has a well defined and stable predetermined value. The brightness of the light emitting elements may be set by the peak current set level, and/or the above discussed ratio. Especially, during the switching cycles, to minimize the influence of the actual current value on the color point, preferably the current has either a predetermined fixed value during the active period and the current is set to zero during the inactive period. This zero current may be achieved by setting the predetermined peak current level to zero when the switch is off. In an embodiment as claimed in claim 5, the down-converter further comprises a circuit for sensing the inductor current. The controller comprises a set-reset flip-flop, a comparator which compares the sensed inductor current and the peak current level to reset the set-reset flip-flop when the sensed inductor current reaches the peak current level. The controller further comprises a comparator which compares the sensed inductor current with a zero level for setting the set-reset flip-flop when the sensed inductor current reaches the zero level. The set-reset flip-flop has an output coupled to a control input of switch to have the switch closed if the set-reset flip-flop is set and to have the switch opened if the set-reset flip- flop is reset. In this embodiment, the switch off of the switch occurs at zero current through the inductor. Thus, the down-converter is operating in the critical conduction mode and the average current to the load is the half of the peak current through the inductor.

In an embodiment as claimed in claim 6, the down-converter further comprises a capacitor arranged in parallel with the switch, a capacitor arranged in parallel with said load, a diode arranged in parallel with a series arrangement of the inductor and the load, and a circuit for sensing the inductor current. The diode is poled to conduct current when the switch is open. The controller comprises a set-reset flip-flop, a comparator which compares the sensed inductor current and the peak current level to reset the set-reset flip-flop when the sensed inductor current reaches the peak current level. The controller further comprises a detector which detects a zero level or a minimum level of a voltage across the switch to set the set-reset flip-flop at the detected zero level or minimum level. The set-reset flip-flop has an output coupled to a control input of switch to have the switch closed if the set-reset flip- flop is set and to have the switch opened if the set-reset flip-flop is reset.

This down-converter has an oscillation phase at the end of the on-period of the switch. The actual situation depends on the ratio between the DC input voltage and the output voltage. If, as claimed in claim 7, this ratio is 2, the minimum value of the voltage across the switch is reached at the instant the current through the inductor is zero. Again the optimal critical conduction mode is obtained. In this embodiment, the minimum value of the voltage across the switch is zero. The switch is closed at the instant the voltage across the switch is zero or has reached the minimum value. If the ratio is larger than two, the switch has to be closed at the instant the minimum of the voltage across the switch is reached. At this instant the current through the inductor is again zero. Because now the switching on of the switch occurs not at zero voltage, the losses are higher than if the ratio is 2. If the ratio is smaller than two, again the switch has to be closed at the instant the minimum voltage across the switch is reached. Now, the current through the inductor is still negative. However, as long as the inductor current is substantially zero, the fast response and the one to one relation between the average current and the peak current level are upheld. Preferably, the ratio is larger than 1.5 and smaller than 4.

In an embodiment as claimed in claim 8, the processor adapts the peak current set level in response to a user input signal defining a brightness of the light emitting element or the series arrangement of light emitting elements. The system provides an average current through the light emitting element or through the series arrangement of light emitting elements which has a one to one relation with the input signal supplied by the user. In an embodiment as claimed in claim 9, the processor adapts the peak current set level (IP) and/or said ratio of the active period and the complete period in response to a user input signal defining a brightness of the light emitting element or the series arrangement of light emitting elements. The system provides an average current through the light emitting element or through the series arrangement of light emitting elements which has a one to one relation with the input signal supplied by the user.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Brief description of the drawings

In the drawings:

Fig. 1 shows diagrammatically a circuit diagram of a system in accordance with an embodiment of the invention,

Fig. 2 shows signals for elucidating the operation of the circuit of Fig. 1, Fig. 3 shows diagrammatically a circuit diagram of a system in accordance with another embodiment of the invention,

Figs. 4 A to 4C show signals for elucidating an operation mode of the circuit of Fig. 3,

Fig. 5 shows the voltage across the switch for another operation mode of the circuit of Fig. 3,

Fig. 6 shows the voltage across the switch for yet another operation mode of the circuit of Fig. 3,

Fig. 7 shows the active and inactive periods of the down-converter, and

Fig. 8 schematically shows a display apparatus which comprises N systems in accordance with the invention.

It should be noted that items which have the same reference numbers in different Figures, have the same structural features and the same functions, or are the same signals. Where the function and/or structure of such an item has been explained, there is no necessity for repeated explanation thereof in the detailed description.

Detailed description

Fig. 1 shows diagrammatically a circuit diagram of a system in accordance with an embodiment of the invention. The system comprises a down-converter 1, a processor 12, and a light emitting diode or a string of light emitting diodes. The processor 12 supplies a peak current set level IP. The single light emitting diode or the string of diodes is or are referred to as LEi and is further also referred to as the load LEi. The individual diodes in the string are indicated by LEl to LEN.

The down-converter 1 comprises a series arrangement of a switch S 1 and an inductor Ll . This series arrangement is arranged in series with the load LEi to receive a DC- input voltage VI. A diode Dl is arranged in parallel with the series arrangement of the inductor Ll and the load LEi. The diode Dl is poled to conduct when the switch is open and to block when the switch is closed.

The down-converter 1 further comprises a current sense circuit CS which senses the inductor current ILl through the inductor to obtain a sensed inductor current SIl which is also referred to as the sensed current SIl. Although the current sense circuit CS is shown to directly sense the inductor current ILl, this current may be sensed indirectly, for example by sensing both the current through the switch Sl and the current through the diode Dl. The current sense circuit CS is, for example a resistor across which the voltage is sensed, or a current transformer, or may use any other current sensing technique.

The down-converter further comprises a controller 10 which supplies a switch signal SCl to the switch Sl to control the on and off periods of the switch Sl. The controller 10 comprises a comparator 100 which compares the sensed current SIl with peak current set level IP to reset the set-reset flip-flop 102 when the sensed current SIl reaches the peak current set level IP. The controller 10 further comprises a comparator 101 which compares the sensed current SIl with a zero level 0 to set the set-reset flip-flop 102 when the sensed current SIl reaches the level zero. If the set-reset flip-flop 102 is set, the switch Sl is closed, if the set-reset flip-flop 102 is reset, the switch Sl is open.

The operation of the system shown in Fig. 1 will be elucidated with respect to Fig. 2.

Fig. 2 shows signals for elucidating the operation of the circuit of Fig. 1. Fig. 2 shows the inductor current ILl for two peak current set levels IP and IP'. It is assumed that the system is in a stable situation wherein the peak current set level IP or IP' is constant. At the instant tl, the inductor current ILl reaches the zero level, the set-reset flip-flop 102 is set via the comparator 101 and the switch Sl is closed. Now, the DC-input voltage VI is supplied across the series arrangement of the inductor Ll and the load LEi. Because the load LEi is a single diode or a string of diodes, the voltage VO across the load LEi is considered to be constant. Consequently, at the instant tl, the voltage across the inductor Ll is VI-VO, wherein VI is larger than VO, otherwise the power converter would not be a down-converter. Thus, the inductor current ILl increases linearly. At the instant t2, the inductor current ILl reaches the peak current set level IP and the set-reset flip-flop 102 is reset via the comparator 100. Now, the switch Sl is opened, the inductor current ILl starts flowing through the diode Dl, and the voltage across the inductor Ll is approximately -VO. Consequently, the inductor current ILl decreases linearly until at the instant t3 the zero crossing is detected and the set- reset flip-flop 102 is set again, and so on. The period in time lasting from the instant tl to t2 is the on-time TON of the switch Sl, the period in time lasting from the instant t2 to t3 is the off-time TOFF of the switch Sl.

If the peak current set level is the level IP' which is higher than the level IP, the same sequence will be performed, the only difference is that the on-period TON now ends later, at the instant t2', and that the off-period TOFF is shifted to occur from the instant t2'to the instant t3'. A switching cycle of the down-converter comprises a consecutive on-period TON and off-period TOFF.

It is clear from Fig. 2 that the average value of the inductor current ILl and thus of the current through the load LEi is exactly half the peak value of this current ILl .

Consequently, if the down-converter is operated in the critical conduction mode, a fixed one to one relation exists between the peak current set level IP generated by the processor 12 and the average inductor current ILl. As the average current flowing through the LEDs LEi determines the brightness produced, the brightness of the LEDs LEi has a fixed one to one relation with the peak current set level IP. It has to be noted that the control mechanism is very simple and that no voltage feedback is required as is usual in current mode operated down-converters.

Further, because the inductor current ILl is zero at the end of a particular switching cycle, it is possible to decide per switching cycle whether the switch S 1 will actually be closed to start a next cycle or not. For example, the processor 12 may switch the peak current set level IP to a zero level during the off period TOFF. At the start of the next switching cycle, first the switch is closed because set-reset flip-flop 102 is set via the comparator 101, but at substantially the same instant the set-reset flip-flop 102 is reset via the comparator 102. Thus, no further switching cycles are started until the processor 12 changes the peak current set level IP to a non-zero value. The period in time during which the peak current set level IP has a non-zero value and switching cycles occur, is referred to as the active period TA (see Fig. 7). The period in time during which the peak current set level IP has the zero level and no switching cycles occur, is referred to as the inactive period TIA (see Fig. 7). It has to be noted that the actual average inductor current ILl, and thus the average current through the load LEi depends on both the actual non-zero value of the peak current set level IP, and on the ratio of the active period TA and the total period TT (see Fig. 7) which is the sum of one active period TA and one inactive period TIA. The larger the non- zero peak current set level IP is during the active period TA, the larger the average value of the inductor current ILl is during the active period TA. The actual average value is the average value during the active period multiplied by the above mentioned ratio. Consequently, the actual average inductor current ILl has a one to one relation with the actual level of the peak current set level IP and the ratio. Thus, the processor 12, which controls both these parameters, is able to accurately set the brightness of the LEDs LEi. The processor may have an input to receive a user command UC indicating the desired brightness.

In a system in which different groups of LEDs are used which supply differently colored light, the accurate control of the brightness of the different groups is particularly relevant if the color point of the combined light should be kept constant. The color point of the combined light can be controlled by setting the non-zero peak current set levels IP, IP', IP" (see Fig. 8) and/or the ratio of the active period TA and the total period TT of the different groups of LEDs.

Further, it has to be noted that the average inductor current ILl is independent of the actual levels of the DC-input voltage VI and the output voltage VO because the average value of the sawtooth shape of the inductor current ILl is always the same due to the fixed current levels zero and IP at which the state of the switch alters. A varying level of the DC-input voltage VI and the output voltage VO only causes a change of the slope of the sawtooth and of the duration of the on-period TON and/or the off-period TOFF.

Fig. 3 shows diagrammatically a circuit diagram of a system in accordance with another embodiment of the invention. The system shown in Fig. 3 comprises a down- converter 1, the load LEi and a controller 10.

The down-converter 1 comprises an inductor L2, a switch S2, a diode D2, the capacitors C2 and C3, and a current sense circuit CS. The load LEi comprises a string of LEDs LEl to LEN, but may comprise a single LED. The inductor L2, the load LEi, and the switch S2 are arranged in series to receive a DC-input voltage VI. The inductor L2 is arranged between the positive pole of the DC-input voltage VI and the load LEi. The switch S2 is arranged between the load LEi and the negative pole of the DC-input voltage VI. The diode D2 is arranged in parallel with the series arrangement of the inductor L2 and the load LEi. The diode D2 is poled to block when the switch S2 is closed and to conduct when the switch S2 is open. The capacitor C2 is arranged in parallel with the switch S2, and the capacitor C3 is arranged in parallel with the load LEi. The sense circuit CS senses the inductor current IL2 flowing both through the inductor L2 and the parallel arrangement of the load LEi and the capacitor C3 to obtain a sensed inductor current SI2. It is assumed that the voltage VO across the load LEi is constant. Consequently, also the voltage across the capacitor C3 is constant and the inductor current IL2 is also flowing through the load LEi.

The controller 10 comprises a comparator 104, a voltage sense circuit 106, and a set-reset flip-flop 105. The comparator 104 compares the sensed inductor current SI2 with the peak current set level IP to reset the set-reset flip-flop 105 when the sensed inductor current SI2 reaches the peak current set level IP. Again, the peak current set level IP is supplied by a processor 12. The voltage sense circuit 106 senses the voltage VS2 across the switch S2. The set-reset flip-flop 105 is set if the voltage sense circuit 106 detects that the voltage VS2 has reached its minimum value or has become zero. If the set-reset flip-flop 105 is set, the switch S2 is closed, if the set-reset flip-flop 105 is reset, the switch S2 is open. The operation of the system shown in Fig. 3 will be elucidated with respect to

Figs. 4A to 4C and Figs. 5 and 6.

Figs. 4 A to 4C show signals for elucidating an operation mode of the circuit of Fig. 3. Fig. 4A shows the voltage VS2 across the switch S2. Fig. 4B shows the voltage VL2 across the inductor L2, and Fig. 4C shows the inductor current IL2. The switch S2 is closed before the instant tlO. Consequently, the voltage VS2 across the switch is substantially zero and the voltage VL2 across the inductor L2 is VI-VO causing a linearly increasing inductor current IL2.

At the instant tlO, the inductor current IL2 reaches the peak current set level IP, the set-reset flip-flop 105 is reset via the comparator 104 and the switch S2 is opened. The relatively large inductor current IL2 quickly charges the capacitor C2 until the diode D2 starts conducting and the voltage VL2 becomes the sum of the DC-input voltage VI and the diode voltage VD2 across the conductive diode D2. The voltage VL2 across the inductor L2 drops to -VO and the inductor current IL2 starts decreasing linearly.

At the instant tl 1, the inductor current IL2 becomes zero, and the diode D2 stops conducting. Because also the switch S2 is open, the inductor L2 and the capacitors C2 and C3 form a resonance circuit. In Figs. 4 it is assumed that the level of DC-input voltage VI is exactly two times higher than the level of the voltage VO across the load LEi. The voltage VA starts resonating around the voltage VI. As shown in Fig. 4B, the voltage across the inductor L2 resonantly changes from -VO to VI-VO during the resonance period lasting from the instant tl 1 to the instant tl2. As shown in Fig. 4A, the voltage VS2 across the switch S2 resonantly changes from VI+VD2 to zero during the resonance period. The inductor current IL2 will be zero at the end of the resonance period as is shown in Fig. 4C. Fig. 5 shows the situation if the DC-input voltage VI has a level which is higher than two times the level of the voltage VO across the load LEi. Fig. 6 shows the situation if the DC- input voltage VI has a level which is lower than two times the level of the voltage VO.

At the instant tl2, the voltage VS2 reaches its minimal level which is zero, and the set-reset flip-flop 105 is set via the voltage sense circuit 106. The switch S2 is closed and the same situation exists as before the instant tlO: the inductor current IL2 starts increasing until the peak set value IP is reached at the instant tl3. It has to be noted that the switch S2 is switched on at the instant tl2 when the inductor current IL2 is zero and the voltage VS2 across the switch S2 is zero. Thus again, it is possible to decide at a cycle by cycle rate whether a next switching cycle should be started or not. A next switching cycle is started if the peak current set level IP is non-zero, and no next cycle is started if the peak current set level IP is changed to zero during the off-period of the switch S2.

Further, again a one to one relation exists between the peak current set level IP and the average value of inductor current IL2, which is elucidated by showing the inductor current IL2 for peak current set level IP' which is higher than the peak current set level IP. Now, the peak current set level IP' is reached at the instant tlO' and the inductor current IL2 becomes zero at the instant ti l '. The switch S2 is closed at the instant tl2' until the instant tl3' at which the peak current set level IP' is reached again.

Fig. 5 shows the voltage across the switch for another operation mode of the circuit of Fig. 3. Now, the DC-input voltage VI has a level which is higher than two times the level of the voltage VO across the load LEi. Again, the voltage VS2 starts resonating at the instant tl 1, but because VI >2VO its minimum level at the instant tl2, which is VI-2V0 is larger than zero. Consequently, the switch S2, which is switched on at the minimum level of the voltage VS2, is still switched on at the instant tl2 that the inductor current IL2 is zero, but not a zero voltage VS2 across it. Thus, the efficiency of the system is somewhat lower than the embodiment discussed with respect to Figs. 4 due to the switch on losses. But all other advantages related to switching on the switch S2 at zero inductor current IL2 are kept. It has been experimentally found that the switching losses are acceptable if the DC-input voltage VI has a level which is lower than 4 times the level of the voltage VO across the load LEi. Fig. 6 shows the voltage across the switch for yet another operation mode of the circuit of Fig. 3. Now, the DC-input voltage VI has a level which is lower than two times the level of the voltage VO across the load LEi. Again, the voltage VS2 starts resonating at the instant tl 1, but because VI <2VO its zero level is reached at the instant tl4 which occurs before the instant tl2. Consequently, the switch S2, which is switched on at the zero level of the voltage VS2, is no longer switched on at the instant tl2 that the inductor current IL2 is zero. Thus, although the switching on of the switch S2 occurs at zero voltage, the non-zero inductor current is a small drawback only as long as the inductor current is substantially zero. It has been experimentally found that the DC-input voltage VI should have a level which is higher than 1.5 times the level of the voltage VO across the load LEi.

Fig. 7 shows the active and inactive periods of the down-converter. As discussed hereinbefore, the down-converter in accordance with the invention may have active periods TA and inactive periods TIA. During the active periods TA, the peak current set level IP has a non-zero value and switching cycles occur, during the inactive periods TIA, the peak current set level IP has a zero value and no switching cycles occur. In the example shown in Fig. 7 the active periods TA lasts from the instant Tl to the instant T2, and from the instant T3 to the instant T4. The inactive period TIA lasts from the instant T2 to the instant T3. The total or complete period TT comprises one active period TA and one inactive period TIA.

Fig. 8 schematically shows a display apparatus which comprises N systems in accordance with the invention. Fig. 8 shows schematically a display panel 3 which is covered by a back light unit 4. The display panel has pixels Pij of which only one is shown. The display panel preferably is a matrix display such as, for example, a LCD display. The back light unit 4 comprises the LEDs which are interconnected to form groups Gl, G2, G3. The LEDs of the same group emit light having substantially the same color, and the color of the light of the LEDs of different groups is different. Preferably, the colors are primary colors such that the total light is white. For example, all the LEDs of the group Gl emit red light, all the LEDs of the group G2 emit green light, and all the LEDs of the group G3 emit blue light. In Fig. 8 a large amount of LEDs is shown, one for each pixel Pij, this has the advantage that no color filters are required in the LCD display. However in a more practical implementation, the number of LEDs per group is lower than the number of pixels. The

LEDs are only required to produce a same back light (preferably white) for all the pixels, the pixels have a color filter for filtering the required primary color.

The current through each one of the groups Gl, G2, G3 of the LEDs is generated with a down-converter 1, 1 ', 1", respectively, in accordance with the invention. The processor 12 generates the peak current set levels IP, IP', IP" which are supplied to the down-converters 1, 1 ', 1", respectively. Due to the one to one relation between the peak current set levels IP, IP', IP" and the average currents ILl, ILl ', ILl" the white color and the total brightness of the combined light can be controlled by setting the peak current set levels IP, IP', IP". The setting of the peak current levels IP, IP', IP" may include the setting of the value of the levels and/or the on/off periods to control the active/inactive periods of the down-converters 1, 1 ', 1".

Instead of using one down-converter for all LEDs of one of the groups, it is possible to divide the LEDs of a same group in sub-groups and use a down-converter for each one of the sub-groups. This allows optimizing the down-converters with respect to the maximum current they have to supply.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. Although in the embodiments shown, the load LEi comprises LEDs, the load

LEi may comprise other elements which require a well defined current.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A system for driving a constant current load (LEi) and comprising the constant current load (LEi) and a down-converter (1), the down-converter (1) comprises a series arrangement of a switch (Sl; S2) and an inductor (Ll; L2), said series arrangement being arranged in series with said load (LEi), the series arrangement of the switch (Sl; S2), the inductor (Ll; L2), and said load (LEi) being arranged for receiving a DC input voltage (VI), and a controller (10) for receiving a peak current set level (IP) having a predetermined non-zero value independent of an output voltage (VO) across said load (LEi), the controller (10) being constructed for: (i) opening the switch (Sl; S2) when an inductor current (ILl; IL2) through the inductor (Ll; L2) reaches a peak current value indicated by the peak current set level (IP), and (ii) closing the switch (Sl; S2) at a substantially zero level of the inductor current (ILl; IL2).

2. A system as claimed in claim 1, further comprising a processor (12) being constructed for supplying the peak current set level (IP) having the predetermined non-zero value during an active period of said down-converter (1), and having a zero value during an inactive period of said down-converter (1), wherein the active period and the inactive period both have a duration of at least one switching cycle comprising a consecutive on-period and off-period of the switch (Sl; S2).

3. A system as claimed in claim 2, wherein the processor (12) is constructed for changing the peak current set level (IP) from the predetermined non-zero value to the zero value when the switch (S 1 ; S2) is open.

4. A system as claimed in claim 1, 2 or 3, wherein the constant current load (LEi) comprises a light emitting element or a series arrangement of light emitting elements.

5. A system as claimed in claim 1, 2 or 3, wherein said down-converter further comprises means for sensing the inductor current (ILl) to obtain a sensed inductor current (SIl), the controller (10) comprises a set-reset flip-flop (102), a comparator (100) for comparing the sensed inductor current (SIl) and the peak current level (IP) for resetting the set-reset flip-flop (102) when the sensed inductor current (SIl) reaches the peak current level (IP), and a comparator (101) for comparing the sensed inductor current (SIl) with a zero level for setting the set-reset flip-flop (102) when the sensed inductor current (SIl) reaches the zero level, wherein the set-reset flip-flop (102) has an output coupled to a control input of switch (Sl) to have the switch (Sl) closed if the set-reset flip-flop (102) is set and to have the switch (Sl) opened if the set-reset flip-flop (102) is reset.

6. A system as claimed in claim 1, 2 or 3, wherein said down-converter further comprises a capacitor (C2) arranged in parallel with the switch (S2), a diode (D2) arranged in parallel with a series arrangement of the inductor (L2) and said load (LEi), the diode (D2) being poled to conduct current when the switch (S2) is open, a capacitor (C3) arranged in parallel with said load (LEi), and means for sensing the inductor current (IL2) to obtain a sensed inductor current (SI2), the controller (10) comprises a set-reset flip-flop (105), a comparator (104) for comparing the sensed inductor current (SI2) and the peak current level (IP) for resetting the set-reset flip-flop (105) when the sensed inductor current (SI2) reaches the peak current level (IP), a detector (106) for detecting a zero level or a minimum level of a voltage across the switch (S2) for setting the set-reset flip-flop (105) at the detected zero level or minimum level, wherein the set-reset flip-flop (105) has an output coupled to a control input of switch (S2) to have the switch (S2) closed if the set-reset flip-flop (105) is set and to have the switch (S2) opened if the set-reset flip-flop (105) is reset.

7. A system as claimed in claim 6, wherein a ratio of the DC-input voltage (VI) and the output voltage (VO) has a value between 1.5 and 4.

8. A system as claimed in claim 4 when dependent on claim 1, wherein the processor (12) is constructed for adapting the peak current set level (IP) in response to a user input signal defining a brightness of the light emitting element or the series arrangement of light emitting elements.

9. A system as claimed in claim 4 when dependent on claim 2, wherein the processor (12) is constructed for adapting the peak current set level (IP) and/or said ratio in response to a user input signal defining a brightness of the light emitting element or the series arrangement of light emitting elements.

10. A system as claimed in claim 4, wherein the light emitting element is a LED, or the light emitting elements are LEDs.

11. A display apparatus comprising - a display device, and a back light unit comprising the system as claimed in claim 4, the light emitting element being arranged for illuminating the display device.

12. A display apparatus comprising - a display device having N > 1 groups of differently colored pixels, and a back light unit comprising N systems as claimed in claim 1 , the light emitting element of each one of the N systems being associated with a corresponding one of the groups.