WO2007026226A3 - Microcontroller architecture including a predefined logic area and customizable logic areas - Google Patents

Microcontroller architecture including a predefined logic area and customizable logic areas Download PDF

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Publication number
WO2007026226A3
WO2007026226A3 PCT/IB2006/002381 IB2006002381W WO2007026226A3 WO 2007026226 A3 WO2007026226 A3 WO 2007026226A3 IB 2006002381 W IB2006002381 W IB 2006002381W WO 2007026226 A3 WO2007026226 A3 WO 2007026226A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic
architecture including
customizable
microcontroller architecture
module
Prior art date
Application number
PCT/IB2006/002381
Other languages
French (fr)
Other versions
WO2007026226A2 (en
Inventor
Alain Vergnes
Original Assignee
Atmel Corp
Alain Vergnes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/412,317 external-priority patent/US20070067542A1/en
Application filed by Atmel Corp, Alain Vergnes filed Critical Atmel Corp
Publication of WO2007026226A2 publication Critical patent/WO2007026226A2/en
Publication of WO2007026226A3 publication Critical patent/WO2007026226A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Bus Control (AREA)

Abstract

A microcontroller architecture in accordance with this invention provides modules or circuitry that may be programmed with a protocol for communication or other application. The architecture in accordance with this invention provides at least one module on a high bandwidth or system bus and a second module on a second low bandwidth or peripheral bus that allows a maker to program a module needing specified processing bandwidths using the desired bus. This allows microcontrollers to be produced that are adaptable without a great increase of cost or loss functionality.
PCT/IB2006/002381 2005-08-29 2006-08-23 Microcontroller architecture including a predefined logic area and customizable logic areas WO2007026226A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0508819 2005-08-29
FR0508819 2005-08-29
US11/412,317 US20070067542A1 (en) 2005-08-29 2006-04-26 Microcontroller architecture including a predefined logic area and customizable logic areas
US11/412,317 2006-04-26

Publications (2)

Publication Number Publication Date
WO2007026226A2 WO2007026226A2 (en) 2007-03-08
WO2007026226A3 true WO2007026226A3 (en) 2008-07-03

Family

ID=37809241

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/002381 WO2007026226A2 (en) 2005-08-29 2006-08-23 Microcontroller architecture including a predefined logic area and customizable logic areas

Country Status (1)

Country Link
WO (1) WO2007026226A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808851A (en) * 1986-02-18 1989-02-28 U.S. Philips Corporation ECL-compatible semiconductor device having a prediffused gate array
US6583344B2 (en) * 2001-06-19 2003-06-24 Stine Seed Farm Inc. Soybean cultivar 82147657
US20040030861A1 (en) * 2002-06-27 2004-02-12 Bart Plackle Customizable computer system
US6754881B2 (en) * 2001-12-10 2004-06-22 International Business Machines Corporation Field programmable network processor and method for customizing a network processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808851A (en) * 1986-02-18 1989-02-28 U.S. Philips Corporation ECL-compatible semiconductor device having a prediffused gate array
US6583344B2 (en) * 2001-06-19 2003-06-24 Stine Seed Farm Inc. Soybean cultivar 82147657
US6754881B2 (en) * 2001-12-10 2004-06-22 International Business Machines Corporation Field programmable network processor and method for customizing a network processor
US20040030861A1 (en) * 2002-06-27 2004-02-12 Bart Plackle Customizable computer system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Electrically Erasable Programmable Read-Only Memory", THE FREE ON-LINE DICTIONARY OF COMPUTING, 22 April 1995 (1995-04-22) *
LU L.: "Crosstalk Versus Interline Space in Ultra High Speed Digital PCBs", IEEE, 1998, pages 1 *

Also Published As

Publication number Publication date
WO2007026226A2 (en) 2007-03-08

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