WO2007013381A1

WO2007013381A1 - Image display apparatus, method of generating a two-dimensional pixel data array and a compatible processor

Info

Publication number: WO2007013381A1
Application number: PCT/JP2006/314538
Authority: WO
Inventors: Shuhei Kato; Kouichi Usami
Original assignee: Ssd Company Limited
Priority date: 2005-07-28
Filing date: 2006-07-18
Publication date: 2007-02-01

Abstract

A combined image is generated by interleaving the two sprites SP1 and SP2 to be combined in a display process so that the respective pixels thereof are arranged in turn one pixel after another to realize the displaying of high resolution images. Specifically, pixel data is assigned to left and right pixels of each pixel set in accordance with the flip parameter Fs[0] in order to generate a combined image. The resolution is switched in accordance with the flip parameter Fs[1] by assigning pixel data to the respective pixels of each pixel set on a 'pixel to pixel' basis (in a high resolution mode) or by assigning pixel data to the respective pixel set on a 'pixel set to pixel set' basis (in a standard resolution mode). The standard resolution mode is used for an image which is satisfactorily displayed even with a lower resolution, and the high resolution mode is used for an image which requires a higher resolution for satisfactorily displaying it.

Description

DESCRIPTION

IMAGE DISPLAY APPARATUS, METHOD OF GENERATING A TWO-DIMENSIONAL PIXEL

DATA ARRAY AND A COMPATIBLE PROCESSOR

Technical Field

The present invention relates to an image display apparatus, a method of generating a two-dimensional pixel data array, a compatible processor and the related arts in which the resolution can be adjusted.

Background Art

Generally speaking, a resolution of an image displayed on a screen is changed by changing a frequency of a dot clock, as illustrated in Fig. 1 of Japanese Patent Published Application No. Hei 9-44117. Because of this, the resolution can be changed only throughout the entirety of the screen in which images are displayed.

However, the same screen may include an image which is satisfactorily displayed even with a lower resolution and an image which requires a higher resolution for satisfactorily displaying it. In such a case, if the resolution can be changed only throughout the entirety of the screen as has been discussed above, the resolution must be set to the higher resolution.

Thereby, high resolution data must be prepared also for an image which can be satisfactorily ^• displayed even with a lower resolution. Because of this, the amount of data tends to increase as well as the memory capacity as required. This entails an increase in costs. In addition to this, the increase in the amount of data results in the increase in the processing load on a processor and the load of data transfer on the bandwidth of the bus. It is therefore an object of the present invention to provide an image display apparatus, a method of generating a two-dimensional pixel data array, a compatible processor and the related arts in which different resolutions can be set respectively for images displayed in the same screen so that the memory capacity as required, the processing load on a processor and the load on the bus band can be reduced.

Disclosure of Invention

In accordance with an aspect of the present invention, an image display apparatus is operable to display a combined image which is formed by combining "N" image data items on a display screen, where "N" is two or a larger integer, wherein the display screen is composed of a plurality of lines which are arranged in a first direction and each of which is composed of a plurality of pixel sets, which are arranged in a second direction and each of which consists of "N" pixels arranged in a predetermined order from a zeroth to an (N-I) th pixel, the second direction being perpendicular to the first direction, wherein each of the image data items is associated with pixel designation information which designates the M-th pixel of each pixel set, where "M" is an integer from "0" to (N-I) and takes a different value for each image data item, and wherein a displaying process is performed by making use of each of pixel data items, of which one of the image data items is composed, as data to be used for displaying the M-th pixel of each of the pixel sets corresponding to the one of the image data items as designated by the pixel designation information which is associated with the one of the image data items.

In accordance with this configuration, a plurality of image data items is combined by assigning the pixel data to the respective pixels of each pixel set on the basis of the pixel designation information which is differently provided for each of the image data items to be combined. In other words, a combined image is generated by interleaving the respective image data items to be combined so that the respective pixels thereof are arranged in turn one pixel after another. Accordingly, the image data items to be combined can be prepared in the exactly same format.

In this case, while any value can be assigned to each of the pixels of which one pixel set consists, the same pixel data can be assigned to all the pixels of which one pixel set consists. In other words, a combined image is generated by interleaving the same image data item one pixel after another. In this case, it is not needed to prepare a plurality of the same image data items, but only one image data item suffices for this purpose so that it is possible to reduce the memory capacity and lessen the processing load. Incidentally, it is assumed here that one pixel is displayed in a fixed time period. While the displaying of images can be realized in this manner at a lower resolution as compared with the case where any value can be assigned to each of the pixels of which one pixel set consists (in the high resolution ) , even in the case where the displaying of lower resolution images is implemented, it is possible to use image data which has the exactly same format between the displaying of lower resolution images and the displaying of high resolution images.

Incidentally, if the time required for displaying one pixel set is fixed, the resolution of the combined image is proportional to the number "N" of pixels of which one pixel set consists. For example, comparing the case where N = 2 and the case where N = 3, the resolution is higher in the case where N = 3.

In the image display apparatus as described above, each of the image data items is associated with resolution setting information which designates either a standard resolution mode for displaying images at a predetermined resolution or a high resolution mode for displaying images at a resolution higher than the predetermined resolution, wherein the image display apparatus serves to: when an image data item is associated with the resolution setting information designating the standard resolution mode, irrespective of the content of the pixel designation information which is associated with this image data item, assign the same pixel data item corresponding to the pixel set to the zeroth to (N-I) th pixels of the pixel set for each pixel set corresponding to this image data item, and when an image data item is associated with the resolution setting information designating the high resolution mode, assign the pixel data items of this image data item to the M-th pixels of the pixel sets corresponding to this image data item as designated by the pixel designation information which is associated with this image data item.

In accordance with this configuration, the resolution is switched in accordance with the resolution setting information by assigning pixel data to the respective pixels of each pixel set on a "pixel to pixel" basis (in the high resolution mode) or by assigning pixel data to the respective pixel set on a "pixel set to pixel set" basis (in the standard resolution mode) . In this case, when the displaying is performed in the standard resolution mode, it is not required to prepare a plurality of the same image data items and associate the resolution setting information to these image data items respectively, but it suffices that only one image data is prepared and associated with the resolution setting information. It is possible to change the resolutions for the respective images independently in the same screen and optimize the size of the image data by utilizing the standard resolution mode for an image which is satisfactorily displayed even with a lower resolution and utilizing the high resolution mode for an image which requires a higher resolution for satisfactorily displaying it, in accordance with the resolution setting information. Accordingly, it is possible to

^' reduce the memory capacity for storing image data and lessen the processing load on the processor, and in addition to this, to lessen the load on the bandwidth of the bus for transferring image data. In the image display apparatus as described above, a display mode switching unit operable to switch between a first display mode and a second display mode is further provided, wherein when the first display mode is set, irrespective of the content of the resolution setting information associated with an image data item, the same pixel data item corresponding to the pixel set is assigned to the zeroth to (N-I) th pixels of the pixel set for each pixel set corresponding to this image data item.

In accordance with this configuration, when the first display- mode is, it is possible to run any software, with no modification, which is designed for the previous generation processor including the previous generation image display apparatus which is capable of displaying images only in the standard resolution mode but which is not implemented with a high resolution mode. Because of this, while retaining backward compatibility with software which is runnable by the previous generation processor, it is possible to display images at a high resolution in the second display mode.

In the image display apparatus as described above, the display mode switching unit includes a display mode control register which can be externally and dynamically^" set to data indicative of either the first display mode or the second display mode, and wherein a displaying process is performed in either the first display mode or the second display mode on the basis of the data set in the display mode control register.

In accordance with this configuration, while software is run by an external unit (for example, a CPU or the like which is incorporated in a processor having a built-in image display apparatus) , it is possible for the software to dynamically switch between the first display mode and the second display mode.

The image display apparatus as described above further comprises: "N" resolution setting information storing registers provided corresponding to the "N" image data items and each of the "N" resolution setting information storing registers operable to store the resolution setting information associated with the image data item corresponding thereto; and "N" pixel designation information storing registers provided corresponding to the "N" image data items and each of the "N" pixel designation information storing registers operable to store the pixel designation information associated with the image data item corresponding thereto, wherein the resolution setting information storing registers and the pixel designation information storing registers can be externally accessed in order to dynamically change the information stored therein.

In accordance with this configuration, while software is run by an external unit (for example, a CPU or the like which is incorporated in a processor having a built-in image display apparatus) , it is possible for the software to dynamically switch between the standard resolution mode and the high resolution mode, and dynamically change the content of the pixel designation information, with respect to the "N" image data items (for example, the image data of the background screens of the following embodiment) . The image display apparatus as described above further comprises a memory, wherein said memory includes: "N" resolution setting information storing areas provided corresponding to the "N" image data items and each of the "N" resolution setting information storing areas operable to store the resolution setting information associated with the image data item corresponding thereto; and "N" pixel designation information storing areas provided corresponding to the "N" image data items and each of the "N" pixel designation information storing areas operable to store the pixel designation information associated with the image data item corresponding thereto. In accordance with this configuration, the resolution setting information storing area and/or the pixel designation information storing area can be dynamically changed by software which is run by an external unit (for example, a CPU or the like which is incorporated in a processor having a built-in image display apparatus) , and it is possible to dynamically switch between the standard resolution mode and the high resolution mode, and dynamically change the content of the pixel designation information, with respect to the "N" image data items (for example, the image data items of sprites in the case of the following embodiment) . In the above image display apparatus, the displaying process is performed in the first display mode by treating the resolution setting information and the pixel designation information as information for controlling the predetermined image display process.

In accordance with this configuration, for the purpose of enhancing the functionality, it is possible to utilize without modification the storage unit for storing the information for controlling the predetermined image display process and the data path for processing the information stored therein, and thereby to realize a processor (for example, the processor used in the following embodiment) which is designed on the basis of the previous generation processor including the previous generation image display apparatus but extended in functionality without substantial circuit modification.

In the above image display apparatus, the predetermined image display process Is image inversion in the first direction and/or the second direction.

The image display apparatus as described above further comprises a zeroth to an (N-I) th storage unit, wherein the pixel data of an image data item is stored in the M-th storage unit as designated by the pixel designation information which is associated with this image data item.

In accordance with this configuration, it is possible to realize an image display apparatus (for example, the graphics processor used in the following embodiment) which is capable of displaying images at a high resolution only by adding .another storage unit having the same configuration as the storage unit of the previous generation image display apparatus .

The image display apparatus as described above further comprises: a read and write control unit operable to receive read and write requests for the storage units, and read and write operations for the storage units; a pixel data write request unit operable to issue the write request to the read and write control unit in order to write the pixel data of an image data item in the M-th storage unit as designated by the pixel designation information which is associated with this image data item; and a pixel data read request unit operable to issue the read request to the read and write control unit in order to read the pixel data from the zeroth to (N-I) th storage units.

In accordance with this configuration, the read and write operations of the storage units can be realized with a simple circuit configuration in an effective manner. In the image display apparatus as described above, each of the image data items is associated with resolution setting information which designates either a standard resolution mode for displaying images at a predetermined resolution or a high resolution mode for displaying images at a resolution higher than the predetermined resolution, and wherein the pixel data write request unit is operable to issue the write request for writing the pixel data of an image data item to all the zeroth to (N-I) th storage units, when the resolution setting information designates the standard resolution mode, irrespective of the content of the pixel designation information, and issue the write request for writing the pixel data of an image data item to the M-th storage unit as designated by the pixel designation information which is associated with this image data item, when the resolution setting information designates the high resolution mode.

In accordance with this configuration, since the same pixel data is stored in the corresponding positions of all the zeroth to (N-I) th storage units in the standard resolution mode, the same pixel data is read from the zeroth to (N-I) th storage units, and as a result the displaying of images becomes possible at a resolution lower than that in the high resolution mode. On the other hand, since arbitrary pixel data is stored in each of the zeroth to (N-I) th storage units in the high resolution mode, different data is read from different unit of the zeroth to (N-I) th storage units, and as a result the displaying of images becomes possible at the high resolution mode.

The image display apparatus as described above further comprises a display mode switching unit operable to switch between a first display mode and a second display mode, wherein the pixel data write request unit is operable to issue the write request to the read and write control unit to write the pixel data of an image data item to all the zeroth to (N-I) th storage units, when the first display mode is set, irrespective of the content of the resolution setting information associated with this image data item.

In accordance with this configuration, since the same pixel data is stored in the corresponding positions of all the zeroth to (N-I) th storage units in the first resolution ^• mode, the same pixel data is read from the zeroth to (N-I) th storage units, and as a result the displaying of images becomes possible at a resolution corresponding to the standard resolution mode. Accordingly, when the first display mode is set, it is possible to run any software, with no modification, which is designed for the previous generation processor including the previous generation image display apparatus which is capable of displaying images only in the standard resolution mode but which is not implemented with a high resolution mode. Because of this, while retaining backward compatibility with software which is runnable by the previous generation processor, it is possible to display images at a high resolution in the second display mode. In the image display apparatus as described above, the pixel data read request unit is operable to receive the pixel data which is read from the zeroth to (N-I) th storage units and sequentially output this pixel data in a time-interleaved manner to a subsequent stage. In accordance with this configuration, a combined image is generated by sequentially butputting the pixel data which is read from the zeroth to (N-I) th storage units and used for making up a pixel set to the subsequent stage in a time-interleaved manner in order to form the pixel set. Namely, in an image display apparatus which performs image processing on the basis of the scan position of the scan line, it is possible to accomplish the displaying of images at a high resolution only with a simple circuit configuration.

In the image display apparatus as described above, each of the pixel data items, of which one of the image data items is composed, includes color data which directly or indirectly designates the display color of a pixel and depth data which designates a display priority, and wherein when receiving the write request from the pixel data write request unit, the read and write control unit reads the depth data stored in the location for writing of said storage unit, compares the depth data as read and the depth data contained in the pixel data which the pixel data write request unit requests to write, and if the depth data contained in the pixel data which the pixel data write request unit requests to write is given a display priority higher than the depth data as read, the pixel data which the pixel data write request unit requests to write is written to the location for writing of the storage unit.

In accordance with this configuration, when there are pixel data items to be displayed in the same position, the pixel data item having a higher display priority can be displayed irrespective of the order of writing pixels.

In the image display apparatus as described above, after the pixel data is read from the location for reading of said storage unit in accordance with the read request from the pixel data read request unit, the read and write control unit initializes the depth data stored in the location for reading of the storage unit to a value indicative of the lowest display priority.

In accordance with this configuration, by initializing the data of a pixel which need no longer be used after completing the read operation of the data, new pixel data can be written to the storage location of the storage unit which is initialized. Accordingly, a storage unit for one complete line is not necessarily required, but it is possible to provide storage unit having a smaller capacity than required for one complete line and cyclically use it. Thereby, the cost can be reduced. In accordance with another aspect of the present invention, a method is provided for generating a two-dimensional pixel data array for forming a display screen which includes images having different effective resolutions, wherein each of the image data items having the same resolution in the row direction of the two-dimensional pixel data array is associated with a flag designating twice the same resolution and a flag indicative of either an odd or an even numbered element of each row of the two-dimensional pixel data array, the method comprising: when the flag designating twice the same resolution is turned off, assigning each of the pixel data items of the image data item to two adjacent elements of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to the same resolution; and when the flag indicative of twice the same resolution is turned on, in accordance with the flag indicative of either an odd or an even numbered element, assigning each of the pixel data items of the image data item to an odd or an even numbered element of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to twice the same resolution.

In accordance with this configuration, it is possible to generate a two-dimensional pixel data array for forming a display screen which includes images having different effective resolutions by making use of image data items having a predetermined resolution.

In accordance with a further aspect of the present invention, a compatible processor is operable to run the software that can be run on a previous generation processor which is capable of generating images at a predetermined resolution, and operable to generate images at twice the predetermined resolution, said compatible processor comprising: an image display unit operable to generate a two- dimensional pixel data array for forming a display screen corresponding to twice the predetermined resolution in the row direction of the two-dimensional pixel data array; and a data processing unit operable to process data in accordance with a predetermined program and output image data items having the same resolution which corresponds to the predetermined resolution to the image display unit, wherein there is a display mode control register for storing display mode control information indicative of either a compatible display mode in which it is possible to run the software that can be run on the previous generation processor or an extended display mode in- which it is possible to display images at twice the predetermined resolution in the row direction of the two-dimensional pixel data array, wherein when the display mode control information indicates the extended display mode, the image display unit makes use of a value stored in a field of the image data item as information indicative of either odd or even numbered columns of the two- dimensional pixel data array, wherein when the display mode control information indicates the extended display mode, the image display unit can generate a combined image having twice the predetermined resolution from a pair of image data items which are associated respectively with the odd and even numbered columns by the information stored in the field indicative of either odd or even numbered columns by assigning the pixel data items of one of the image data item pair associated with the odd numbered columns to odd numbered elements of each row of the two-dimensional pixel data array corresponding to the positions of the display screen where the pixel data items of the one of the image data item pair are * to be displayed, and assigning the pixel data items of the other image data item associated with the even numbered columns to even numbered elements of each row of the two- dimensional pixel data array corresponding to the positions of the display screen where the pixel data items of the other image data item are to be displayed, wherein when the display mode control information indicates the compatible display mode, the image display unit assigns each of the pixel data items of the image data item to two adjacent elements of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to the predetermined resolution.

In accordance with this configuration, it is possible to design, only with minimal change, a compatible processor capable of displaying images at a higher resolution than a previous generation processor while retaining backward compatibility with the previous generation processor .

Brief Description of Drawings

The novel features of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reading the detailed description of specific embodiments in conjunction with the accompanying" drawings, wherein:

Fig. 1 is a block diagram showing the overall configuration of a processor 1000, which is a data processing unit in accordance with an embodiment of the present invention.

Fig. 2A is an example displayed of a sprite SPl in the compatible display mode.

Fig. 2B is an example displayed of a sprite SP2 in the compatible display mode.

Fig. 3A is an example displayed of the sprite SPl in the extended display mode when the flip parameters Fs [1:0] = ObIO.

Fig. 3B is an example displayed of the sprite SP2 in the extended display mode when the flip parameters Fs [1:0] =.0bll. Fig. 4 is a view for showing an example of a double resolution image drawn by displaying the sprite SPl of Fig. 3A and the sprite SP2 of Fig. 3B at the same coordinates.

Fig. 5 is a block diagram showing the front part of the internal configuration of the graphics processor 3 of Fig. 1. Fig. 6 is a block diagram showing the latter part of the internal configuration of the graphics processor 3 of Fig. 1.

Fig. 7 is a view for showing the structure of the zeroth entry defined in the sprite memory 52 of Fig. 5.

Fig. 8 is a view which shows the structures of the FSC registers 57 and 61 of Fig. 5.

Fig. 9 is a time chart for explaining the operation of the pixel buffer controller 76 of Fig. 6.

Fig. 10 is a time chart for explaining the operation of the view driver 80 of Fig. 6.

Best Mode for Carrying Out the Invention

In what follows, several embodiments of the present invention will be explained in conjunction with the accompanying drawings.

Meanwhile, like references indicate the same or functionally similar elements throughout the respective drawings, and therefore redundant explanation is not repeated. Also, when it is necessary to specify a particular bit or bits of a signal in the description or the drawings, [a] or [a:b] is suffixed to the name of the signal. While [a] stands for the a-th bit of the signal, [a:b] stands for the a-th to b-th bits of the signal. In regard to the hexadecimal expression, "H" is suffixed to the number in order to distinguish it from the decimal expression. Also, while a prefixed "Ob" is used to designate a binary number, a prefixed "Ox" is used to designate a hexadecimal number.

Fig. 1 is a block diagram showing the overall configuration of a processor 1000, which is a data processing unit in accordance with an embodiment of the present invention. As shown in Fig. 1, this processor 1000 includes a central processing unit (CPU) 1, a graphics processor 3 (an embodiment of the image display apparatus as recited in the appended claims) , a pixel plotter 5, a sound processor 7, a DMA (direct memory access) controller 9, a first bus arbiter 13, a second bus arbiter 14, a backup control circuit 15, a main memory 17, a timer circuit 19, an analog-to-digital converter (ADC) 20, an input/output control circuit 21, an external memory interface circuit 23, a clock driver 29, a PLL (phase-locked loop) circuit 27, a low voltage detection circuit 25, a first bus 31 and a second bus 33.

The CPU 1 performs various operations and controls the overall system in accordance with a program stored in the memory MEM. The CPU 1 is a bus master of the first bus 31 and the second bus 33, and can access the resources connected to the respective buses. In the present embodiment, the main memory 17 and the external memory 45 are generally referred to as the "memory MEM" in the case where they need not be distinguished.

The graphics processor 3, which is related to one of the characteristic features of the present invention, is a bus master of the first bus 31 and the second bus 33, and serves to convert the data stored in the memory MEM into graphic data, and generate a video signal VD to be output to a television receiver (not shown in the figure) on the basis of the graphic data. Also, the graphics processor 3 is controlled by the CPU 1 through the first bus 31, and capable of issuing an interrupt request signal "INRQ" to the CPU 1.

In this case, the graphic data is generated by synthesizing a background screen(s), a sprite (s) and a bitmap screen. The background screen covers the entirety of the screen of a television receiver and comprises a two-dimensional array. And each array element comprises of a rectangular set of pixels. There are a first background screen and a second background screen respectively prepared as the background screen for showing depths in the background. In what follows, these are referred to simply as the "background screen" unless it is necessary to distinguish them. A sprite consists of a rectangular set of pixels which can be relocated in any position of the screen of the television receiver. Each rectangular set of pixels constituting the background screen and the sprite is referred to as a character. For example, there are characters prepared as 8 x 8 pixels, 8 x 16 pixels, 16 x 8 pixels and 16 x 16 pixels. The bitmap screen consists of a two- dimensional pixel array of which the size and location as displayed can be freely designated.

The graphics processor 3 serves to generate display images of the background screens and sprites respectively in either a compatible display mode or an extended display mode. That is, in the compatible display mode, the display images are generated always with a standard resolution (for example, eight clocks per pixel) . In this case, the clock signal is a clock signal "CK40" to be described below, unless otherwise specified.

On the other hand, in addition to a mode (a standard resolution mode) in which display images are generated with the standard resolution, the extended display mode supports a mode (a double resolution mode) in which display images are generated with a double resolution (for example, four clocks per pixel) which is twice the standard resolution in the horizontal direction. In the extended display mode, either the standard resolution or the double resolution mode can be set separately for each sprite. In the same way, in the extended display mode, either the standard resolution or the double resolution mode cab be set for the background screens.

Namely, in the extended display mode, it is possible to display a screen including a sprite with the standard resolution, a sprite with the double resolution and a background screen with the standard resolution, a screen including a sprite with the standard resolution, a sprite with the double resolution and a background screen with the double resolution, and so forth. Needless to say, all the display images can be also displayed only with the standard resolution or only with the double resolution.

Accordingly, by displaying, with a low resolution, images which need not be displayed with a high resolution, it is possible to reduce the size of image data in the memory MEM, and lessen the load of the drawing process and the load of data transfer on the bandwidth of the bus. In addition, since the compatible display mode is a display mode which is full compatible with a previous generation processor, it is possible to display images with a high resolution in the extended display mode while retaining backward compatibility with software which can be run by the previous generation processor. The previous generation processor will be described below.

The pixel plotter 5 is controlled by the CPU 1 through the first bus 31, and capable of drawing pixel data as given from the CPU 1. In this example, the drawing operation can be performed separately for each pixels. Pixel data as described herein is data representing the display color of one pixel by "M" bits (M is one or a larger integer) . In the present embodiment, M = 1 to 8 as an example.

Also, the pixel plotter 5 makes it possible to perform highspeed drawing and effectively use the buses (the first bus 31 and the second bus 33) by virtue of a cache system. Furthermore, the pixel plotter 5 is a bus master of the first bus 31 and the second bus 33, and capable of autonomously writing data from a cache (not shown in the figure) to the memory MEM and from the memory MEM to the cache.

The sound processor 7 is a bus master of the first bus 31 and the second bus 33, and serves to convert data stored in the memory MEM into sound data, and generate and output an audio signal "AU" on the basis of the sound data.

The sound data is synthesized by pitch conversion and amplitude modulation of PCM (pulse code modulation) data serving as the base data of tone quality. For the amplitude modulation, an envelope control function for reproducing waveforms of a music instrument is provided in addition to a volume control function performed in response to an instruction of the CPU 1.

Furthermore, the sound processor 7 is controlled by the CPU 1 through the first bus 31, and capable of issuing an interrupt request signal "INRQ" to the CPU 1.

The DMA controller 9 controls data transfer from the external memory 45 connected to an external bus 43 to the main memory 17. The external memory 45 may be implemented with, for example, an SRAM (static random access memory) , a DRAM (dynamic random access memory) , a ROM (read only memory) or any other appropriate memory, or implemented as a combination of any number of such memories. On the other hand, the DMA controller 9 has the function of outputting, to the CPU 1, an interrupt request signal "INRQ" indicative of the completion of the data transfer. Particularly, the DMA controller 9 is a bus master of the first bus 31 and the second bus 33, and controlled by the CPU 1 through the first bus 31.

The main memory 17 may be implemented with one or any necessary combination of a mask ROM, an SRAM and a DRΔM in accordance with the system requirements. In the present embodiment, the main memory 17 is composed of an SRAM.

The backup control circuit 15 deactivates the main memory 17 when the low voltage detection circuit 25 to be described below detects a low voltage condition. On the other hand, the main memory 17 is supplied with a power supply voltage from the battery 41. Accordingly, the data stored in the main memory 17 composed of the SRAM can be maintained even after the power supply voltages VccO and Vccl are taken away.

The first bus arbiter 13 accepts first bus use request signals from the respective bus masters of the first bus 31, performs bus arbitration among the requests, and issues a first bus use acknowledge signal to one of the respective bus masters for each bus cycle. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels (priority rankings) assigned to a plurality of the bus masters in regard to the use of the first bus 31, the first bus arbiter 13 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected.

Each bus master is permitted to access the first bus 31 after receiving the first bus use acknowledge signal. In this example, the first bus use request signal and the first bus use acknowledge signal are illustrated as first bus arbitration signals "FAB" in Fig. 1.

For example, the first bus 31 consists of an 8-bit data bus, a 15-bit address bus, and a control bus (not shown in the figure) . The second bus arbiter 14 accepts second bus use request signals from the respective bus masters of the second bus 33, performs bus arbitration among the requests, and issues a second bus use acknowledge signal to one of the respective bus masters for each bus cycle or each sequence of a predetermined number of bus cycles corresponding to the number of bytes as required. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels (priority rankings) assigned to a plurality of the bus masters in regard to the use of the second bus 33, the second bus arbiter 14 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected.

Each bus master is permitted to access the second bus 33 after receiving the second bus use acknowledge signal. In this example, the second bus use request signal and the second bus use acknowledge signal are illustrated as second bus arbitration signals "SAB" in Fig.

1.

For example, the second bus 33 includes a data bus of 16 bits, an address bus of 27 bits and a control bus (not shown in the figure) . The timer circuit 19 has the function of repeatedly outputting an interrupt request signal "INRQ" to the CPU 1 with a configured interval. The setting of the time interval and so forth is performed by the CPU 1 through the first bus 31.

The ADC 20 converts an analog input signal to a digital signal. This digital signal is read by the CPU 1 through the first bus 31. In addition, the ADC 20 has the function of outputting an interrupt request signal "INRQ" to the CPU 1. In addition, an analog signal as output from an external device is input to the ADC 20, for example, through any one of six analog ports "AINO" to "AIN5" (not shown in the figure) . The input/output control circuit 21 serves to perform the input and output operations of input and output signals to enable the communication with external input/output devices and/or external semiconductor devices . The read and write operations of input and output signals are controlled by the CPU 1 through the first bus 31. Also, the input/output control circuit 21 has the function of outputting an interrupt request signal "INRQ" to the CPU 1. Incidentally, the input and output signals are input and output, for example, through programmable input/output ports "IOO" to "1023" (not shown in the figure) . The low voltage detection circuit 25 monitors the power supply voltages VccO and Vccl, and issues a reset signal "LPW" to the PLL circuit 27 and so forth and a reset signal "RES" to the other circuit elements of the entire system when either the power supply voltage VccO or Vccl falls below corresponding one of reference voltages which are determined in advance individually for the respective power supply voltages VccO and Vccl. The reset signal "LPW" is output in order to protect the system at power up or down and perform the initialization of the system. The reset signal "RES" is output in order to initialize the system at power up or after restart. When the reset signal "LPW" is made active, the reset signal "RES" is also made active at the same time and maintained in its active state, even after the reset signal "LPW" is deactivated, for a short time.

In this case, the power supply voltage VccO is for example + 2.5

V, which is supplied mainly to digital circuits in the processor 1000. On the other hand, the power supply voltage Vccl is for example + 3.3

V, which is supplied mainly to analog circuits and I/O circuits in the processor 1000.

The PLL "circuit 27 generates a high frequency clock signal "ck40" by multiplication of the sinusoidal signal as obtained from a crystal oscillator 37, and generates a clock signal "ck20" by dividing the clock signal "ck40" by 2.

The clock driver 29 receives the clock signals "ck40" and "ck20" from the PLL circuit 27, amplifies these signals to a sufficient driving capability, and supplies these signals to the respective blocks as internal clock signals "CK40" and "CK20".

The external memory interface circuit 23 has the function of connecting the second bus 33 to the external bus 43.

Next, the data transfer paths within the processor 1000 shown in Fig. 1 will be explained. For example, in the case where the CPU 1 controls, as a bus master, one of the other functional blocks (the graphics processor 3, the pixel plotter 5, the sound processor 7, the DMA controller 9, the first bus arbiter 13, the second bus arbiter 14 and the like) respectively connected to the first bus 31 as a bus slave, the CPU 1 outputs write data to the first bus arbiter 13 for writing the write data to the control register of the functional block and, after arbitration, the first bus arbiter 13 transmits the write data to the control register through the first bus^' 31, while the CPU 1 receives read data transmitted from the control register of the functional block after arbitration through the first bus 31 and the first bus arbiter 13. On the other hand, each of the graphics processor 3, the pixel plotter 5, the sound processor 7 and the DMA controller 9 has the function of outputting the first bus use request signal to the first bus arbiter 13 as a bus master of the first bus 31.

When accessing the main memory 17, a bus master outputs write data to the first bus arbiter 13 for writing the write data to the main memory 17 and the first bus arbiter 13 transmits the write data to the main memory 17 after arbitration through the first bus 31, while a bus master receives read data from the main memory 17 after arbitration through the first bus 31 and the first bus arbiter 13. Also, when accessing the external memory 45, a bus master outputs write data to the second bus arbiter 14 for writing the write data to the external memory 45 and the second bus arbiter 14 transmits the write data to the external memory 45 after arbitration through the second bus 33, the external memory interface circuit 23 and the external bus 43, while a bus master receives the read data from the external memory 45 after arbitration through the external bus 43, the external memory interface circuit 23, the second bus 33 and the second bus arbiter 14. '

By the way, next is a detailed description of the compatible display mode, the extended display mode, the standard resolution mode and the double resolution mode as described above.

Although will be described later in detail, the graphics processor 3 has, within it, a display mode control register 101 for storing display mode control information "CHRMODE". The display mode control information "CHRMODE" is set to "0" to enter the compatible display mode, and set to "1" to enter the extended display mode.

Each of the respective sprites and background screens has 2-bit flip parameters Fs [1:0]. The flip parameters Fs [1:0] are parameters which are used to designate display inversion in the horizontal direction (right and left direction) , display inversion in the vertical direction (high and low direction) , display inversion in the horizontal and vertical direction (right and left direction and high and low direction) , or display non-inversion.

In the compatible display mode, the flip parameters Fs [1:0] are functioning as parameters indicative of display inversion as in accordance with the original purpose thereof. However, in the extended display mode, the flip parameters Fs [1:0] have another function. In advance of explaining this function, a brief explanation is provided of pixel buffers 78L and 78R which will be described latter in detail (refer to Fig. 6) .

The pixel buffer 78L consists of the number of pixel buffer units, which is smaller than the number of pixels of one line of the display screen, and is used as a drawing area. One pixel buffer unit stores the depth value (4 bits) and color code (8 bits) of one pixel. The pixel buffer 78R has the same structure as the pixel buffer 78L.

Returning to the explanation of the flip parameters Fs [1:0], in the extended display mode, the flip parameter Fs[I] is a bit which is used to switch between the standard resolution mode and the double resolution mode, and the flip parameter Fs[O] is a bit which is used in the double resolution mode to select either the left hand pixel or the right hand pixel of a pixel set consisting of these two pixels arranged in the horizontal direction.

Generally speaking, one pixel set consists of "N" pixels which are arranged in a predetermined order from a zeroth to an (N-I) th pixel. "N" is two or a larger integer. In the case of the present embodiment, N = 2, and the respective pixels are arranged in the horizontal direction. Accordingly, in the double resolution mode, the flip parameter Fs[O] is used to select either an odd or an even numbered pixel in a line of the display screen. One line is made up of pixel sets arranged in the horizontal direction, and the display screen is made up of a plurality of lines arranged in the vertical direction.

The pixel buffer 78L is used to store (draw) the data (the depth value and the color code) for displaying the left hand pixels of pixel sets, and the pixel buffer 78R is used to store (draw) the data (the depth value and the color code) for displaying the right hand pixels of the pixel sets. From this configuration, in the extended display mode, the flip parameter Fs[O] can be said as a bit indicative of which the pixel buffer 78L or 78R is used for drawing. Here, a specific example will be explained in which the depth value and color code of one pixel is referred to as pixel data. Incidentally, as described above, one sprite consists of one character. On the other hand, each of the background screens consists of a two- dimensional array of characters. In what follows, unless it is necessary to distinguish between the character of a sprite and the character of a background screen, these characters are referred to simply as "characters".

In the case where the display mode control information "CHRMODE" is set to "0" such that images are displayed in the compatible display mode, the pixel data of characters of all the sprites and background screens is assigned to the left hand pixels of pixel sets (namely, written to the pixel buffer 78L) , and the same pixel data of the same characters is assigned to the right hand pixels of the same pixel sets (namely, written to the pixel buffer 78R) . That is to say, in the compatible display mode, the same pixel data is written to the corresponding positions of the pixel buffers 78L and 78R.

In the case of the present embodiment, the coordinates (X, Y) of each character in the display screen are set in units of pixel sets, and therefore the "corresponding positions" are positions which represents the same coordinates (X, Y) in units of pixel sets but actually point respectively to the adjacent pixels of the display- screen in the pixel set. Meanwhile, this is true also in the case of the extended display mode. "X" represents the horizontal coordinate, and "Y" represents the vertical coordinate. Fig. 2A is an example displayed of a sprite SPl in the compatible display mode, and Fig. 2B is an example displayed of a sprite SP2 in the compatible display mode. In Fig. 2A and Fig. 2B, one square represents one pixel set in the display screen. It is assumed here that one pixel set is displayed in a fixed time period on the basis of the video signal VD (for example, eight clocks per pixel set) . In addition, each of the sprites SPl and SP2 consists of 16 x 16 pixels (this "pixel " does not mean a pixel in the display screen but means a pixel as a constituent element of a sprite) and represents a letter "A". As shown in Fig. 2A, in the compatible display mode, it will be understood that the same pixel data is assigned to the right and left hand pixels of one pixel set. In other words, in the compatible display mode, the same pixel data is written to the corresponding positions of the pixel buffers 78L and 78R. Furthermore, in other words, the same character is displayed adjacent to each other in order to represent the letter "A". Meanwhile, this is true also in the case of the sprite SP2 of Fig. 2B. The same process is performed also for the background screen so that, in the compatible display mode, the same pixel data is written to the corresponding positions of the pixel buffers 78L and 78R.

On the other hand, in the case where the display mode control information "CHRMODE" is set to "1" such that images are displayed in the extended display mode, for such characters that have the flip parameters Fs[I] set to "0" (i.e., the standard resolution mode is selected for such characters), the same pixel data is written to the corresponding positions of the pixel buffers 78L and 78R for these characters irrespective of the set values of the flip parameters Fs[O]. Accordingly, with regard to such characters, there is no difference from the compatible display mode as illustrated in Fig. 2. However, even in the case where the display mode control information "CHRMODE" is set to "1" such that images are displayed in the extended display mode, such characters that have the flip parameters Fs[I] set to "1" (i.e., the double resolution mode is selected for such characters) are handled in accordance with the set values of the flip parameters Fs[O] as follows. Namely, when the flip parameter Fs[O] is set to "0", the pixel data of the character is written to the pixel buffer 78L, and when the flip parameter Fs[O] is set to "1", the pixel data of the character is written to the pixel buffer 78R. Fig. 3A is an example displayed of the sprite SPl in the extended display mode when the flip parameters Fs [1:0] = ObIO

(indicative of the double resolution mode and drawing in the pixel buffer 78L) , and Fig. 3B is an example displayed of the sprite SP2 in the extended display mode when the flip parameters Fs [1:0] = ObIl (indicative of the double resolution mode and drawing in the pixel buffer 78R) .

In Fig. ^• 3A and Fig. 3B, one rectangle represents one pixel in the display screen. Also, it is assumed here that one pixel is displayed in a fixed time period on the basis of the video signal VD (for example, four clocks per pixel, i.e., eight clocks per pixel set). In addition, each of the sprites SPl and SP2 consists of 16 x 16 pixels (this "pixel" does not mean a pixel in the display screen but means a pixel as a constituent element of a sprite) and represents a letter "A". In other words, the pixel data of the character of the sprite SPl shown in Fig. 3A is identical with the pixel data of the character of the sprite SPl shown in Fig. 2A. The pixel data of the character of the sprite SP2 shown in Fig. 3B is identical with the pixel data of the character of the sprite SP2 shown in Fig. 2B. As shown in Fig. 3A, the pixel data of the sprite SPl is stored in the pixel buffer 78L and displayed as the left hand pixel of the pixel set if the flip parameters Fs [1:0] = ObIO in the extended display mode. On the other hand, as shown in Fig. 3B, the pixel data of the sprite SP2 is stored in the pixel buffer 78R and displayed as the right hand pixel of the pixel set if the flip parameters Fs [1:0] = ObIl in the extended display mode.

The first background screen and the second the background screen are also provided respectively with the flip parameters Fs [1:0], and processed in the same manner as sprites. Namely, in the extended display mode, the pixel data of each of the first background screen and the second the background screen is written to the pixel buffer 78L or 78R in accordance with the flip parameters Fs [1:0] thereof.

Meanwhile, when sprites or background screens designating the double resolution mode is displayed with the double resolution in the extended display mode, the pixel data is read for display from the pixel buffers 78L and 78R by a view driver 80 which is incorporated in the graphics processor 3 and to be described below. At this time, the view driver 80 receives at the same time both the pixel data from the pixel buffer 78L and the pixel data from the pixel buffer 78R to be displayed at the same coordinates (X, Y) , and performs a double resolution display process by outputting the pixel data, which is received from the pixel buffer 78L, to the subsequent stage in the output timing of the left hand pixel of the pixel set and outputting the pixel data,- which is received from the pixel buffer 78R, to the subsequent stage in the output timing of the right hand pixel of the pixel set.

Fig. 4 is a view for showing an example of a double resolution image drawn by displaying the sprite SPl of Fig. 3A and the sprite SP2 of Fig. 3B at the same coordinates (X, Y) . As shown in Fig. 4, the pixel data of the character of the sprite SPl are assigned respectively to the left hand pixels of the pixel sets since the flip parameters Fs [1:0] = ObIO (indicative of the double resolution mode and drawing in the pixel buffer 78L) in the extended display mode, and the pixel data of the character of the sprite SP2 are assigned respectively to the right hand pixels of the pixel sets since the flip parameters Fs [1:0] = ObIl (indicative of the double resolution mode and drawing in the pixel buffer 78R) in the extended display mode. In other words, the sprite SPl and the sprite SP2 are combined by displaying them at the same coordinates (X, Y) . As a result, it can be realized to display the image (double resolution image) of the letter "A" with the double resolution as compared to that shown in Fig. 2A and Fig. 2B. Meanwhile, as has been discussed above, the time period required for displaying one pixel set is fixed irrespective of whether it is in the compatible display mode or the extended display mode.

By the way, next is a detailed description of the graphics processor 3 of Fig. 1. Fig. 5 and Fig. 6 are block diagrams showing the front part and the latter part of the internal configuration of the graphics processor 3 of Fig. 1.

As shown in Fig. 5 and Fig. 6, the graphics processor 3 includes a sprite DMA controller 50, a sprite memory 52, a sprite generator 54, a first background generator 56, a first picture parameter mixer 58, a second background generator 60, a second picture parameter mixer 62, an address generator 64, a strip generator 66, a character fetcher 68, a pixel generator 70, a transparency controller 72, a draw driver 74, a pixel buffer controller 76, the pixel buffer 78L, the pixel buffer 78R, the view driver 80, a color palette controller 82, a character color palette 84, a bitmap generator 86, a bitmap color palette 88, a pixel mixer 90, a color modulator 92, a noise generator 94, a window generator 96, a video encoder 98, a video timing generator 100, a video position adjuster 102 and a video function generator 104. The first background generator 56, the second background generator 60 and the video function generator 104 include respectively an FSC register 57, an FSC register 61 and the display mode control register 101 which serves to store the display mode control information "CHRMODE". The sprite memory 52 is a local memory of 256 entries x 56 bits, and one entry thereof stores the respective parameters of one sprite (which are sometimes referred to sprite parameters) . In addition, the respective sprite parameters are stored respectively in predetermined positions in one entry. Fig. 7 is a view for showing the structure of the zeroth entry defined in the sprite memory 52 of Fig. 5. As shown in Fig. 7, the zeroth entry is mapped in the address space of the first bus 31. The respective sprite parameters will be explained with reference to Fig. 7. The respective sprite parameters are palette information PO [3:0], the number of bits per pixel BO [2:0], a depth value ZO [3:0], size information SO [1:0], flip information FO [1:0] (explained as the flip parameters Fs [1:0] in the above description), horizontal position information XO [8:0], vertical position information YO [7:0], and address information AO [23: O]. Incidentally, XHO = XO [8], XLO = XO [7: O].

The palette information "PO" is the information for designating a palette entry. As will be described below, in accordance with the present embodiment, the character color palette 84 comprises a local memory used to store 256 colors. The palette information "PO" corresponds to the upper 4 bits of the 8-bit address pointing to one of the entries of the color palette 84. However, depending upon the color mode as selected, the first to fourth bits from the LSB of the palette information "PO" are overwritten by part of the color code.

The number of bits "BO" is the number of bits of each pixel of a character comprising a sprite (bits per pixel: color mode) .

The depth value "ZO" is the information indicative of the depth position in which the character comprising a sprite is located. The depth value "ZO" can be set between "OH" (rearmost position) to "FH"

(topmost position) . When a plurality of pixels is located in the same position, the pixel having the largest depth value "ZO" is selected from thereamong.

The size information "SO" is the information indicative of the size of a character comprising a sprite which is set for example to "00" if the size of the character is 8 pixels (height) * 8 pixels (width) .

The flip information "FO" is the information indicative of the display inversion of a character comprising a sprite, and is set to "00" for indicating that the character is not inverted, "10" for indicating that the character is inverted in the horizontal direction, "01" for indicating that the character is inverted in the vertical direction, and "11" for indicating that the character is inverted in the horizontal direction and in the vertical direction.

However, as described above, while the flip information functions as inversion information in the compatible display mode, the flip information FO functions in the extended display mode to provide a switch bit between the standard resolution mode and the double resolution mode and a selection bit for designating either left or right pixel in the double resolution mode.

The horizontal position information "XO" is indicative of the horizontal coordinate of a sprite in the coordinate system of the character screen, while the vertical position information "YO" is indicative of the vertical coordinate of the sprite in the coordinate system of the character screen.

For the sake of clarity in explanation, the screen generated by combining a sprite (s) and a background screen (s) is referred to herein as a character screen.

The address information "AO" is the information (head address information) indicative of the location of the memory MEM in which the pattern data of the character of a sprite (which is referred to also as character pattern data) is stored. The character pattern data contains the color codes of the respective pixels forming the character. In like manner, the character pattern data forming the first and second background screen contains the color codes of the respective pixels forming each character. The structure of each of the first to the 255th entries of the sprite memory 52 is the same as the structure of the zeroth entry and therefore no redundant description is repeated. However, the addresses mapped to the address space of the first bus 31 are different therebetween . Returning to Fig. 5, the sprite DMA controller 50 serves to DMA transfer the respective sprite parameters stored in the main memory 17 to the sprite memory 52.

The sprite DMA controller 50 outputs an address "FA" and a read/write control signal "FW" to the sprite memory 52 for reading or writing data. In response to these signals, write data "FI" is written to the sprite memory 52, and read data "FO" is read out from the sprite memory 52. ,

The sprite DMA controller 50 arbitrates the access to the sprite memory 52 among the write operation to the sprite memory 52 by DMA transfer, the access to the sprite memory 52 by the CPU 1, and the read operation from the sprite memory 52 by the sprite generator 54, for managing the access to the sprite memory 52 in an integrated fashion.

During the image displaying process, the sprite generator 54 repeatedly increments an address "SA" in order to successively read the data of each entry from the sprite memory 52, and outputs to the first picture parameter mixer 58 the respective sprite parameters "BO", "SO", "FO", "XO", "YO", "ZO", "PO" and "AO" of the sprite (overlapping (or coming to overlap) the pixel buffers 78L and 78R) located in the area where the image displaying process is performed in accordance with the horizontal scan count signal "HP" and the vertical scan count signal "VP". In this description, by "the sprite overlapping the pixel buffers 78L and 78R", it is meant that, while the pixel buffers 78L and 78R are associated with a span of the horizontal coordinate, the sprite overlaps the span of the horizontal coordinate.

However, with regards to the vertical position information "YO", the sprite generator 54 outputs only the lower 5 bits, i.e., "YO [4: O]" rather than the full bits thereof. Meanwhile, the address "SA" is supplied to the sprite memory 52 as the address "FA" from the sprite DMA controller 50.

Also, the sprite generator 54 includes a register (not shown in the figure) which is accessible from the CPU 1 and used to store the format "TO [2: O]" of the address information of the sprites. The format "TO" of the address information is the information indicative of the addressing mode for use in fetching the character pattern data of a sprite. The sprite generator 54 outputs the format "TO" of the address information to the first picture parameter mixer 58 as well as the above sprite parameters .

Incidentally, two handshake signals, i.e., a signal "VALID" and a signal "WISH" are used when data is transmitted from one stage to the subsequent stage. The signal "VALID" is transmitted from a data outputting unit to a data receiving unit and activated when data to be transmitted is valid. On the other hand, the signal "WISH" is transmitted from a data receiving unit to a data outputting unit and activated when the data receiving unit is ready to receive data. One set data is transmitted during the period (one clock) when both the signals "VALID" and "WISH" are activated.

The first background generator 56 is provided with registers (only the FSC register 57 is illustrated in the figure) which are accessible by the CPU 1 through the first bus 31. Some of the registers stores pointers "Ll", "Hl" and "Ul" pointing to arrays in the main memory 17 storing information of the first background screen. The other registers store the information to be applied to the first background screen including the number of bits per pixel "Bl [2: O]", size information "Sl [1:0]", flip information "Fl[l:0]", horizontal position information "TXl[7:0]^π, vertical position information "TY1[7:O]", a depth value "Zl [3:0] ", palette information "Pl[3:0]^τ\ the format "Tl [2:0]" of the address information and the location "Wl" of the attribute information. The arrays in the main memory 17 pointed to by the read pointers "Ll" and "Hl" are used to store address information "Al" pointing to the location of the character pattern data in the memory MEM used for the first background screen. The array in the main memory 17 pointed to by the read pointer "Ul" stores two attribute information items, i.e., the palette information "Pl" and the depth value "Zl". The data size (1 to 3 bytes) of this address information "Al" is determined in accordance with the format "Tl" of the address information while this attribute information is made valid when the location "Wl" of the attribute information designates the array. In this case, the number of bits "Bl", the size information "Sl", the flip information "Fl", the depth value "Zl", palette information "Pl" and the format "τi" of the address information are associated with the character forming the first background screen, but correspond respectively to the number of bits "BO", the size information "SO", the flip information "FO", the depth value "ZO", palette information "PO", and the format "TO" of the address information of the character forming the above sprite.

Fig. 8 is a view which shows the structures of the FSC registers 57 and 61 of Fig. 5. As shown in Fig. 8, the FSC resister 57 is mapped to the address space of the first bus 31, and serves to store the flip information "Fl", the size information "Sl", and the number of bits "Bl" (a color mode) .

However, as described above, while the flip information "Fl" functions as inversion information in the compatible display mode, the flip information "Fl" functions in the extended display mode to provide a switch bit between the standard resolution mode and the double resolution mode and a selection bit for designating either left or right pixel in the double resolution mode.

Returning to Fig. 5, the first background generator 56 reads the information (that is, the array elements, or more specifically described, the address information "Al", the depth value "Zl" (depending on "Wl") and the palette information "Pl" (depending on "Wl") of the character) of the character (overlapping (or coming to overlap) the pixel buffers 78L and 78R) located in the area where the image displaying process is performed, through the first bus 31 from the main memory 17 in accordance with the horizontal scan count signal "HP" and the vertical scan count signal "VP", and outputs them to the first picture parameter mixer 58, while the first background generator 56 also outputs the other information of the character (the number of bits "Bl", the size information "Sl", the flip information "Fl", the horizontal position ^"information "Xl", the vertical position information "Yl", the depth value "Zl" (depending on "Wl"), the palette information "Pl" (depending on "Wl"), the format "Tl" of the address information) to the first picture parameter mixer 58. However, the location "Wl" of the attribute information is not used in the subsequent stages and therefore not transmitted.

In this case, if the location "Wl" of the attribute information is "0", the depth value "Zl" and the palette information "Pl" are output from the registers of the first background generator 56, and if the location "Wl" of the attribute information is "1", the depth value "Zl" and the palette information "Pl" are read and output from the main memory 17. Also, with regards to the horizontal position information "Xl" and the vertical position information "Yl", the horizontal position information "Xl [8: O]" and the vertical position information "Yl [4: O]" of each character are calculated on the basis of the horizontal position information "TXl" and vertical position information "TYl" of the entire first background screen, and output to the first picture parameter mixer 58.

In addition, the first background generator 56 outputs the signal "VALID" and an emergency signal "E" to the first picture parameter mixer 58, and receives the signal "WISH" from the first picture parameter mixer 58. The emergency signal "E" is the signal which demands reception of data by the subsequent stage, and is activated when the data as output is not transferred to the subsequent stage for a certain time.

Specifically speaking, when the position information of the output data (the horizontal position information "Xl" and the vertical position information "Yl") is substantially delayed from the position information indicated by the horizontal scan count signal "HP" and the vertical scan count signal "VP", the first background generator 56 detects a wide positional difference therebetween and activates the emergency signal "E".

The first picture parameter mixer 58 outputs to the second picture parameter mixer 62 signals "T2", "B2", "S2", "F2", "X2", "Y2", "Z2", "P2" and "A2" by selecting and unifying the signals "TO", "BO", "SO", "FO", "XO", "YO", "ZO", "PO" and "AO" for defining the sprite as output from the sprite generator 54 and the signals "Tl", "Bl", "Sl", "Fl", "Xl", "Yl", "Zl", "Pl" and "Al" for defining the first background screen as output from the first background generator 56 in accordance with the following rules.

In this case, the first picture parameter mixer 58 preferentially selects the signals "TO", "BO", "SO", "FO", "XO", "YO", "ZO", "PO" and "AO" for defining the sprite unless otherwise required as specified below. Namely, the first picture parameter mixer 58 selects the signals "Tl", "Bl", "Sl", "Fl", "Xl", "Yl", "Zl", "Pl" and "Al" for defining the first background screen when the emergency- signal "E" is activated. Needless to say, even if the emergency signal "E" is not activated, the signals "Tl", "Bl", "Sl", "Fl", "Xl", "Yl", "Zl", "Pl" and "Al" for defining the first background screen is selected when the signals "TO", "BO", "SO", "FO", "XO", "YO", "ZO", "PO" and "AO" for defining the sprite are not input.

Also, the first picture parameter mixer 58 outputs the signal "VALID" to the second picture parameter mixer 62 while the signal "WISH" is input from the second picture parameter mixer 62 to the first picture parameter mixer 58.

The second background generator 60 is provided with registers (only the FSC register 61 is illustrated in the figure) which are accessible by the CPU 1 through the first bus 31. Some of the registers store pointers "L2", "H2" and "U2" pointing to arrays in the main memory 17 in which the information "^'of the second background screen is stored. The other registers also store the information to be applied to the second background screen, i.e., the number of bits per pixel "B3[2:0]^TI, size information "S3 [1:0]", flip information "F3[l:0]", horizontal position information "TX3[7:0]", vertical position information "TY3[7:0]", a depth value "Z3[3:0]", palette information "P3[3:0]^π, the format "T3[2:0]" of the address information and the location "W3" of the attribute information.

The arrays in the main memory 17 pointed to by the read pointers "L2" and "H2" store address information "A3" pointing to the location of the character pattern data in the memory MEM used for the second background screen. The array in the main memory 17 pointed to by the read pointer "U2" stores two attribute information items, i.e., the palette information "P3" and the depth value "Z3". The data size (1 to 3 bytes) of this address information "A3" is determined in accordance with the format "T3" of the address information while this attribute information is made valid when the location "W3" of the attribute information designates the array.

In this case, the number of bits "B3", the size information "S3", the flip information "F3", the depth value "Z3", the palette information "P3", and the format "T3" of the address information are associated with the character forming the second background screen, but correspond respectively to the number of bits "Bl", the size information "Sl", the flip information "Fl", the depth value "Zl", palette information "Pl", and the format "τl" of the address information of the character forming the first background screen.

Referring to Fig. 8, the FSC register 61 is mapped in the address space of the first bus 31, and used to store the flip information F3, the size information S3, and the number of bits "B3" (color mode) . However, as described above, while the flip information functions as inversion information in the compatible display mode, the flip information F3 functions in the extended display mode to provide a switch bit between the standard resolution mode and the double resolution mode and a selection bit for designating either left or right pixel in the double resolution mode.

Returning to Fig. 5, the second background generator 60 reads the information (that is, the array elements, or more specifically described, the address information "A3", the depth value "Z3" (depending on "W3") and the palette information "P3" (depending on "W3") of the character) of the character (overlapping (or coming to overlap) the pixel buffers 78L and 78R) located in the area where the image displaying process is performed, through the first bus 31 from the main memory 17 in accordance with the horizontal scan count signal "HP" and the vertical scan count signal "VP", and outputs them to the second picture parameter mixer 62, while the second background generator 60 also outputs the other information of the character (the number of bits "B3", the size information "S3", the flip information "F3", the horizontal position information "X3", the vertical position information "Y3", the depth value "Z3" (depending on "W3"), the palette information "P3" (depending on "W3") , the format "T3" of the address information) to the second picture parameter mixer 62. However, the location "W3" of the attribute information is not used in the subsequent stages and therefore not transmitted.

In this case, if the location "W3" of the attribute information is "0", the depth value "Z3" and the palette information "P3" are output from the registers of the second background generator 60, and if the location "W3" of the attribute information is "1", the depth value "Z3" and the palette information "P3" are read and output from the main memory 17. Also, with regards to the horizontal position information "X3" and the vertical position information "Y3", the horizontal position information "X3[8:0]" and the vertical position information "Y3[4:0j" of each character are calculated on the basis of the horizontal position information "TX3" and the vertical position information "TY3" of the entire second background screen, and output to the second picture parameter mixer 62.

In addition, the second background generator 60 outputs the signal "VALID" and the emergency signal "E" to the second picture parameter mixer 62, and receives the signal "WISH" from the second picture parameter mixer 62. The second picture parameter mixer 62 outputs to the address generator 64 signals "Ts", "Bs", "Ss", "Fs", "Xs", "Ys", "Zs", "Ps" and "As" by selecting and unifying the signals "T2", "B2", "S2", "F2", "X2", "Y2", "Z2", "P2" and "A2" for defining the sprite and/or the first background screen as output from the first picture parameter mixer 58 and the signals "T3", "B3", "S3", "F3", "X3", "Y3", "Z3", "P3" and "A3" for defining the second background screen as output from the second background generator 60 in accordance with the following rules .

In this case, the second picture parameter mixer 62 preferentially selects the signals "T2", "B2", "S2", "F2", "X2", "Y2", .¹ _Z2" "p2" and "A2" as output from the first picture parameter mixer 58 unless otherwise required as specified below. Namely, the second picture parameter mixer 62 selects the signals "T3", "B3", "S3", "F3", "X3", "Y3", "Z3", "P3" and "A3" for defining the second background screen when the emergency signal "E" is activated. Needless to say, even if the emergency signal "E" is not activated, the signals "T3", "B3", "S3", "F3", "X3", "Y3", "Z3", "P3" and "A3" for defining the second background screen is selected when the signals "T2", "B2", "S2", "F2", "X2", "Y2", "Z2", "P2" and "A2" are not input from the first picture parameter mixer 58.

Also, the second picture parameter mixer 62 outputs the signal "VALID" to the address generator 64 while the signal "WISH" is input from the address generator 64.

The address generator 64 is a circuit for converting address information "As" into a real address "Ar" of 27 bits in accordance with the format "Ts" of the address information output from the second picture parameter mixer 62. The address generator 64 is provided with 16 segment registers (not shown in the figure) each of which consists of 16 bits and is accessible by the CPU 1 and used to store a base address or a segment address for use in converting the address information "As".

In accordance with the present embodiment, there are eight types of the addressing modes indicated by the format "Ts" of the address information. Namely, there are an 8-bit character number mode, a 16- bit character number mode, a 16-bit aligned address pointer mode, a 16-bit address pointer mode, a 24-bit address pointer mode, a 16-bit extended character number mode, a 16-bit extended address pointer mode and a 24-bit aligned address pointer mode.

The 8-bit character number mode is used to select a character by an 8-bit number "As". The 16-bit character number mode is used to select a character by a 16-bit number "As". In these modes, on the basis of the base address (256-byte alignment) stored in the address "0" of the segment register and zero-extended to 27 bits, a real address "Ar" is calculated from the size of one character corresponding to the number of bits "Bs" and the size information "Ss" output from the second picture parameter mixer 62.

Specifically speaking, a real address "Ar" is calculated as (base address) + (the character number indicated by the address information "As") x (the number of bits per pixel indicated by the number "Bs") x (the number of pixels per character indicated by the size information "Ss") /8. Incidentally, the division by "8" is performed because the real address "Ar" is a byte address.

In the 16-bit aligned address pointer mode, a character is selected by a 16-bit address pointer "As" with alignment. More specifically speaking, a 27-bit real address "Ar" is generated by- adding the lower 13 bits of the 16-bit address pointer "As", which is zero-extended to a 16-bit address with low-order 3 bits of "0", to the segment address (256-byte alignment) , which is stored in the segment register pointed to by the upper 3 bits of the 16-bit aligned address pointer "As" and zero-extended to a 27-bit address.

In the 16-bit address pointer mode, a character is selected by a 16-bit address pointer "As". More specifically speaking, a 27-bit real address "Ar" is generated by adding the lower 12 bits of the 16-bit address pointer "As" to the segment address (256-byte alignment) which is stored in the segment register pointed to by the upper 4 bits of the 16-bit address pointer "As" and zero-extended to a 27-bit address.

In the 24-bit address pointer mode, a character is selected by a 24-bit address pointer "As". More specifically speaking, the 24-bit address pointer "As" is zero-extended to 27 bits which can be used as a 27-bit real address "Ar".

The 16-bit extended character number mode is an extended mode of the 16-bit character number mode. In this mode, on the basis of the 27-bit base address (2K-byte alignment) stored in the address "0" of the segment register, a real address "Ar" is calculated from the size of one character corresponding to the number of bits "Bs" and the size information "Ss" output from the second picture parameter mixer 62. The actual calculation is performed in the same manner as in the 16- bit character number mode.

The 16-bit extended address pointer mode is an extended mode of the 16-bit address pointer mode. More specifically speaking, a real address "Ar" is generated as the sum of the 27-bit base address (2K- byte alignment) stored in the segment register pointed to by the upper 4 bits of the 16-bit address pointer "As", and the lower 12 bits of the 16-bit address pointer "As". In the 24-bit aligned address pointer mode, a 27-bit real address "Ar" is generated by concatenating three zeros as the lower three bits to the 24-bit address pointer "As" as the upper 24 bits of the 27-bit real address (8 byte alignment) .

As has been discussed above, the address generator 64 converts the address information "As" into a real address "Ar" (referred to herein as the address information "Ar"), and outputs the address information "Ar" to the strip generator 66 together with the other signal "Bs", "Ss", "Fs", "Xs", "Ys", "Zs" and "Ps". However, the format "Ts" of the address information is not used in the subsequent stages and therefore not transmitted.

On the other hand, the address generator 64 supplies the signal "VALID" to the strip generator 66 while the signal "WISH" is input from the strip generator 66 to the address generator 64.

The strip generator 66 selects the character (overlapping (or coming to overlap) the pixel buffers 78L and 78R) located in the area where the image displaying process is performed in accordance with the horizontal scan count signal "HP" and the vertical scan count signal "VP" .

Then, the strip generator 66 extracts a one-dimensional array (referred to also as a strip) forming a horizontal line to be drawn from the character pattern data (a two-dimensional array) as selected. For example, if a character consists of 16 pixels x 16 pixels, a strip consists of a horizontal line of 16 pixels.

In what follows, more specific explanation is given separately in the case where the display mode control information "CHRMODE" is "0" to select the compatible display mode and in the case where the display mode control information "CHRMODE" is "1" to select the extended display mode.

In the compatible display mode, the strip generator 66 determines a strip to be extracted on the basis of the vertical position information "Ys", the flip information Fs[I] indicative of inversion in the vertical direction, and the vertical scan count signal "VP". Since the flip information Fs[I] is taken into consideration in the compatible display mode, if Fs[I] = 1 (indicative of inversion in the vertical direction) , a strip is determined on the basis of the values obtained by inverting the vertical coordinate "Ys" of the character as input in the vertical direction (inversion in the high and low direction) .

Then, the strip generator 66 calculates the address information (start address) "Asp" of the strip as determined on the basis of the address information (head address) "As" of character pattern data, the number of bits per pixel "Bs", and the horizontal size corresponding to the size information "Ss" of the character. This is the extraction of a strip. The extraction of a strip in this case is therefore not the extraction of color codes of the strip as determined from the character pattern data.

The strip generator 66 outputs the calculated address information "Asp" to the character fetcher 68 together with the other signal "Bs", "Ss", Fs [1:0], "Xs", "Zs" and "Ps". However, the vertical position information "Ys" are not used in the subsequent stages and therefore not transmitted.

In addition, the strip generator 66 outputs the signal "VALID" to the character fetcher 68 while the signal "WISH" is input from the character fetcher 68 to the strip generator 66. On the other hand, when a strip is determined in the extended display mode, the flip information Fs[I] is ignored (not taken into consideration) . This is because, in this case, the flip information Fs[I] functions as the switch bit between the standard resolution mode and the double resolution mode. Other points are the same as in the compatible display mode.

The character fetcher 68 converts a character, which is transmitted as the address information "Asp", into color codes. More specifically speaking, the character fetcher 68 reads in bytes data "D" (that is, color codes of the respective pixels forming a strip) corresponding to the amount of the data as calculated from the number of bits per pixel "Bs" and the horizontal size indicated by the size information "Ss" from the location of the memory MEM pointed to by the address information "Asp", and sequentially outputs the data "D" to the pixel generator 70 on a byte-by-byte basis in little endian order. In the following explanation, the data "D" is referred to as the strip pattern data "D". ^{' ' ''"'}

The character fetcher 68 also outputs other signal "Bs", "Ss", Fs[IrO], "Xs", "Zs" and "Ps" to the pixel generator 70 together with the strip pattern data "D". In addition, the character fetcher 68 outputs the signal "VALID" to the pixel generator 70 while the signal "WISH" is input from the pixel generator 70 to the character fetcher 68.

The pixel generator 70 arranges byte data (part or all of the strip pattern data '¹D") , as sequentially received, in little endian order, and extracts data (the color code of one pixel) of the number of bits per pixel (M bits per pixel: M = 1 to 8) indicated by the "Bs" from the lower bits of the strip pattern data "D". Then, the pixel generator 70 generates an 8-bit color code "C" by combining the color code of one pixel as extracted with the palette information "Ps". This combination is performed by the following process. Namely, the palette information "Ps" is used as the upper 4 bits of the 8-bit color code,

■ and then the color code of one pixel as extracted is used as the lower

"M" bits. The remaining bits are filled with "0". If the number of bits "M" is greater than or equal to 5, the lower bit(s) of the palette information "Ps" is overwritten by the color code of one pixel as extracted.

As has been discussed above, the pixel generator 70 generates a color code "C" for each pixel (referred to hereinbelow as a pixel color code "C") on the basis of the strip pattern data "D" given in bytes .

Also, the pixel generator 70 calculates horizontal position information "Xp" for each pixel on the basis of the horizontal position information "Xs" of a character.

In this case, in the compatible display mode, the flip information Fs[O] is referred to, and if Fs[O] = 1 indicative of the inversion in the horizontal direction, the horizontal position information "Xp" for each pixel is calculated by decrement from the position advanced by the horizontal size indicated by the size information "Ss" in the reverse direction. Namely, the horizontal position information "Xp" is obtained so that the character is inverted in the horizontal direction (displayed after left-right inversion) .

On the other hand, in the extended display mode, the flip information Fs[O] is ignored (not taken into consideration) when the horizontal positional information Xp is obtained. This is because, in the extended display mode, the flip information Fs[O] functions to provide a selection bit for designating either left or right pixel in the double resolution mode.

The pixel generator 70 outputs the pixel color code "C" and the horizontal position information "Xp", obtained as described above, to the transparency controller 72 together with the depth value "Zs" and the flip information Fs[IrO]. In this case, the flip information Fs[I] is output as the switch bit "Cmb", and the flip information Fs[O] is output as the selection bit "Ofs". However, the number of bits "Bs", the size information "Ss" and the palette information "Ps" are not used in the subsequent stages and therefore not transmitted. Also, the pixel generator 70 outputs the signal "VALID" to the transparency controller 72 while the signal "WISH" is input from the transparency controller 72 to the pixel generator 70. The transparency controller 72 is provided with a transparency control memory (not shown in the figure) consisting of 16 entries each of which consists of 5 bits which can be indirectly accessed by the CPU 1. The character color palette 84 to be described below is composed of a local memory which includes 256 entries each of which consists of 16 bits, which can be grouped into 16 blocks each of which is 16 entries so that a maximum of one transparent color can be provided for each block. Each entry of the transparency control memory is associated with the corresponding block of the character color palette 84. When the CPU 1 writes color data to an entry of the character color palette 84 and if the color data indicates a transparent color, the entry of the transparency control memory corresponding to the block including the entry is used to store a 4- bit value indicative of which entry in the block saves the transparent color and set a one-bit value (referred to herein as a transparency valid bit) to "1" indicative of the transparency. In this case, if the transparent color in the entry of the character color palette 84 is overwritten by a non-transparent color, the corresponding transparency valid bit is cleared to "0" such that the entry is associated with the non-transparent color. The transparency- controller 72 accesses the transparency control memory by the upper 4 bits of the pixel color code "C" input from the pixel generator 70 (i.e., the palette information "Ps"), and if the transparency valid bit of the accessed entry is "1" and if the remaining 4 bits of the accessed entry matches the lower 4 bits of the pixel color code "C", then the transparency controller 72 judges that the pixel is transparent.

The transparency controller 72 outputs to the draw driver 74 the information (i.e., the horizontal position information "Xp", the depth value "Zs", the pixel color code "C", the switch bit "Cmb" and the selection bit "Ofs") of a pixel which is judged non-transparent, and does not output but does discard here the information of a pixel which is judged transparent. In addition, the transparency controller 72 outputs the signal "VALID" to the draw driver 74, while the signal "WISH" is input from the draw driver 74 to the transparency controller 72.

The draw driver 74 judges whether or not the pixel of which the display position is indicated by the horizontal position information "Xp" overlaps the pixel buffers 78L and 78R on the basis of the horizontal position information "Xp" and the horizontal scan count signal "HP". And if the pixel overlaps the pixel buffers 78L and 78R, the ^'draw driver 74 instructs the pixel buffer controller 76 to write the depth value "Zs" and the pixel color code "C" of the pixel to the pixel buffers 78L and/or 78R (i.e., by issuing a request for drawing). Since the horizontal scan count signal "HP" may be incremented by one after issuing a request for drawing and before accepting the request for drawing, the draw driver 74 makes the judgment in the area of the pixel buffers 78L and 78R narrowed by one pixel.

More specifically speaking, in the case where it is judged that the pixel overlaps the pixel buffers 78L and 78R, when the display mode control information "CHRMODE" input from the display mode control register 101 is "1" (that is, indicative of the extended display mode) and the switch bit "Cmb" is "1" (that is, indicative of the double resolution mode) , the draw driver 74 asserts a signal "REQO" which is used to request the operation of writing pixel data to the pixel buffer 78L if the selection bit "Ofs" is "0", or asserts a signal "REQl" which is used to request the operation of writing pixel data to the pixel buffer 78R if the selection bit "Ofs" is "1".

Then, the horizontal position information "Xp", the depth value "Zs" and the pixel color code "C" are output to the pixel buffer controller 76 when the signal "WISH" is input from the pixel buffer controller 76.

On the other hand, when at least one of the display mode control information "CHRMODE" and the switch bit "Cmb" is "0", i.e., when it is in the compatible display mode or when even in the extended display mode it is in the standard resolution mode, both the signals "REQO" and "REQl" are asserted in order to request the operation of writing same pixel data to the corresponding positions of both the pixel buffers 78L and 78R.

And, the horizontal position information "Xp", the depth value "Zs" and the pixel color code "C" are output to the pixel buffer controller 76 when the signal "WISH" is input from the pixel buffer controller 76.

The pixel buffer controller 76 performs arbitration between a request issued by the draw driver 74 for writing (drawing) data to the pixel buffers 78L and/or 78R, and a request for reading issued by the view driver 80. In this case, the request for reading issued by the view driver 80 is given priority. As a result of arbitration, the pixel buffer controller 76 performs the required process as accepted. In this case, the pixel buffer controller 76 accesses the pixel buffers 78L and 78R, and reads read data "BOO" and "BOl" from the location pointed to by a read address "BRA" or writes write data "BIO" and "BIl" to the location pointed to by a write address "BWA". The details of each request (writing or reading) are as follows.

When only the signal "REQO" is asserted and the write request from the draw driver 74 is accepted, the pixel buffer controller 76 compares the depth value "Zs" input from the draw driver 74 with the depth value "ZpbO" included in the read data "BOO" (the depth value "ZpbO" and the pixel color code "CpbO") as read from the pixel buffer 78L. Then, in accordance with the result of comparison, the pixel buffer controller 76 determines the data "BIO" to be written to the pixel buffer 78L, i.e., determines which is to be written, the data "BOO" as read (the depth value "ZpbO" and the pixel color code "CpbO") or the data as input (the depth value "Zs" and the pixel color code "C") . In this case, the data containing the larger depth value is written to the pixel buffer 78L as the write data "BIO". Incidentally, the read address "BRA" and write address "BWA" to be input to the pixel buffer 78L are generated on the basis of the horizontal position information "Xp". When only the signal "REQl" is asserted and the write request from the draw driver 74 is accepted, the similar process is performed for the pixel buffer 78R in place of the pixel buffer 78L. Likewise, when both the signals "REQO" and "REQl" are asserted and the write request from the draw driver 74 is accepted, the similar process is performed for both the pixel buffers 78L and 78R rather than for one of the pixel buffers 78L and 78R.

On the other hand, when the signal "REQ" is asserted and the read request from the view driver 80 is accepted, the pixel buffer controller 76 outputs, to the view driver 80, the read data "BOO" (the depth value "ZpbO" and the pixel color code "CpbO") as read from the pixel buffer 78L and the read data "BOl" (the depth value "Zpbl" and the pixel color code "Cpbl") as read from the pixel buffer 78R.

Incidentally, after the read data BOO and BOl is output to the view driver 80, the corresponding locations of the pixel buffers 78L and 78R are cleared by writing data which is fixed to "0" (corresponding to the depth value indicative of the deepest position and the color code indicative of "0") . Also, the read address "BRA" and write address "BWA" to be input to the pixel buffers 78L and 78R are the address information "Xa" which is input from the view driver 80. The pixel buffer 78L comprises a depth buffer and a code buffer

(not shown in the figure) . The depth buffer is composed of 128 entries each of which is provided for each pixel and consists of 4 bits per pixel. The code buffer is composed of 128 entries each of which is provided for each pixel and consists of 8 bits per pixel. In this description, the entry for one pixel of the pixel buffer 78L is referred to as a pixel buffer unit (consisting of 4 bits for the depth value "ZpbO" and 8 bits for the pixel color code "CpbO", totaling to

12 bits) . The pixel buffer 78L sequentially stores the depth value "ZpbO" and the pixel color code "CpbO" for each pixel in order that the tail location of the pixel buffer 78L is the location of the pixel buffer unit corresponding to the scan position (i.e., the read position of the view driver 80) , and the top location of the pixel buffer 78L is the location of the pixel buffer unit corresponding to the position as advanced from the scan position by the capacity of the pixel buffer 78L. When the scan position is shifted, the pixel buffer unit at the tail is then used as the pixel buffer unit at the top in order to cyclically use the pixel buffer units . The structure and operation of the pixel buffer 78R are the same as those of the pixel buffer 78L and therefore no redundant description is repeated.

The view driver ^' 80 issues a request to the pixel buffer controller 76 for reading data from the pixel buffers 78L and 78R on the basis of the horizontal scan count signal "HP". This read request is issued by outputting, to- the pixel buffer^" controller 76, the address information "Xa" generated on the basis of the horizontal scan count signal "HP" together with the signal "REQ". The read request from the view driver 80 is given priority by the pixel buffer controller 76 so that there is no wait signal for the read request.

In addition, the view driver 80 outputs the depth values "ZpbO" and "Zpbl" and the pixel color codes "CpbO" and "Cpbl" as read to the color palette controller 82 respectively as a depth value "Zpb" and a pixel color code "Cpb". In other words, the view driver 80 outputs the depth value "ZpbO" and the pixel color code "CpbO" as read to the subsequent stage as the left hand pixel data of the pixel set, and outputs the depth value "Zpbl" and the pixel color code "Cpbl" to the subsequent stage as the right hand pixel data of the pixel set.

By the way, next is an explanation of the operation of the pixel buffer controller 76 with reference to a time chart. Fig. 9 is a time chart for explaining the operation of the pixel buffer controller 76 of Fig. 6. Incidentally, the logic is described in positive logic. Furthermore, explained herein is the operation in the extended display mode. At first, the write operation to the pixel buffers 78L and 78R will be explained. With reference to Fig. 9, when the signal "REQ" is negated while the signal "REQO" is asserted, the pixel buffer controller 76 starts the compare/write operation for the pixel buffer 78L. In this case, the condition that REQ = 0 is required because the read operation from the pixel buffers 78L and 78R for displaying images is given priority over the write operation.

The cycle in which the signal "REQO" is asserted while the signal "REQ" is negated is herein referred to as a compare/write operation start cycle. The pixel buffer controller 76 performs the read operation from the read address BRA[6:0] of the pixel buffer 78L (equivalent to the horizontal coordinate "Xp" of the compare/write operation start cycle) in the cycle next to the compare/write operation start cycle. The bits [11:8] of the data BOO [11:0] as read are the depth value of a pixel which has already been written to the pixel buffer 78L.

The pixel buffer controller 76 compares this depth value BO0[ll:8] and the depth value Zs[3:0] of the pixel to be drawn (i.e., the depth value Zs of the compare/write operation start cycle) , and if Zs ≥ BOO [11: 8], the pixel buffer controller 76 writes, in the cycle next to the cycle in which the data BOO [11:0] is read, the pixel data { Zs [3:0], C[7:0]} of the compare/write operation start cycle to the write address BWA[6:0] of the pixel buffer 78L (= the read address BA[6:0] in the cycle in which the data BOO [11:0] is read) as the write data BIO[HrO] . On the other hand, if Zs < BOO [11: 8] as a result of the comparison, the pixel buffer controller 76 writes, in the cycle next to the cycle in which the data BOO [11:0] is read, the data BOO[HrO] as read to the write address BWA[6:0] of the pixel buffer 78L (= the read address BA[6:0] in the cycle in which the data BOO [11:0] is read) as the write data BIO [11:0] as it is. Namely, in this case, there is no change in the data of the pixel buffer 78L.

The pixel buffer controller 76 performs the same compare/write operation also for the pixel buffer 78R.

The above process will be more specifically explained with reference to Fig. 9. When the signal "REQ" is negated while the signal "REQO" is asserted in the cycle T3, the pixel buffer controller 76 starts the compare/write operation of pixel data to the pixel buffer 78L.

The pixel buffer controller 76 performs the read operation from the read address "BRA" ( = 15H) of the pixel buffer 78L (equivalent to the horizontal coordinate "Xp" of the compare/write operation start cycle T3) in the cycle T4 next to the compare/write operation start cycle T3. The bits [11:8] ( = 2H) of the data BOO[HrO] ( = 235H) as read are the depth value of a pixel which has already been written to the pixel buffer 78L.

The pixel buffer controller 76 compares this depth value BOO [11: 8] ( = 2H) and the depth value Zs [3:0] ( = 5H) of the pixel to be drawn (i.e., the depth value Zs of the compare/write operation start cycle T3) . Since Zs > BOO [11: 8], the pixel buffer controller 76 writes, in the cycle T5 next to the cycle T4 in which the data BO0[ll:0] is read, the pixel data {Zs[3:0], C[7:0]} ( = {5H, 05H}) of the compare/write operation start cycle T3 to the write address BWA[6:0] ( = 15H) of the pixel buffer 78L (= the read address BRA[6:0] in the cycle T4 in which the data BOO[HrO] is read) as the write data BIO[HrO] ( = 505H) .

On the other hand, when the signal "REQ" is negated while the signal "REQl" is asserted in the cycle T3, the pixel buffer controller 76 starts the compare/write operation of pixel data to the pixel buffer 78R. The pixel buffer controller 76 performs the read operation from the read address "BRA" ( = 15H) of the pixel buffer 78R (equivalent to the horizontal coordinate "Xp" of the compare/write operation start cycle T3) in the cycle T4 next to the compare/write operation start cycle T3. The bits [11:8] ( = 2H) of the data BOl[HrO] ( = 236H) as read are the depth value of a pixel which has already been written to the pixel buffer 78R.

The pixel buffer controller 76 compares this depth value BOl [11: 8] ( = 2H) and the depth value Zs [3:0] ( = 5H) of the pixel to be drawn (i.e., the depth value Zs of the compare/write operation start cycle T3) . Since Zs ≥ B01[H:8], the pixel buffer controller 76 writes, in the cycle T5 next to the cycle T4 in which the data BOl[H:0] is read, the pixel data {Zs[3:0], C[7:0]} ( = {5H, 05H}) of the compare/write operation start cycle T3 to the write address BWA[6:0] ( = 15H) of the pixel buffer 78R (= the read address BRA[6:0] in the cycle T4 in which the data BOl[HrO] is read) as the write data BIl[HrO] ( = 505H) .

When the signal "REQO" is asserted while the signal "REQ" is negated in the cycle T6, the pixel buffer controller 76 starts the compare/write operation of pixel data to the pixel buffer 78L. The pixel buffer controller 76 performs the read operation from the read address "BRA" ( = 17H) of the pixel buffer 78L (equivalent to the horizontal coordinate "Xp" of the compare/write operation start cycle T6) in the cycle T7 next to the compare/write operation start cycle T6. The bits [11:8] ( = DH) of the data BOO [11:0] ( = DlOH) as read are the depth value of a pixel which has already been written to the pixel buffer 78L.

The pixel buffer controller 76 compares this depth value BOO [11: 8] ( = DH) and the depth value Zs [3:0] ( = 5H) of the pixel to be drawn (i.e., the depth value Zs of the compare/write operation start cycle T6) . Since Zs < BO0[ll:8], the pixel buffer controller 76 writes, in the cycle T8 next to the cycle T7 in which the data BOO [11:0] is read, the data BOO [11:0] ( = DlOH) as read to the write address BWA[6:0] ( = 17H) of the pixel buffer 78L (= the read address BRA[6:0] in the cycle T7 in which the data BOO[H = O] is read) as the write data BIO [11:0] as it is.

On the other hand, when the signal "REQl" is asserted while the signal "REQ" is negated in the cycle T6, the pixel buffer controller 76 starts the compare/write operation of pixel data to the pixel buffer 78R. The pixel buffer controller 76 performs the read operation from the read address "BRA" ( = 17H) of the pixel buffer 78R (equivalent to the horizontal coordinate "Xp" of the compare/write operation start cycle T6) in the cycle T7 next to the compare/write operation start cycle T6. The bits [11:8] ( = DH) of the data BOl[ll:0] ( = DHH) as read are the depth value of a pixel which has already been written to the pixel buffer 78R.

The pixel buffer controller 76 compares this depth value BOl [11:8] ( = DH) and the depth value Zs [3:0] ( = 5H) of the pixel to be drawn (i.e., the depth value Zs of the compare/write operation start cycle T6) . Since Zs < BO1[11:8], the pixel buffer controller 76 writes, in the cycle T8 next to the cycle T7 in which the data BOl [11:0] is read, the data BOl [11:0] ( = DHH) as read to the write address BWA[6:0] ( = 17H) of the pixel buffer 78R (= the read address BRA[6:0] in the cycle T7 in which the data BOl[HrO] is read) as the write data BIl[HrO] as it is. Thereafter, the compare/write operation is repeated as has been discussed above.

Meanwhile, it is noted that in the cycles TO to T8 the signal "REQO" and the signal "REQl" are asserted in the same timing. This is because in the case where the display mode control information "CHRMODE" = 1 (i.e., in the extended display mode), both the signal "REQO" and the signal "REQl" are asserted when the pixel having the switch bit "Crttb" equal to "0" (i.e., indicative of the standard resolution mode) is input to the draw driver 74. On the other hand, in the cycles T12 to Tl 6, only the signal "REQO" is asserted. This is because in the case where the display mode control information "CHRMODE" = 1 (i.e., in the extended display mode), when the pixel having the switch bit "Cmb" equal to "1" (i.e., indicative of the double resolution mode) is input to the draw driver 74, either one of the signal "REQO" and the signal "REQl" is asserted in accordance with the value of the select bit "Ofs".

Next, the read operation from the pixel buffers 78L and 78R will be explained. Referring to Fig. 9, when the signal "REQ" is asserted, the operation of reading pixel data for displaying images is started. The reading is performed always from both the pixel buffer 78L and the pixel buffer 78R. In this case, the cycle in which the signal "REQ" is asserted is referred to as the reading operation start cycle.

The pixel buffer controller 76 reads the data BOO[IIrO] and

BOl [11:0] respectively from the read address BRA[6:0] of the pixel buffers 78L and 78R (equivalent to the horizontal coordinate "Xa" of the reading operation start cycle) in the cycle next to the reading operation start cycle.

Then, the pixel buffer controller 76 outputs, in the cycle next to the read cycle, the read data BOO[IIcO] and BOl[IIcO], i.e., the data BOO [11: 8] as the depth value ZpbO[3:O], the data BOO [7:0] as the pixel color code CpbO[7cO], the data BOl [11: 8] as the depth value

■ Zpbl[3cO] and the data BOl [7 cO] as the pixel color code Cpbl[7cO], respectively to the view driver 80.

The data which is read from the read address BRA[6cO] of the pixel buffers 78L and 78R for displaying images in the cycle next to the reading operation start cycle is initialized by writing write data BIO ( = BIl = 000H) , in the further next cycle, to the write address BWA of the pixel buffers 78L and 78R ( = the read address BRA in the cycle in which the data BOO and BOl is read) . Referring to Fig. 9, the above process will be more specifically explained. When the signal "REQ" is asserted in the cycle T2, the operation of reading pixel data for displaying images is started. The read operation is performed always from both the pixel buffer 78L and the pixel buffer 78R. The pixel buffer controller 76 reads the data BOO[IIrO] ( = 475H) and BOl[IIrO] ( = 475H) respectively from the read address BRA[6:0] (= 05H) of the pixel buffers 78L and 78R ( equivalent to the horizontal coordinate "Xa" of the reading operation start cycle T2) in the cycle T3 next to the reading operation start cycle T2. Then, the pixel buffer controller 76 outputs, in the further next cycle T4, the read data BOO[HrO] ( = 475H) and BOl[HrO] ( = 475H), i.e., the data BOO [11: 8] ( = 4H) as the depth value ZpbO[3rO], the data BOO [7:0] ( = 75H) as the pixel color code CpbO[7rO], the data BOl [Hr 8] ( = 4H) as the depth value Zpbl[3:0] and the data BOl [7:0] ( = 75H) as the pixel color code Cpbl[7:0], respectively to the view driver 80.

The data BOO ( = 475H) and BOl ( = 475H) which is read from the read address BRA ( = 05H) of the pixel buffers 78L and 78R for displaying images in the cycle T3 next to the reading operation start cycle T2 is initialized in the further next cycle T4 by writing write data BIO ( = BIl = 000H) to the write address BWA ( = 05H) of the pixel buffers 78L and 78R ( = the read address BRA in the cycle T3 in which the data BOO and BOl is read) .

Thereafter, the read operation is repeated as has been discussed above .

By the way, next is an explanation of the operation of the view driver 80 with reference to a time chart. Fig. 10 is a time chart for explaining the operation of the view driver 80 of Fig. 6. Incidentally, the logic is described in positive logic. Furthermore, explained herein is the operation in the extended display mode and the double resolution mode.

Referring to Fig. 10, when the clock signal CK20 = 1 (high level) and the horizontal scan count HP[IrO] = "01", the view driver 80 asserts the signal "REQ" on the subsequent falling edge of the clock signal "CK40", and negates the signal "REQ" on the next subsequent falling edge of the clock signal "CK40" (i.e., after one clock) .

After the signal "REQ" is asserted, the view driver 80 receives the pixel color code "CpbO", the depth value "ZpbO", the pixel color code "Cpbl" and the depth value "Zpbl" from the pixel buffer controller 76 two clocks after the clock signal "CK40".

Then, when the clock signal CK20 = 1 (high level) and the horizontal scan count HP [1:0] = "11", the view driver 80 outputs, on the subsequent falling edge of the clock signal "CK40", the pixel color code "CpbO" and the depth value "ZpbO" to the subsequent stage as the pixel color code "Cpb" and the depth value "Zpb".

Furthermore, when the clock signal CK20 = 1 (high level) and the horizontal scan^' count HP[1:O] = "01", the view driver 80 outputs, on the subsequent falling edge of the clock signal "CK40", the pixel color code "Cpbl" and the depth value "Zpbl" to the subsequent stage as the pixel color code "Cpb" and the depth value "Zpb".

The above process will be more specifically explained with reference to Fig. 10. When the clock signal CK20 = 1 (high level) and the horizontal scan count HP[l:0] = "01", the view driver 80 asserts the signal "REQ" on the subsequent falling edge "El" of the clock signal "CK40", and negates the signal "REQ" on the next subsequent falling edge "E2" of the clock signal "CK40".

After the signal "REQ" is asserted on the falling edge "El" of the clock signal "CK40", the view driver 80 receives the pixel color code "CpbO" ( = 02H), the depth value "ZpbO" ( = 2H) , the pixel color code "Cpbl" ( = 12H) and the depth value "Zpbl" ( = AH) from the pixel buffer controller 76 on the falling edge "E3" of the clock signal "CK40" after two clocks.

Then, when the clock signal CK20 = 1 (high level) and the horizontal scan count HP[IiO] = "11", the view driver 80 outputs, on the next falling edge E5 of the clock signal "CK40", the pixel color code "CpbO" ( = 02H) and the depth value "ZpbO" ( = 2H) to the subsequent stage as the pixel color code "Cpb" and the depth value "Zpb". Furthermore, when the clock signal CK20 = 1 (high level) and the horizontal scan count HP[IiO] = "01", the view driver 80 outputs, on the next falling edge "E9" of the clock signal "CK40", the pixel color code "Cpbl" ( = 12H) and the depth value "Zpbl" ( = AH) to the subsequent stage as the pixel color code "Cpb" and the depth value "Zpb".

Thereafter, the above process is repeated.

As has been discussed above, the view driver 80 outputs data corresponding to one pixel of the character written to the pixel buffer 78L (for example, the sprite SPl of Fig. 3A) in four cycles of the clock signal CK40, and then outputs data corresponding to one pixel of the character written to the pixel buffer 78R (for example, the sprite SP2 of Fig. 3B) in the following four successive cycles of the clock signal CK40 in order to generate a combined image (for example, the combined image as shown in Fig. 4) , that is to say, a double resolution image. In this case, the resolution is four clocks per pixel. Incidentally, needless to say, the two characters necessary for generating a double resolution image can be prepared by creating the image data which is made only of the odd numbered coloums of the double resolution image and the image data which is made only of the even numbered coloums of the double resolution image.

On the other hand, when it is in the compatible display mode or when even in the extended display mode it is in the standard resolution mode, the view driver 80 outputs data corresponding to one pixel of the character written to the pixel buffer 78L in four cycles of the clock signal CK40, and then outputs data corresponding to one pixel of the same character written to the pixel buffer 78R in the following successive four cycles of the clock signal CK40, i.e., outputs the same data corresponding to one pixel in eight cycles of the clock signal CK40, in order to generate one image (for example, the image as shown in Fig. 2A) , that is to say, a standard resolution image. In this case, the resolution is substantially eight clocks per pixel .

Returning to Fig. 6, the character color palette 84 is comprised of a local memory which includes 256 entries each of which consists of 16 bits, and each entry comprises a hue of 6 bits, a color saturation of 4 bits and a brightness of 6 bits. In other words, one entry represents one color by 16 bits.

A hue can take an integer from 0 to 47, and a color saturation can take an integer from 0 to 15, and a brightness can take an integer from 0 to 47. A transparent color is designated by setting the hue to a value from 48 to 63.

The color palette controller 82 accesses the character color palette 84 with an address "PlA" which is the pixel color code "Cpb" input from the view driver 80, devides the data "PlO" as obtained from the character color palette 84 into a hue "Hc", a color saturation "Sc" and a brightness "Lc", and outputs them to the pixel mixer 90 together with the depth value "Zs" (referred to hereinbelow as the depth value "Zc") . In accordance with the present embodiment, the rate of outputting these values is eight clocks per pixel. Incidentally, in this description, the hue "Hc", the color saturation "Sc", the brightness "Lc" and the depth value "Zc" are referred to also as "pixel data PDC".

The two-dimensional array consisting of the pixel data "PDC" as output from the color palette controller 82 is the above character screen (a sprite(s) + a background screen(s)).

The bitmap generator 86 reads bitmap data which is stored in the memory MEM on the basis of the horizontal scan count signal "HC" and the vertical scan count signal "VC" generated by the video timing generator 100 to be described below, generate pixel data "PDB" of the bitmap screen (which is data comprising a hue "Hb", a color saturation "Sb", a brightness "Lb" and a depth value "Zb") , and outputs the pixel data "PDB" to the pixel mixer 90 at the output rate corresponding to the horizontal resolution of the bitmap screen. Incidentally, the horizontal resolution of the bitmap screen is programmable. The bitmap color palette 88 is designed in the same configuration as the character color palette 84. However, a transparent color is designated by setting the hue to a value of "47", the color saturation to a value of "0" and the brightness to a value of "0" respectively. The pixel mixer 90 mixes the pixel data "PDC" of the character screen as input from the color palette controller 82 and the pixel data "PDB" of the bitmap screen as input from the bitmap generator 86. The pixel mixer 90 determines pixel data to be output (a data item comprising a hue, a color saturation and a brightness) on the basis of the depth values "Zc" and "Zb" indicative of depth positions in the display screen (television frame) . Namely, the pixel mixer 90 outputs the pixel data which is located in the most foreground position (which has the largest depth value) . However, even in the case where the depth value of a data item is indicative of the foreground position, if the hue is indicative of a transparent color, the other pixel data item is selected and output.

The hue, color saturation and brightness of a pixel data item as output from the pixel mixer 90 are referred to respectively as the hue "Hm", color saturation "Sm" and brightness "Lm". The window generator 96 is a circuit which serves to make special effects on the character screen mixed with the bitmap screen

(the mixed screen is referred to simply as the "screen" in the explanation of the window generator 96) , and divide the screen into a masked area and a non-masked area. The special effects can be performed in the masked area by the use of the color modulator 92 to be described below. This window generator 96 is provided with registers which are accessible by the CPU 1 and used to set the coordinates of the start point of the mask, the coordinates of the end point of the mask and the logic of the left edge of the screen respectively in one horizontal line. The logic of the left edge of the screen is a logic indicative of the state at the left edge, i.e., a logic indicative of whether or not the left edge is masked.

The window generator 96 starts outputting the signal "WIN" in accordance with the logic as set of the left edge of the screen, asserts the signal "WIN" when the horizontal scan count signal "HP" reaches the start point of the mask, and negates the signal "WIN" when the horizontal scan count signal "HP" reaches the end point of the mask. In addition, every time the signal "WIN" reaches the start point or end point of the mask, an interrupt is issued to the CPU 1 which then can change the start point and/or end point of the mask in a successive manner. By this configuration, it is possible to provide the mask area of the screen in a variety of profiles.

The noise generator 94 generates noise to produce one of the visual color effects which can be made by the color modulator 92. More specifically, the noise generator 94 is a digital pseudo-random number sequence generator using an M-sequence (polynominal counter) , and outputs the lower three bits of the M-sequence as a noise component "N [2: O]". Incidentally, the noise generator 94 is reset by the reset signal "LPW" in order to prevent a cyclic operation in an abnormal loop.

The color modulator 92 is a circuit which serves to give a variety of visual effects to the color (the hue "Hm", the color saturation "Sm" and the brightness "Lm") which is input thereto. The color modulator 92 is activated when the signal "WIN" is asserted, and inactivated when the signal "WIN" is negated.

The color modulator 92 is provided with a variety of registers and flags which are accessible by the CPU 1 and used to set visual effects. There are four effects which are available as follows.

When the first effect is used, the respective components of color, i.e., the hue, the color saturation and the brightness are individually fixed. These components can be set respectively in the registers (not shown in the figure) corresponding thereto. The value loaded to each of these registers is effective respectively if a flag (not shown in the figure) provided corresponding to the register is set to "1". This flag is provided individually for each component such that it can be determined for each component whether or not the fixed value is used.

When the second effect is used, the value of the brightness "Lm" and the value of the color saturation "Sm" can respectively be halved by setting "1" to flags (not shown in the figure) provided for halftone effect corresponding respectively to the components.

When the third effect is used, negative/positive inversion can be performed. More specifically, a value of "24 " is added to the hue "Hm" and then, if the result exceeds "47 ", a value of "48 " is subtracted from the hue "Hm" in order to wrap around to "0", while the brightness "Lm" is subtracted from a value of "47 ". As a result, the bright and dark are inverted.

When the fourth effect is used, an appropriate degree of noise can be applied to the brightness. More specifically, the lower three bits of the brightness "Lm" and the noise component "N[2:0]" output from the noise generator 94 are bitwise XORed together. Corresponding to the respective three bits, there are flags (not shown in the figure) which indicate whether or not the XOR operation is performed, such that it is possible to adjust the noise amount as applied by these flags.

In this description, the hue "Hm", the color saturation "Sm" and the brightness "Lm" are referred to respectively as the hue "Hf", the color saturation "Sf" and the brightness "Lf" after application of visual effects by the use of the color modulator 92. However, since these visual effects are not necessarily applied, the hue "Hm", the color saturation "Sm" and the brightness "Lm" which are output from the color modulator 92 as they are without visual effects are referred to also as the hue "Hf", the color saturation "Sf" and the brightness "Lf" . The video encoder 98 converts color information (the hue "Hf", the color saturation "Sf" and the brightness "Lf") input from the color modulator 92 and timing information (a composite synchronization signal "SYN", a composite blanking signal "BLK", a burst flag signal "BST", an alternating line signal "LA" and so forth) input from the video timing generator 100 into a composite video signal "VD" in accordance with a signal "VS" as input. The signal "VS" is a signal indicative of a television system (NTSC/PAL) . The alternating line signal "LA" is used when PAL is selected as the television system by the signal "VS". The details of the video encoder 98 are as follows. . The video encoder 98 comprises a 48-base counter of 6 bits which returns to zero after it counts to "47", and this counter is incremented by "4" in the case of NTSC and by "5" in the case of PAL in synchronization with the clock signal "CK40" of 43 MHz. Accordingly, the counter wraps around once every 12 clocks in the case of NTSC and every 9.6 clocks in the case of PAL.

This counter serves as a sub-carrier oscillator which wraps around in the sub-carrier cycle so that the value of this counter indicates the phase thereof. Meanwhile, since the lower 2 bits of the counter are fixed in the case of NTSC, the lower 2 bits are gradually decreased to zero to provide the same pattern.

The video encoder 98 adds the hue "Hf" to the phase data of this sub-carrier to generate phase modulated phase data, which is the phase data of sub-carrier as phase-modulated by the hue "Hf". Then, the video encoder 98 converts this phase modulated phase data into amplitude data by a waveform ROM. Furthermore, the video encoder 98 multiplies the amplitude data by the color saturation "Sf" to generate a signal (i.e., modulated color signal), which is amplitude modulated by the color saturation "Sf". On the other hand, the video encoder 98 generates a brightness signal by adding an offset value of "8" to the brightness "Lf".

The video encoder 98 generates a digital composite video signal by adding the brightness signal and the modulated color signal together, converts the digital composite video signal into an analog signal by means of an AD converter (not shown in the figure) , and externally outputs the analog signal as an analog composite video signal "VD".

When the composite blanking signal "BLK" is asserted, the video encoder 98 sets the brightness signal to a black level which is a value of "8" and, when the composite synchronization signal "SYN" is asserted, the video encoder 98 sets the brightness signal to a synchronization level which is a value of "0". In addition, the video encoder 98 controls the hue and the color saturation respectively to be zero when the composite blanking signal "BLK" is asserted, and to be a constant value when the burst flag signal "BST" is asserted. Thus, in this case, the hue "Hf" and the color saturation "Sf" input from the color modulator 92 are not used. Furthermore, when the composite blanking signal "BLK" is asserted, the video encoder 98 outputs only the brightness signal as the composite video signal "VD" without adding the modulated color signal. However, even when the composite ^• blanking signal "BLK" is asserted, the video encoder 98 outputs a color burst signal in a predetermined timing.

The video timing generator 100 generates the timing signals such as the horizontal scan count signal "HC", the vertical scan count signal "VC", the composite synchronization signal "SYN", the composite blanking signal "BLK", the burst flag signal "BST" and the alternating line signal "LA" on the basis of clock CK40.

The video timing generator 100 comprises a divider which changes the dividing ratio in accordance with the signal "VS", i.e., depending upon whether NTSC or PAL. While the timing signals generated by the video timing generator 100 can be adjusted by the CPU 1, these signals are initialized such that one horizontal cycle comprises 2730 clocks of the clock signal "CK40" and one vertical cycle comprises 263 horizontal cycles in the case of NTSC. Also, in the case of PAL, these timing signals are initialized such that one horizontal cycle comprises 2724 clocks of the clock signal "CK40" and one vertical cycle comprises 314 horizontal cycles.

These dividing ratios are used for the purpose of providing horizontal and vertical cycles approximately corresponding to the standard cycles of NTSC and PAL and the interleave mode in accordance with the standard signals. In the case of NTSC standard, line and frame interleaving is performed with a differential phase of 180 degrees, while in the case of line interleaving based on PAL standard is performed with a differential phase of 270 degrees. However, in the case of PAL, frame interleaving of this embodiment is performed with a differential phase of 180 degrees, which differs from the standard phase. This phase difference is employed in order to lessen the dot- interference of the sub-carrier signal with the brightness signal in the case of non-interlaced scanning.

In this case, not shown in the figure, the video timing generator 100 is provided with a register for setting the horizontal cycle, a register for setting the left position of the horizontal synchronization pulse, a register for setting the right position of the equalizing pulse, a register for setting the right position of the horizontal synchronization pulse, a register for setting the left position of the color burst signal, a register for setting the right position of the color burst signal, a register setting the left position of a video field, a register for setting the right position of the vertical synchronization pulse, a register for setting the right position of the video field, a register for setting the horizontal cycle, a register for setting the bottom position of the video field, a register for setting the bottom position of the color burst signal, a register for setting the top position of the equalizing pulse, a register for setting the top position of the vertical synchronization pulse, a register for setting the bottom position of the vertical synchronization pulse, a register for setting the bottom position of the equalizing pulse, a register for setting the top position of the color burst and a register for setting the top position of the' video field. Accordingly, the CPU 1 can adjust the general profile of the composite video signal "VD" by accessing these registers.

The video position adjuster 102 adjusts the position of the character screen in relation to the display screen (television frame) . More specific description is as follows.

The video position adjuster 102 gives an offset to each of the horizontal scan count signal "HC" and the vertical scan count signal "VC" in order to generate the horizontal scan count signal "HP" and the vertical scan count signal "VP". The horizontal scan count signal "HP" and the vertical scan count signal "VP" are output to the respective functional blocks used for generating the character screen as discussed above. The CPU 1 accesses the control registers (not shown in the figure) , which are implemented within the video position adjuster 102, for setting the respective offsets.

In this case, as has been discussed above, the bitmap generator 86 makes use of the horizontal scan count signal "HC" and the vertical scan count signal "VC" which are generated by the video timing generator 100. Accordingly, the video position adjuster 102 can adjust the relative position between the character screen and the bitmap screen.

The video function generator 104 determines the timing of finishing the drawing of each frame of the character screen on the basis of the horizontal scan count signal "HP" and the vertical scan count signal "VP", and outputs a non-maskable interrupt signal "NMI" to the CPU 1 at the timing. By this configuration, the CPU 1 can be informed of when drawing one frame of the character screen is finished. Also, when both the horizontal scan count signal "HP" and the vertical scan count signal "VP" matches corresponding one of predetermined values stored in control registers (not shown in the figure) , the video function generator 104 outputs an interrupt request signal "IRQ". The CPU 1 can access these control registers in order to control the timing of the interrupt request signal "IRQ". Furthermore, the video function generator 104 serves to latch the value of the horizontal scan count signal "HP" and the value of the vertical scan count signal "VP" in synchronization with the edges of light-pen input signals "LPO" and "LPl". The CPU 1 can read these values as latched through the first bus 31. Incidentally, the non-maskable interrupt signal "NMI" and the interrupt signal "IRQ" are output from the graphics processor 3 to the CPU 1 respectively as the interrupt request signals "INRQ".

The CPU 1 can freely access the display mode control register 101 through the first bus 31, and can dynamically modify the value of the display mode control information "CHRMODE".

Meanwhile, the sprite DMA controller 50, the first background generator 56 and the second background generator 60 are provided respectively with a function of requesting the use of the first bus 31 so that they can actively obtain data from the main memory 17. Also, the character fetcher 68 and the bitmap generator 86 have a function of requesting the use of the first bus 31 and the second bus 33 so that they can actively obtain data from the main memory 17 and the external memory 45. By the way, next is a description of the previous generation processor, with which the processor 1000 of Fig. 1 retains backward compatibility, in regard to the differences therebetween. In the case where a constituent element of the previous generation processor is referred to, the prefix "previous generation" is attached in front of the constituent element.

The configuration of the previous generation processor is similar to the configuration of the processor 1000 of Fig. 1. In addition, the configuration of the previous generation graphics processor is similar to the configuration of the graphics processor 3 as shown in Fig. 5 and Fig. 6. However, it should be noted that the previous generation video function generator is not provided with the display mode control register. Accordingly, the previous generation processor can display images only at the standard resolution corresponding to the compatible display mode of the processor 1000. However, the previous generation processor can adjust the resolution of a bit map screen in the same manner as the processor 1000.

Thus, the graphics processor of the previous generation processor is provided with only one pixel buffer. The configuration and operation of the previous generation pixel buffer are the same as the configuration and operation of the pixel buffer 78L. In addition to this, in the case of the previous generation processor, the flip parameter "Fs" is used always as information indicative of inversion. Accordingly, the previous generation strip generator determines a strip to be extracted on the basis of the vertical .position information "Ys", the flip information Fs[I] indicative of inversion in the vertical direction, and the vertical scan count signal "VP". In accordance with the previous generation configuration as thus described, since the flip information Fs[I] is always used, if Fs[I] = 1 (indicative of inversion in the vertical direction) , a strip is determined on the basis of the values obtained by inverting the vertical coordinate "Ys" of the character as input in the vertical direction (inversion in the high and low direction) . This is the same as in the compatible display mode of the processor 1000. However, since the flip information Fs[I] is not used in the subsequent stages in the case of the previous generation configuration, the flip information output to the subsequent stages is only the flip information Fs[O].

Accordingly, the flip information Fs[O] is input to the previous generation character fetcher, from which the flip information Fs[O] is output to the subsequent stages. This differs from the character fetcher 68 of the processor 1000 which receives and outputs the flip information Fs [1:0].

The previous generation pixel generator always takes the flip information Fs[O] into consideration, and if Fs[O] = 1 indicative of the inversion in the horizontal direction, the horizontal position information "Xp" for each pixel is calculated by decrement from the position advanced by the horizontal size indicated by the size information "Ss" in the reverse direction. This is the same as in the compatible display mode of the processor 1000. However, since the flip information Fs[O] is not used in the subsequent stages in the case of the previous generation configuration, it is not output to the subsequent stages.

Accordingly, unlike the transparency controller 72 of the processor 1000, the bits "Cmb" and "Ofs" are not input to or output from the previous generation transparency controller.

In addition, since there is only one pixel buffer in the case of the previous generation configuration, when a request for write operation is issued to the previous generation pixel buffer controller, the previous generation draw driver asserts the signal "REQ". Accordingly, the previous generation pixel buffer controller performs arbitration between a request for write operation issued through the signal "REQ" from the previous generation draw driver and a request for read operation issued through the signal "REQ" from the previous generation view driver, and accesses the previous generation pixel buffer in accordance with the arbitration result.

The previous generation view driver issues the request for reading data from the previous generation pixel buffer, and outputs the pixel color code "Cpb" and the depth value "Zpb" as read to the subsequent stage. In this regard, the previous generation view driver differs from the view driver 80 which outputs the pixel color code "CpbO", the depth value "ZpbO", the pixel color code "Cpbl" and the depth value "Zpbl" to the subsequent stage. Accordingly, in the case of the previous generation configuration, one pixel corresponds to one pixel set of the processor 1000, and thereby images are displayed at a half resolution of the double resolution of the processor 1000.

The previous generation processor is similar to the processor 1000 in regard to other points, and therefore no redundant description is repeated. In other words, except for the display processing in the extended display mode, the operation of the processor 1000 is the same as the operation of the previous generation processor.

By the way, as has been discussed above, the present embodiment can switch between the compatible display mode and the extended display mode by the use of the display mode control information "CHRMODE". Accordingly, when the compatible display mode is set, it is possible to run any software, with no modification, which is designed for the previous generation processor, which is capable of displaying images only in the standard resolution mode but which is not implemented with an extended display mode. As a result, while retaining backward compatibility with software which is runnable by the previous generation processor, it is possible to display images at a high resolution in the extended display mode.

This display mode control information "CHRMODE" is set in the display mode control register 101, which is freely accessed by the CPU 1 through the first bus 31. As a result, the CPU 1 can dynamically switch between the compatible display mode and the extended display mode.

By the way, for example, in the initialization process after power up, the processor 1000 of Fig. 1 initializes the display mode control information "CHRMODE" of the display mode control register 101 to "0" indicative of the compatible display mode. Incompatible software which can be run in the extended display mode of the processor 1000 of Fig. 1 executes an instruction for switching the compatible display mode to the extended display mode, i.e., the instruction operable to rewrite a display mode control information "CHRMODE" to "1" indicative of the extended display mode, for example, in its start-up routine.

By this process, after then, while the incompatible software runs, the flip parameters Fs[IrO] function as the switch bit "Cmb" and the select bit "Ofs" respectively. Contrary to this, since the instruction for switching the compatible display mode to the extended display mode is not used in compatible software which is made in advance of developing the processor 1000 of Fig. 1 and can be run only by the previous generation processor, the display mode control information "CHRMODE" is maintained in the initialized value, i.e., "0" indicative of the compatible display mode, and thereby the flip^' parameter Fs [1:0] is used as inversion information. Accordingly, the processor 1000 of Fig. 1 can run the compatible software in the same manner as the previous generation processor.

In addition to this, in the extended display mode of the present embodiment, the resolution is switched in accordance with the flip parameter Fs[I]₁ by assigning pixel data to the respective pixels of each pixel set on a "pixel to pixel" basis (in the double resolution mode) or by assigning pixel data to the respective pixel set on a "pixel set to pixel set" basis (in the standard resolution mode) . Accordingly, it is possible to change the resolutions for the respective images independently in the same screen by utilizing the standard resolution mode for an image which is satisfactorily displayed even with a lower resolution and utilizing the double resolution mode for an image which requires a higher resolution for satisfactorily displaying it. As the result, the size of the image data can be optimized, thereby it is possible to reduce the memory capacity for storing image data and lessen the processing load on the processor 1000, and in addition to this, to lessen the load on the bandwidth of the bus for transferring image data.

Furthermore, in the double resolution mode of the extended display mode of the present embodiment, the pixel data is assigned to the left hand pixels of pixel sets (the pixel data is assigned to the pixel buffer 78L) if the flip parameter Fs[O] = 0, while the pixel data is assigned to the right hand pixels of pixel sets (the pixel data is assigned to the pixel buffer 78R) if the flip parameter Fs[O] = 1.

In this way, the pixel data is assigned to either left or right pixel of each pixel set in accordance with the flip parameter Fs[O] in order to combine two characters (two items of image data) . In other words, a combined image is generated by interleaving the two characters to be combined so that the respective pixels thereof are arranged in turn one pixel after another. Accordingly, the characters

(image data) to be combined can be prepared in the exactly same format. In addition to this, it is possible to employ the exactly same format for the format of characters (image data) used when it is in the compatible display mode or when even in the extended display mode it is in the standard resolution mode, and the format of characters (image data) used when it is in the double resolution mode of the extended display mode.

Furthermore, in the case of the present embodiment, the FSC registers 57 and 61 are provided in correspondence with the first background screen and the second background screen. The FSC registers 57 and 61 in which the flip parameters Fl [1:0] and F3[l:0] are stored are freely accessed by the CPU 1 through the first bus 31. Because of this, it is possible to dynamically switch between the standard resolution mode and the double resolution mode for displaying the first background screen and the second background screen, and dynamically change the selection of a left or a right pixel in the double resolution mode.

Furthermore, in the case of the present embodiment, the sprite memory 52 is provided for storing the flip parameters FO [1:0] of one sprite in each entry. Accordingly, the CPU 1 can dynamically change the contents thereof through the first bus 31, and for each sprite the CPU 1 can dynamically switch between the standard resolution mode and the double resolution mode and dynamically change the selection of a left or a right pixel in the double resolution mode.

Furthermore, in the case of the present embodiment, it is possible to utilize without modification the storage unit (the FSC registers 57 and 61, and the sprite memory 52) for storing the flip parameters Fs [1:0] and the data path for processing the information stored therein, and thereby to realize the processor 1000 which is designed on the basis of the previous generation processor but extended in functionality without substantial circuit modification. Furthermore, in the case of the present embodiment, the displaying of high resolution images can be realized by providing the two pixel buffers 78L and 78R. It is possible as described above to realize the graphics processor 3 capable of displaying images at a high resolution only by adding another pixel buffer having the same configuration as the pixel buffer of the previous generation processor.

Furthermore, in the case of the present embodiment, since the same pixel data is stored in the corresponding positions of both the pixel buffers 78L and 78R in the compatible display mode or the standard resolution mode of the extended display mode, the same pixel data is read from both the pixel buffers 78L and 78R, and as a result the displaying of images becomes possible at a resolution corresponding to the standard resolution mode.

Furthermore, in the case of the present embodiment, since the write operation to the pixel buffers 78L and 78R is performed on the basis of the result of comparison of the depth value, when there are pixel data items to be drawn in the same position, the pixel data item having a higher display priority can be written to the pixel buffers 78L and 78R irrespective of the order of writing pixels.

Furthermore, in the case of the present embodiment, by initializing the data of a pixel which need no longer be used after completing the read operation of the data by the view driver 80, new pixel data can be written to the storage location of the pixel buffer 78L which is initialized. Accordingly, a buffer for one complete line is not necessarily required, but it is possible to provide the pixel buffer 78L having a smaller capacity than required for one complete line and cyclically use it. This is true also in the case of the pixel buffer 78R. Thereby, the cost can be reduced.

Furthermore, in the case of the present embodiment, the read and write operations of the pixel buffers 78L and 78R can be realized with a simple circuit configuration in an effective manner by providing the draw driver 74, the pixel buffer controller 76 and the view driver 80.

Furthermore, in the case of the present embodiment, a combined image is generated by sequentially outputting, in a time-interleaved manner, the pixel data of the left and right pixels of pixel sets which are read from the pixel buffers 78L and 78R to the subsequent stage in order to form pixel sets. Namely, in the graphics processor 3 which performs image processing on the basis of the scan position of the scan line, it is possible to accomplish the displaying of images at a high resolution only with a simple circuit configuration. Meanwhile, the present invention is not limited to the above embodiments, and a variety of variations and modifications may be effected without departing from the spirit and scope thereof, as described in the following exemplary modifications.

(1) In the above example, an indirect designation method making use of the color palettes 84 and 88 is employed for designating the display colors. In other words, the character pattern data and bitmap data are represented by color codes. However, the system for representing colors is not limited thereto, but the present invention is similarly applicable to the case where a direct designation method is employed such that color information is described in terms of the hue "H", the color saturation "S" and the brightness "L", or in terms of any other color space.

(2) In the above example, one pixel set is composed of two pixels. However, the number of pixels constituting the pixel set is not limited thereto, but can be three or more. If the time required for displaying one pixel set is fixed, the resolution increases as the number of pixels of which one pixel set is composed increases. Also, in this case, the pixel buffers are implemented of the same number as the pixels of which one pixel set is composed. (3) In the above example, there are two pixel buffers each of which capable of storing data corresponding to a fewer number of pixels than required for one line. However, alternatively, there may be provided two line buffers each of which is provided for one line or two frame buffers each of which is provided for one frame. (4) In the above example, while one pixel set is composed of two pixels, the select bit "Ofs" is used to select either pixel. In this case, one item of pixel data is assigned to one pixel (equal assignment) . However, it is possible to make each pixel set of three or more pixels and to unequally assign pixel data. For example, while one pixel set is composed of three pixels, it is possible to assign the same item of pixel data to the two pixels in the left and center positions and assign one item of pixel data to the pixel in the right position, or alternatively assign the same item of pixel data to the two pixels in the left and right positions and assign one item of pixel data to the pixel in the center position.

While the present invention has been described in terms of embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting in any way on the present invention.

Claims

1. An image display apparatus operable to display a combined image which is formed by combining "N" image data items on a display screen, where "N" is two or a larger integer, wherein the display screen is composed of a plurality of lines which are arranged in a first direction and each of which is composed of a plurality of pixel sets, which are arranged in a second direction and each of which consists of "N" pixels arranged in a predetermined order from a zeroth to an (N-I) th pixel, the second direction being perpendicular to the first direction, wherein each of the image data items is associated with pixel designation information which designates the M-th pixel of each pixel set, where "M" is an integer from "0" to (N-I) and takes a different value for each image data item, and wherein a displaying process is performed by making use of each of pixel data items, of which one of the image data items is composed, as data to be used for displaying the M-th pixel of each of the pixel sets corresponding to the one of the image data items as designated by the pixel designation information which is associated with the one of the image data items .

2. The image display apparatus as claimed in claim 1 wherein the second direction is a horizontal direction.

3. The image display apparatus as claimed in claim 2 wherein N = 2.

4. The image display apparatus as claimed in claim 1 wherein each of the image data items is associated with resolution setting information which designates either a standard resolution mode for displaying images at a predetermined resolution or a high resolution mode for displaying images at a resolution higher than the predetermined resolution, wherein the image display apparatus serves to: when an image data item is associated with the resolution setting information designating the standard resolution mode, irrespective of the content of the pixel designation information which is associated with this image data item, assign the same pixel data item corresponding to the pixel set to the zeroth to (N-I) th pixels of the pixel set for each pixel set corresponding to this image data item, and when an image data item is associated with the resolution setting information designating the high resolution mode, assign the pixel data items of this image data item to the M-th pixels of the pixel sets corresponding to this image data item as designated by the pixel designation information which is associated with this image data item.

5. The image display apparatus as claimed in claim 4 further comprising a display mode switching unit operable to switch between a first display mode and a second display mode, wherein when the first display mode is set, irrespective of the content of the resolution setting information associated with an image data item, the same pixel data item corresponding to the pixel set is assigned to the zeroth to (N-I) th pixels of the pixel set for each pixel set corresponding to this image data item.

6. The image display apparatus as claimed in claim 5 wherein the display mode switching unit includes a display mode control register which can be externally and dynamically set to data indicative of either the first display mode or the second display mode, and wherein a displaying process is performed in either the first display- mode or the second display mode on the basis of the data set in the display mode control register.

7. The image display apparatus as claimed in claim 4 further comprising:

"N" resolution setting information storing registers provided corresponding to the "N" image data items and each of the "N" resolution setting information storing registers operable to store the resolution setting information associated with the image data item corresponding thereto; and

"N" pixel designation information storing registers provided corresponding to the "N" image data items and each of the "N" pixel designation information storing registers operable to store the pixel designation information associated with the image data item corresponding thereto, wherein the resolution setting information storing registers and the pixel designation information storing registers can be externally accessed in order to dynamically change the information stored therein.

8. The image display apparatus as claimed in claim 4 further comprising a memory, wherein said memory includes:

"N" resolution setting information storing areas provided corresponding to the "N" image data items and each of the "N" resolution setting information storing areas operable to store the resolution setting information associated with the image data item corresponding thereto; and

"N" pixel designation information storing areas provided corresponding to the "N" image data items and each of the "N" pixel designation information storing areas operable to store the pixel designation information associated with the image data item corresponding thereto.

9. The image display apparatus as claimed in claim 5 wherein, in the first display mode, a displaying process is performed by treating the resolution setting information and the pixel designation information as information for controlling a predetermined image process.

10. The image display apparatus as claimed in claim 9 wherein the predetermined image process is image inversion in the first direction and/or the second direction.

11. The image display apparatus as claimed in claim 1 further comprising a zeroth to an (N-I) th storage unit, wherein the pixel data of an image data item is stored in the M-th storage unit as designated by the pixel designation information which is associated with this image data item.

12. The image display apparatus as claimed in claim 11 further comprising: a read and write control unit operable to receive read and write requests for the storage units, and read and write operations for the storage units; a pixel data write request unit operable to issue the write request to the read and write control unit in order to write the pixel data of an image data item in the M-th storage unit as designated by the pixel designation information which is associated with this image data item; and a pixel data read request unit operable to issue the read request to the read and write control unit in order to read the pixel data from the zeroth to (N-I) th storage units.

13. The image display apparatus as claimed in claim 12 wherein each of the image data items is associated with resolution setting information which designates either a standard resolution mode for displaying images at a predetermined resolution or a high resolution mode ^' for displaying images at a resolution higher than the predetermined resolution, and wherein the pixel data write request unit is operable to issue the write request for writing the pixel data of an image data item to all the zeroth to (N-I) th storage units, when the resolution setting information designates the standard resolution mode, irrespective of the content of the pixel designation information, and issue the write request for writing the pixel data of an image data item to the M-th storage unit as designated by the pixel designation information which is associated with this image data item, when the resolution setting information designates the high resolution mode.

14. The image display apparatus as claimed in claim 13 further comprising a display mode switching unit operable to switch between a first display mode and a second display mode, wherein the pixel data write request unit is operable to issue the write request to the read and write control unit to write the pixel data of an image data item to all the zeroth to (N-I) th storage units, when the first display mode is set, irrespective of the content of the resolution setting information associated with this image data item.

15. The image display apparatus as claimed in claim 12 wherein the pixel data read request unit is operable to receive the pixel data which is read from the zeroth to (N-I) th storage units and sequentially output this pixel data in a time-interleaved manner to a subsequent stage.

16. The image display apparatus as claimed in claim 12 wherein each of the pixel data items, of which one of the image data items is composed, includes color data which directly or indirectly designates the display color of a pixel and depth data which designates a display priority, and wherein when receiving the write request from the pixel data write request unit, the read and write control unit reads the depth data stored in the location for writing of said storage unit, compares the depth data as read and the depth data contained in the pixel data which the pixel data write request unit requests to write, and if the depth data contained in the pixel data which the pixel data write request unit requests to write is given a display priority higher than the depth data as read, the pixel data which the pixel data write request unit requests to write is written to the location for writing of the storage unit.

17. The image display apparatus as claimed in claim 16 wherein after the pixel data is read from the location for reading of said storage unit in accordance with the read request from the pixel data read request unit, the read and write control unit initializes the depth data stored in the location for reading of the storage unit to a value indicative of the lowest display priority.

18. A method of generating a two-dimensional pixel data array for forming a display screen which includes images having different effective resolutions, wherein each of the image data items having the same resolution in the row direction of the two-dimensional pixel data array is associated with a flag designating twice the same resolution and a flag indicative of either an odd or an even numbered element of each row of the two-dimensional pixel data array, the method comprising: when the flag designating twice the same resolution is turned off, assigning each of the pixel data items of the image data item to two adjacent elements of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to the same resolution; and when the flag indicative of twice the same resolution is turned on, in accordance with the flag indicative of either an odd or an even numbered element, assigning each of the pixel data items of the image data item to an odd or an even numbered element of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to twice the same resolution.

19. A compatible processor operable to run the software that can be run on a previous generation processor which is capable of generating images at a predetermined resolution, and operable to generate images at twice the predetermined resolution, said compatible processor comprising: an image ^• display unit operable to generate a two-dimensional pixel data array for forming a display screen corresponding to twice the predetermined resolution in the row direction of the two- dimensional pixel data array; and a data processing unit operable to process data in accordance with a predetermined program and output image data items having the same resolution which corresponds to the predetermined resolution to the image display unit, wherein there is a display mode control register for storing display mode control information indicative of either a compatible display mode in which it is possible to run the software that can be run on the previous generation processor or an extended display mode in which it is possible to display images at twice the predetermined resolution in the row direction of the two-dimensional pixel data array, wherein when the display mode control information indicates the extended display mode, the image display unit makes use of a value stored in a field of the image data item as information indicative of either odd or even numbered columns of the two-dimensional pixel data array, wherein when the display mode control information indicates the extended display mode, the image display unit can generate a combined image having twice the predetermined resolution from a pair of image data items which are associated respectively with the odd and even numbered columns by the information stored in the field indicative of either odd or even numbered columns by assigning the pixel data items of one of the image data item pair associated with the odd numbered columns to odd numbered elements of each row of the two-dimensional pixel data array corresponding to the positions of the display screen where the pixel data items of the one of the image data item pair are to be displayed, and assigning the pixel data items of the other image data item associated with the even numbered columns to even numbered elements of each row of the two-dimensional pixel data array corresponding to the positions of the display screen where the pixel data items of the other image data item are to be displayed, and wherein when the display mode control information indicates the compatible display mode, the image display unit assigns each of the pixel data items of the image data item to two adjacent elements of the each row of the two-dimensional pixel data array corresponding to the position of the display screen where the each of the pixel data items is to be displayed, such that an image is displayed at an effective resolution corresponding to the predetermined resolution.

20. The compatible processor as claimed in claim 19 wherein when the display mode control information indicates the compatible display mode, the value stored in the field of the image data item is used as information indicative of an image inversion.