WO2006134550A3 - Memory controller - Google Patents
Memory controller Download PDFInfo
- Publication number
- WO2006134550A3 WO2006134550A3 PCT/IB2006/051876 IB2006051876W WO2006134550A3 WO 2006134550 A3 WO2006134550 A3 WO 2006134550A3 IB 2006051876 W IB2006051876 W IB 2006051876W WO 2006134550 A3 WO2006134550 A3 WO 2006134550A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- stl
- buffer
- data streams
- memory controller
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
Abstract
A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface. The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data stream (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B) and for dynamically allocating buffers (PFB, WBB) for at least one of the data streams (STl - ST4). The second interlace is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. Furthermore, a buffer dimensioning unit (BDU) is provided for dimensioning the buffer (B) for at least one of the data streams (STl - ST4).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06765728A EP1894108A2 (en) | 2005-06-13 | 2006-06-13 | Memory controller |
JP2008516481A JP2008544359A (en) | 2005-06-13 | 2006-06-13 | Memory controller |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05105145.6 | 2005-06-13 | ||
EP05105145 | 2005-06-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006134550A2 WO2006134550A2 (en) | 2006-12-21 |
WO2006134550A3 true WO2006134550A3 (en) | 2007-03-08 |
Family
ID=37235997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2006/051876 WO2006134550A2 (en) | 2005-06-13 | 2006-06-13 | Memory controller |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1894108A2 (en) |
JP (1) | JP2008544359A (en) |
CN (1) | CN101198941A (en) |
WO (1) | WO2006134550A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE538435T1 (en) * | 2005-06-09 | 2012-01-15 | Nxp Bv | MEMORY CONTROL AND METHOD FOR COUPLING A NETWORK AND A MEMORY |
CN100557584C (en) | 2005-06-09 | 2009-11-04 | Nxp股份有限公司 | Be used for Memory Controller and method that network and storer are coupled |
US20120066444A1 (en) * | 2010-09-14 | 2012-03-15 | Advanced Micro Devices, Inc. | Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation |
WO2014193376A1 (en) * | 2013-05-30 | 2014-12-04 | Hewlett-Packard Development Company, L.P. | Separate memory controllers to access data in memory |
CN105630714B (en) * | 2014-12-01 | 2018-12-18 | 晨星半导体股份有限公司 | Interface resource analytical equipment and its method |
CN109981620A (en) * | 2019-03-14 | 2019-07-05 | 山东浪潮云信息技术有限公司 | A kind of back office interface management system |
KR20210066631A (en) | 2019-11-28 | 2021-06-07 | 삼성전자주식회사 | Apparatus and method for writing data in memory |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6553446B1 (en) * | 1999-09-29 | 2003-04-22 | Silicon Graphics Inc. | Modular input/output controller capable of routing packets over busses operating at different speeds |
US6813701B1 (en) * | 1999-08-17 | 2004-11-02 | Nec Electronics America, Inc. | Method and apparatus for transferring vector data between memory and a register file |
US6859454B1 (en) * | 1999-06-30 | 2005-02-22 | Broadcom Corporation | Network switch with high-speed serializing/deserializing hazard-free double data rate switching |
-
2006
- 2006-06-13 EP EP06765728A patent/EP1894108A2/en not_active Withdrawn
- 2006-06-13 WO PCT/IB2006/051876 patent/WO2006134550A2/en not_active Application Discontinuation
- 2006-06-13 JP JP2008516481A patent/JP2008544359A/en not_active Withdrawn
- 2006-06-13 CN CNA2006800210944A patent/CN101198941A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6859454B1 (en) * | 1999-06-30 | 2005-02-22 | Broadcom Corporation | Network switch with high-speed serializing/deserializing hazard-free double data rate switching |
US6813701B1 (en) * | 1999-08-17 | 2004-11-02 | Nec Electronics America, Inc. | Method and apparatus for transferring vector data between memory and a register file |
US6553446B1 (en) * | 1999-09-29 | 2003-04-22 | Silicon Graphics Inc. | Modular input/output controller capable of routing packets over busses operating at different speeds |
Also Published As
Publication number | Publication date |
---|---|
CN101198941A (en) | 2008-06-11 |
JP2008544359A (en) | 2008-12-04 |
WO2006134550A2 (en) | 2006-12-21 |
EP1894108A2 (en) | 2008-03-05 |
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