WO2006127776A1

WO2006127776A1 - Metal electrodes for elimination of spurious charge effects in accelerometers and other mems devices

Info

Publication number: WO2006127776A1
Application number: PCT/US2006/020029
Authority: WO
Inventors: Henry C. Abbink; Gabriel M. Kuhn; Howard Ge; Daryl Sakaida
Original assignee: Northrop Grumman Corporation
Priority date: 2005-05-25
Filing date: 2006-05-24
Publication date: 2006-11-30

Abstract

A MEMS device, in particular an accelerometer, configured to eliminate spurious charge effects having a first electrode with a top and bottom surface, a second electrode with a top and bottom surface, and a proof mass paddle with a top and bottom surface. The top surface of the proof mass paddle is beneath the bottom surface of the first electrode and the bottom surface of the proof mass paddle is above the top surface of the second electrode. The MEMS device includes a first metal layer on the top and bottom surfaces of the proof mass paddle, on the bottom surface of the top electrode, and on the top surface of the bottom electrode. The MEMS device can also have a second metal layer on top of the first metal layer. The device is manufactured using direct bonding/ fusion bonding.

Description

METAL ELECTRODES FOR ELIMINATION OF SPURIOUS CHARGE EFFECTS IN ACCELEROMETERS AND OTHER MEMS DEVICES

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Provisional Application No. 60/684,432, filed May 25, 2005, herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

[0002] The invention relates generally to Micro-Electro-Mechanical Systems

(MEMS). More particularly, the invention relates to electrode and paddle surfaces that reduces spurious charge effects.

2. DESCRIPTION OF THE RELATED ART

[0003] Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through microfabrication technology. The electronics in a MEMS device are fabricated using Integrated Circuit (IC) technology (CMOS, Bipolar, or BICMOS processes), while the micromechanical components are fabricated using "micromachining" techniques that selectively etch away or add new layers to the silicon wafer to form mechanical and electromechanical devices.

[0004] MEMS devices are widely used in automotives, navigation systems, chemica and biological sensors, microoptics, accelerometers, pressure sensors and othe devices. A common approach to fabrication of MEMS devices is the so-called bul MEMS process. This process consists of processing two or three silicon wafers wi1 patterns machined by Deep Reactive Ion Etching (DRIE) to form the structure used each layer, and then bonding these layers together by a process called direct bonding to form a hermetic cavity.

[0005] An example of a MEMS structure is the Silicon Accelerometer (SiAC™)

Sensor 100, shown in FIG. 1. This structure is fabricated from two silicon-on- insulator (SOI) wafers and one prime silicon wafer. The SOI wafers provide the covers, electrodes and guards, while the prime wafer provides the Proof Mass (PM) layer. The electrodes are positioned parallel to one another to form a capacitor in between. During operation, the capacitance is used to determine the gap between the paddle and each electrode. An electronic circuit supplies the proper voltage pulses to force the paddle to null, defined as the paddle position where both capacitances are equal.

[0006] In current fabrication methods, the wafers are contacted for bonding in ambient class 10 air which contains 20% oxygen and moisture at 50% relative humidity (RH). When the bonded wafers are annealed in excess of 1000 degrees C, the oxygen and water react with the surface of the silicon to form silicon dioxide. Measurements of oxide thickness of dissected chips range from 70 to 100 Angstroms. This oxide and inherent charges at the oxide-silicon interface are responsible for several performance problems.

[0007] One performance problem with existing accelerometers is bias relaxation on the electrode and paddle surfaces. When a chip is stored at an elevated temperature (e.g. 85 degrees C for an hour) and then brought back to room temperature, it can take a number of hours for the bias to stabilize. A differential change of charge in the gap of only 10⁴ electronic charges/cm² results in a bias relaxation of about 100 micro G. This is on the order of parts per million (ppm) of the intrinsic silicon-silicon dioxide interface charge.

[0008] Another performance problem is that the paddle gets electrostatically stuck to one of the electrodes. This can occur during testing for electrical leakage or just from pulses applied when attempting to cage. When this happens the chip is inoperable. This problem is wafer stack dependent.

[0009] Another problem, for which charge trapping is a suspected cause, is bias turn- on to turn-on repeatability. If it were possible to completely eliminate native oxide from the critical surfaces, and somehow do the bonding process without causing oxidation, the situation would actually be much worse, because the charge density on clean silicon surfaces is much greater than on the best oxidized surface.

[0010] With an increasing demand for improved MEMS devices, there remains a continuing need in the art for a MEMS device that reduces spurious charge effects formed on the electrode and paddle surfaces.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The exact nature of this invention, as well as the objects and advantages thereof, will become readily apparent from consideration of the following specification in conjunction with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof and wherein:

[0012] FIG. 1 is a perspective view of a prior art silicon accelerometer sensor.

[0013] FIG. 2 is a perspective view of a silicon accelerometer sensor before assembly, according to one embodiment of the present invention. [0014] FIG. 3 is an assembly drawing of the silicon accelerometer sensor of FIG. 2, according to one embodiment of the present invention. [0015] FIG. 4 is a top view of the silicon accelerometer sensor of FIG. 2, according to one embodiment of the present invention. [0016] FIG. 5 is a front view of the silicon accelerometer sensor of FIG. 2, according to one embodiment of the present invention. [0017] FIG. 6 is a side view of the silicon accelerometer sensor of FIG. 2, according to one embodiment of the present invention. [0018] FIG. 7 is a side view of a paddle and two parallel electrodes, according to one embodiment of the present invention. [0019] FIG. 8 is a side view of a paddle and two parallel electrodes, according to another embodiment of the present invention.

SUMMARY OF THE INVENTION

[0020] A MEMS device configured to eliminate spurious charge effects having a top and a bottom electrode, a proof mass paddle between the electrodes, and at least one metal layer on the proof mass paddle, the top electrode, and the bottom electrode. The metal layer preferably has a melting point higher than the temperature used for annealing. The outer or exposed metal layer is preferably substantially inert to oxidation. Iridium is preferably used if one metal layer is coated on top of the proof mass paddle, the top electrode, or the bottom electrode. In an alternative embodiment, if a plurality of metal layers are used, then the metal layer in contact with the surface of the proof mass paddle, the top electrode, or the bottom electrode can be Chromium, Tungsten, or Iridium, while the exterior metal layer can be Iridium or Platinum.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0021] Methods and systems that implement the embodiments of the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention. Reference in the specification to "one embodiment" or "an embodiment" is intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an embodiment of the invention. The appearances of the phrase "in one embodiment" or "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements. In addition, the first digit of each reference number indicates the figure in which the element first appears.

[0022] FIG. 2 is a perspective view of a silicon accelerometer sensor 200 before assembly, according to one embodiment of the present invention. The sensor 200 has a first outside layer 210, a second outside layer 215, a first guard layer 220, a second guard layer 225, and a proof mass layer 230. The proof mass layer 230 is sandwiched between the first and second guard layers 220 and 225, which are then sandwiched between the first and second outside layers 210 and 215. The sensor 200 also has a via 235 to facilitate a path or opening for circuit shorting. The sensor 200 is fabricated from two silicon-on-insulator (SOI) wafers and one prime silicon wafer. The SOI wafers provide the first and second outside layers 210 and 215, and the first and second guard layers 220 and 225. The prime silicon wafer provides the proof mass layer 230.

[0023] On the surface of each wafer layer 210-230 is a layer of oxide, typically 1 micron thick. When the layers 220-230 are bonded together, a 2 micron layer of oxide is formed between the guard layers 220 and 225 and the proof mass layer 230.

[0024] One technique to bond all the wafer layers 210-230 together is by a process called direct bonding. Before bonding, the wafer layers 210-230 are preferably cleaned and activated. Activation is done by either chemical or plasma surface activation. The wafer layers 210-230 are properly aligned and coupled to each other. Van Der Waals forces will cause the layers 210-230 to bond to each other. Since the Van Der Waals forces are relatively weak, the wafer layers 210-230 may be annealed at an elevated temperature. This temperature depends on the activation process. Older processes used temperatures in excess of 1000⁰C. With newer plasma processes, 400⁰C may suffice. It can be envisioned that other methods or techniques can be used to bond the layers 210-230 together and achieve the same objective of the present invention.

[0025] FIG. 3 is an assembly drawing of the silicon accelerometer sensor 200 of

FIG. 2, according to one embodiment of the present invention. The assembly drawing shows the internal components of sensor 200. Contained within the proof mass layer 230 is a proof mass paddle 305 that may be coupled to the proof mass layer 230 by silicon hinges. On opposite sides of the paddle 305 are electrodes 310. FIG. 3 shows electrode 310 contained within the second guard layer 225. The first guard layer 220 also surrounds an electrode (not shown in the diagram) that is adjacent to the paddle 310 and is parallel to electrode 310. This configuration forms a capacitor between each electrode 310 and the paddle 305. In operation, the capacitance is used to determine the gap between the paddle 305 and each electrode 310.

[0026] FIGS. 4, 5 and 6 are the top, front and side views, respectively, of the silicon accelerometer sensor of FIG. 2, according to one embodiment of the present invention. FIG. 6 shows electrode 310 contained within the second guard layer 225, while electrode 610 is contained within the first guard layer 220. Electrodes 310 and 610 are parallel to one another and are adjacent to the paddle 305.

[0027] Typically, the wafer layers 210-230 are bonded in ambient class 10 air which contains approximately 20% oxygen and moisture of about 50% RH. When the bonded wafer layers 210-230 are annealed, the oxygen and water react with the silicon to form silicon oxide. This surface layer of silicon oxide is responsible for several performance problems, such as bias relaxation in the sensor 200, electrostatic forces forming between the paddle 305 and the electrodes 310 and 610, and bias turn-on to turn-on repeatability.

[0028] According to one embodiment of the present invention, to resolve these performance problems, the surface of paddle 305 and electrodes 310 and 610 are coated with a metal so that charges do not reside on these surfaces. Preferably, the metal on the silicon surface should not form a eutectic at the bond annealing temperature.

[0029] Referring to FIG. 7, the paddle 305 and electrodes 310 and 610 are coated with a metal layer 710 according to one embodiment of the present invention. The paddle 305 and electrodes 310 and 610 can be coated with a plurality of metal layers. FIG. 8 shows the paddle 305 and electrodes 310 and 610 are coated with a first metal layer 810 and a second metal layer 815 according to one embodiment of the present invention. Preferably, the outer metal layer should be inert of oxidation. The metal interdiffusion and the diffusion of silicon in metals during wafer bond annealing should preferably be minimized. Furthermore, the metal layer should have a high melting point to prevent microwelding from occurring at elevated temperatures, especially when the paddle 305 touches the lower electrode 310 for a long time in the off condition.

[0030] In one embodiment, Iridium (Ir) can be used when only one metal layer 710 is applied on the paddle 305 and electrodes 310 and 610. Iridium has an extremely high melting point (2719K/2446°C), and is therefore, resistant to microwelding of the paddle 305 to the electrodes 310 and 610. Iridium is a very hard and dense metal with a very low diffusion rate. These characteristics enable Iridium to form a single layer of good ohmic, low resistance contact between metal and silicon.

[0031] In another embodiment, the paddle 305 and electrodes 310 and 610 are coated with Chromium (Cr) and Platinum (Pt). Referring to FIG. 8, Chromium can be used as the first metal layer 810 and Platinum (Pt) can be used as the second metal layer 815. Preferably, the thickness of the Chromium layer 810 is about 200 A, and the thickness of the Platinum layer 815 is about 500A.

[0032] Both metals have a high melting point — Chromium has a melting point of

2180 K/1907°C, while the Platinum has a melting point of 2041.4 K/1768.3°C. Chromium oxidizes easily, but it does not react with the silicon wafer. Meanwhile, Platinum is corrosion resistant, but it forms an alloy with silicon at low temperatures. When used in combination, Chromium serves the purpose of isolating the Platinum from the silicon wafer, while the Platinum is used to cover the Chromium and prevent it from oxidizing.

[0033] It can be envisioned that other metals, individually or in combination, can be used to achieve the same objective of the present invention. For example, Tungsten (W) can be used as a first metal layer 810 like Chromium. Tungsten has the highest melting point of 3695K/3422°C, but it also oxidizes when exposed to air. Accordingly, Tungsten can be coated with a second metal layer 815 of Platinum to prevent it from oxidizing. Also, Iridium can be used in combination with Platinum, Chromium or Tungsten. Furthermore, the electrodes 310 and 610 can be coated with different metals than the paddle 305.

[0034] All other considerations aside, water vapor should preferably be excluded. The sensor 200 should operate down to -55°C. With gaps on the order of 2 microns, very low vapor pressure of water in the cavity can lead to micro dendritic crystals of water that interfere with the motion of the paddle 305. Therefore bond preparation by plasma activation of the surface may be used instead of wet chemical surface preparations. Plasma activation normally has the added benefit of achieving full bond strength at lower temperatures than wet processes. In addition, it is preferable to eliminate oxygen to prevent any possible oxidation of the metal surface, and thereby create an opportunity for charges to be trapped.

[0035] While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other changes, combinations, omissions, modifications and substitutions, in addition to those set forth in the above paragraphs, are possible. For example, the present invention can also be used for other MEMS devices to eliminate spurious charge effects. Those skilled in the art will appreciate that various adaptations and modifications of the just described preferred embodiment can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.

Claims

CLAIMS What Is Claimed Is:

1. In combination with a MEMS device having a top cover, a top electrode having a top and bottom surface below the top cover, a bottom electrode having a top and bottom surface below the top electrode, and a bottom cover below the bottom electrode, the improvement comprising:

a first metal layer on the bottom surface of the top electrode and on the top surface of the bottom electrode.

2. The MEMS device of Claim 1 further comprising a proof mass paddle between the top electrode and the bottom electrode, the proof mass paddle having a top and bottom surface covered with the first metal layer.

3. The MEMS device of Claim 1 wherein the first metal layer is Iridium.

4. The MEMS device of Claim 1 wherein the first metal layer is substantially inert to oxidation.

5. The MEMS device of Claim 1 wherein the first metal layer has a melting point higher than an annealing temperature.

6. The MEMS device of Claim 1 or 2 further comprising a second metal layer on top of the first metal layer.

7. The MEMS device of Claim 6 wherein the second metal layer is Platinum.

8. The MEMS device of Claim 6 wherein the second metal layer is Iridium.

9. The MEMS device of Claim 6 wherein the first metal layer is Chromium.

10. The MEMS device of Claim 6 wherein the First metal layer is Tungsten.

11. The MEMS device of Claim 6 wherein the second metal layer is substantially inert to oxidation.

12. A MEMS device configured to eliminate spurious charge effects, comprising:

a first electrode having a top and bottom surface;

a second electrode having a top and bottom surface;

a proof mass paddle having a top and bottom surface, wherein the top surface of the proof mass paddle is beneath the bottom surface of the first electrode and the bottom surface of the proof mass paddle is above the top surface of the second electrode;

a first metal layer on the top and bottom surfaces of the proof mass paddle;

a second metal layer on the bottom surface of the top electrode; and

a third metal layer on the top surface of the bottom electrode.

13. The MEMS device of Claim 12 wherein the first, second, or third metal layer are made of Iridium.

14. The MEMS device of Claim 12 wherein the first, second, or third metal layer are selected from a group consisting of metals substantially inert to oxidation and with a high melting point.

15. The MEMS device of Claim 12 further comprising at least one metal layer on top of at least one of the first, second, or third metal layers.

16. The MEMS device of Claim 12 further comprising a top cover above the first electrode and a bottom cover below the second electrode.

17. The MEMS device of Claim 12 further comprising a fourth metal layer covering the exterior of at least one of the first, second, or third metal layers.

18. The MEMS device of Claim 16 wherein the fourth metal layer is Platinum.

19. The MEMS device of Claim 16 wherein at least one of the first, second, or third metal layers is selected from a group consisting of Chromium, Tungsten, and Iridium.

20. A silicon accelerometer sensor configured to eliminate spurious charge effects, comprising:

a first electrode;

a second electrode parallel to the first electrode;

a proof mass paddle between the first electrode and the second electrode; and

a first metal layer on the proof mass paddle, on the top electrode, and on the bottom electrode, wherein the first metal layer is substantially inert to oxidation.

21. The silicon accelerometer sensor of Claim 20 further comprising:

a top cover above the first electrode;

a bottom cover below the second electrode;

a first guard below the top cover and configured to protect the first electrode from damage; and

a second guard above the bottom cover and configured to protect the second electrode from damage.

22. The silicon accelerometer sensor of Claim 20 wherein the first metal layer is Iridium.

23. The silicon accelerometer sensor of Claim 20 further comprising a second metal layer between the first metal layer and the proof mass paddle, the top electrode, and the bottom electrode.

24. The silicon accelerometer sensor of Claim 23 wherein the first metal layer is Platinum and the second metal layer is Chromium.

25. The silicon accelerometer sensor of Claim 23 wherein the first metal layer is Platinum and the second metal layer is Tungsten.

26. The silicon accelerometer sensor of Claim 23 wherein the first metal layer is selected from a group consisting of Iridium and Platinum.