WO2006125157A3 - Erasure generation in a forward-error-correcting communication system - Google Patents

Erasure generation in a forward-error-correcting communication system Download PDF

Info

Publication number
WO2006125157A3
WO2006125157A3 PCT/US2006/019456 US2006019456W WO2006125157A3 WO 2006125157 A3 WO2006125157 A3 WO 2006125157A3 US 2006019456 W US2006019456 W US 2006019456W WO 2006125157 A3 WO2006125157 A3 WO 2006125157A3
Authority
WO
WIPO (PCT)
Prior art keywords
error
memory
indicates
bit
address
Prior art date
Application number
PCT/US2006/019456
Other languages
French (fr)
Other versions
WO2006125157A2 (en
Inventor
Sharori Guo
Original Assignee
Telegent Systems Inc
Sharori Guo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telegent Systems Inc, Sharori Guo filed Critical Telegent Systems Inc
Publication of WO2006125157A2 publication Critical patent/WO2006125157A2/en
Publication of WO2006125157A3 publication Critical patent/WO2006125157A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Abstract

A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.
PCT/US2006/019456 2005-05-18 2006-05-18 Erasure generation in a forward-error-correcting communication system WO2006125157A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68219605P 2005-05-18 2005-05-18
US60/682,196 2005-05-18

Publications (2)

Publication Number Publication Date
WO2006125157A2 WO2006125157A2 (en) 2006-11-23
WO2006125157A3 true WO2006125157A3 (en) 2007-03-29

Family

ID=37054408

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/019456 WO2006125157A2 (en) 2005-05-18 2006-05-18 Erasure generation in a forward-error-correcting communication system

Country Status (1)

Country Link
WO (1) WO2006125157A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401910B (en) 2005-09-19 2013-07-11 St Ericsson Sa Apparatus and method for error correction in mobile wireless applications incorporating multi-level and adaptive erasure data
TWI415416B (en) * 2005-09-19 2013-11-11 St Ericsson Sa Apparatus and method for error correction in mobile wireless applications incorporating erasure table data
TWI430611B (en) 2005-09-19 2014-03-11 St Ericsson Sa Apparatus and method for error correction in mobile wireless applications incorporating correction bypass
KR20080084148A (en) * 2007-03-15 2008-09-19 삼성전자주식회사 Method and apparatus for decoding data in a receiver of digital broadcasting system
GB2519140B (en) 2013-10-11 2021-03-10 Advanced Risc Mach Ltd Cumulative error detection in data transmission

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EBU ET AL: "Digital Video Broadcasting (DVB)", ETSI DRAFTS, EUROPEAN TELECOMMUNICATIONS STANDARDS INSTITUTE, SOPHIA-ANTIPO, FR, September 2004 (2004-09-01), pages 1 - 82, XP002388738, ISSN: 0000-0002 *
JOKI H: "Modeling of DVB-H Link Layer", INTERNET CITATION, 10 May 2005 (2005-05-10), XP002389192, Retrieved from the Internet <URL:http://www.netlab.tkk.fi/opetus/s38310/04-05/Kalvot_04-05/Joki_100505.pp> [retrieved on 20060707] *

Also Published As

Publication number Publication date
WO2006125157A2 (en) 2006-11-23

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