WO2006123264A1

WO2006123264A1 - Clocking system using variable clock signal

Info

Publication number: WO2006123264A1
Application number: PCT/IB2006/051372
Authority: WO
Inventors: Gunnar Wetzker; Adrian W. Payne; Paul Van Zeijl
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-05-18
Filing date: 2006-05-02
Publication date: 2006-11-23

Abstract

The present invention relates to a clocking apparatus (10) and method for generating clock signals based on a variable frequency signal generated by a signal generating means (20) and controlled by a frequency control information such as a frequency control word (FCW). This information also enables to obtain, through storage means (60) storing for example a plurality of look-up tables, a processing control information provided to a digital signal processing means (50) which comprises elements sensitive to sampling frequency rate variations such as a phase shifter means (510), a filter means (520) with a configurable impulse response, and dependent on sampling frequency rate variations such as a re-sampler means (530). The variable frequency signal is used to clock an analog-to-digital converter or, as an alternative, a digital-to-analog converter at a respective sampling frequency. This sampling frequency is used by a clock generator means (30) to serve as a reference for all other clocking in the digital signal processing means (50). The re-sampler means (530) will be preferably located behind the filter means (520) and will comprise a digital oscillator (531) and a re-sampler (532) clocked by a clock signal based on said variable frequency signal and having its outgoing register clocked by a frequency generated by said digital oscillator (531).

Description

Clocking system using variable clock signal

The present invention relates to a clocking apparatus and methods for generating clock signals based on a variable frequency signal, in particular for a receiver system. The invention can be used in broadband wired or wireless transmission systems like Bluetooth of wireless local area networks. During recent years, analog-to-digital converters (ADCs) have been continuously improved and enabled highly digitized low-power system architectures, flexible multi-band systems being able to convert different kinds of signals and multi-channel systems being able to convert multiple signals of the same kind at the same instant.

These advances have been achieved due to improved signal-to-noise-ratios as well as higher sampling bandwidth. Due to the increased performance of the ADCs, jitter requirements on the sampling clock have been continuously tightened.

The required low-jitter clock signals - 7ps is considered to be a low-jitter signal for low-cost systems - can be generated by low-jitter clock generators. Typically, these blocks are costly in terms of area and power consumption. Many systems, including radio frequency (RF) transceivers, have low-jitter signal generators included for other purposes than clocking the ADC, e.g. mixing RF signals. These signal generators can be used to generate a low-jitter clock to clock the ADC as disclosed in the article "A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process", Proceedings, ISSCC, 2004. A disadvantage is that this alternative clock system may have a varying frequency depending on the operational requirements for this alternative signal generator. For example, in a RF transceiver, the signal generator may have to vary the RF channel.

Whereas for low variations of the clock frequency, timing and frequency synchronization blocks being part of the digital processing system at the output of the ADC might be able to cope with this additional signal uncertainty, the synchronization performance is however impacted by these additional errors. Furthermore, filtering tuned to the bandwidth of the processed signal becomes mismatched if the sampling frequency changes, since the bandwidth of the received signal is typically constant within one operation mode of the system (in case of a multi-mode system) whatever the sampling frequency is. In particular, if the change of the sampling frequency can be taken into account by design of a number of digital signal processing blocks, there are blocks where this is not possible, such as phase shifters, which can be used to shift the signal to a different frequency, and filters, which are tuned to the bandwidth of the received signal. Furthermore, it might be needed at a certain instant to cross the boundary to another clock domain since there might be system components, which rather require a constant sampling frequency clock than a low-jitter clock, such that re-sampling of the signal would be required.

It is therefore an object of the present invention to provide a clocking apparatus and method for generating clock signals based on a variable frequency signal, in particular for a receiver system, by means of which low-jitter requirements can be met as well as crossing of clock domains between, for example, a low-jitter clock domain and a clock domain requiring a constant sampling frequency can be easily accomplished. This object is achieved by a clocking apparatus as claimed in claim 1, a method as claimed in claims 13 and 14, and a computer program product as claimed in claim 19.

Accordingly, a variable frequency signal generated by a signal generating means is used to clock an analog-to-digital converter or a digital-to-analog converter at a sampling frequency. This sampling frequency is used by a clock generator means to serve as a reference for all other clocking in a digital signal processing means. Thereby, meta-stability of flip-flops between clock domains can be avoided. A processing control information provided to the digital signal processing means comprising elements sensitive to and dependent from variations of the sampling frequency rate is derived from the frequency control information used for controlling the variable frequency signal generated by a signal generating means. Thereby, no additional signal generating means is required and the elements of the digital signal processing means can be easily adapted to changes in the sampling frequency. The signal generating means may be provided by a low-jitter signal generator, which may be found as such in e.g. radio frequency (RF) transceivers. Thereby, the tightened low-jitter requirements on the sampling clock can be more easily met.

The processing control information may be provided by at least one storage means such as a read-only memory (ROM) or a random-access memory (RAM) in which a look-up table may be stored. Thereby, the processing control information may be modified or adapted in a simple way.

The digital signal processing means may comprise several elements sensitive to sampling frequency rate variations such as, at least, a phase shifter means and a filter means, and dependent on sampling frequency rate variations such as a re-sampler means for enabling crossing clock domains and thereby reducing buffering.

The filter means may comprise a selective filter with a configurable impulse response by changing the filter coefficients at each change of the sampling frequency or a combination of at least two of these selective filters, to thereby improve matching of the filtering operation.

The re-sampler means which may deliver a re-sampled digital signal, may be located behind the filter means to thereby allow a less complex step of re-sampling and an easy adaptation to constant sampling frequency rate clock domains without unnecessarily large buffering. Moreover, the re-sampler means may comprise a digital oscillator and a re- sampler clocked by a clock signal based on said variable frequency signal and having its outgoing register clocked by a frequency generated by said digital oscillator so as to avoid meta-stability issues and reduce the outgoing register area requirements, since the enable input is not required. Furthermore, the elements of the digital signal processing means sensitive to and dependent from sampling frequency rate variations may be individually controlled by a dedicated processing control information, such that it is possible to have several Program Control Words (PCWs) driven by a single FCW.

In the proposed method for generating clock signals based on a variable frequency signal, the step of re-sampling may be performed after the step of filtering.

The method steps may be produced by code means when run on a computer device. The computer program product may be downloaded from a network or may be stored on a computer readable medium such as an optical or magnetic disc. The invention as a computer program product may be run when an analog signal such as an analog RF signal is directly input to and sampled by a computer device where the computer program product is stored.

Further advantageous developments are defined in the dependent claims.

The present invention will be now described based on preferred embodiments with reference to the accompanying drawings in which:

Fig. 1 shows a schematic block diagram of a clocking apparatus according to a first preferred embodiment of the invention; Fig. 2 shows a schematic block diagram of signal generating means according to the first preferred embodiment of the invention;

Fig. 3 shows a schematic block diagram of filter means according to the first preferred embodiment of the invention; and

Fig. 4 shows a schematic block diagram of re-sampler means according to the first preferred embodiment of the invention.

In the following, the first preferred embodiment will be described in connection with a receiver system provided e.g. in a transceiver of a broadband wired or wireless transmission system.

In Fig. 1, a schematic block diagram of a clocking apparatus 10 according to the first preferred embodiment of the invention is shown, in which a frequency control information such as a frequency control word (FCW) is used to drive storage means 60 storing for example look-up-tables (LUTs) 610, 620, 630 to provide control information to the elements of the digital signal processing means 50 which are sensitive to sampling frequency rate variations, such as phase shifter means 510 and filter means 520, and also dependent on this sampling frequency such as re-sampler means 530. The clocking apparatus 10 is drawn for a complex signal processing system as it is often used in RF transceivers to process the intermediate frequency and baseband signals. The system is not restricted to two parallel signal branches. It can be equally used for one or more than two branches.

The FCW sets or adjusts the frequency of a variable frequency signal generated by a signal generating means 20 such as a signal source to produce a signal at frequency f, which is required to process the signals in the analog part of the system. As an example, the signal generating means 20 may be a local oscillator used for generating a mixing frequency in an RF part of the transceiver. From the frequency f, the required sampling signal at frequency f_s is generated, which clocks the analog-to-digital converter means 40 such as an ADC. The sampling frequency f_s of the ADC is then used by a clock generator means 30 to provide a reference for all other clocking in the digital signal processing means 50 which comprises decimator means 540 and interpolator means 550 in addition to the phase shifter means 510, the filter means 520 and the re-sampler means 530.

Fig. 2 shows a schematic block diagram of the signal generating means 20 used in the preferred embodiments of the invention. This can be a typical signal source such as disclosed in the PhD thesis entitled "Architectures for RF frequency synthesizers", C. S. Vaucher, Twente University, August 2001. The signal generating means 20, e.g. Phase- Locked Loop (PLL), comprises a reference signal source 210 such as an oscillator circuit, a phase frequency detector (PFD) 220, a charge pump 230, a loop filter 240 and a Voltage Controlled Oscillator (VCO) 250. The PLL generates a frequency synthesized by a fractional-N synthesizer while placing a fractional-N frequency divider 260 between the VCO 250 and the PFD 220. The output signal frequency synthesized by a fractional-N synthesizer and outputted from the VCO 250 is divided by an integer M such that the sampling frequency f_s is generated. The divisions by the integers M and N are controlled by the FCW which drives individual LUTs such as LUT D 270 and LUT E 280. Furthermore, the division by M has the advantage of reducing the phase noise gain by 20 log₁₀ M, and partially explains why the resulting signal at sampling frequency f_s is a low-jitter signal. By changing M, it is also possible to keep the interval [f_s_min, f_s_max] as small as possible.

The clock generator means 30 of Fig. 1 may be configured to derive all required system clocks (e.g. f_sl for the phase shifter means 510, f_S2 for the filter means 520, f_s3 for the re-sampler means 530) before re-sampling by dividing the sampling frequency f_s of the ADC by predetermined integer numbers. So, all the derived clocks are locked with f_s and meta-stability between clock domains can be avoided.

The sampling frequency rate of the digital signal outputted from the analog-to- digital converter means 40 is decimated by a factor of an integer K using decimator means 540 and then interpolated by a factor of an integer L using interpolator means 550. The decimation and interpolation operations, which are filtering operations well known by the person skilled in the art, are described for example in the book entitled "Multiraten- Signalverarbeitung", N. Fliege, Teubner, Stuttgart 1993. With regard to the design of the filter coefficients, it has to be noted that standard filter design procedures can be used as long as the filter design is accomplished for the lowest possible sampling frequency f_s.

Among the elements of the digital signal processing means 50 which are sensitive to sampling frequency rate variations, the phase shifter means 510 is associated with a required digital oscillator 511 to implement a predetermined frequency shift. A detailed example of such an element can be found for example in "A 540 Mhz 10 bit polar-to- cartesian converter", G. Gielis, R. van de Plassche, J. van Valburg, IEEE JSSC, vol. 26,

1991, pp. 1645-1650. The required LUT A 610 can be implemented as a read only memory (ROM) or a random access memory (RAM). Of course, this applies as well to the other LUTs mentioned herein. The programming for a constant frequency shift f_ΪF follows if G is the word length at the input of the phase shifter being able to resolve 360 degrees into 2^AG steps. The frequency values to program or set in the LUT A 610 are for example given by round (2^ΛG/(f_sl(FCW)/ fiF)).

An additional element sensitive to sampling frequency rate variations is the filter means 520. For signals with a bandwidth which is constant for all sampling frequencies, filters being matched to the signal bandwidth undergo a mismatch. If the filter is matched to the average of the minimum and the maximum sampling frequency, the mismatch increases with increased distance of the sampling frequency from the average f_S2_av = (f_S2_min + f_S2_max)/2. It is possible to take this into account by implementing a filter means 520 with a configurable impulse response, such that the filter means coefficients are changed with every change in sampling frequency. An example of such a system is given for example in "Computation sharing programmable FIR filter for low-power and high-performance applications", J. Park et al.. IEEE JSCC, vol. 39, no 2, 2004, pp. 348-357. In many cases, the coefficients will only change slightly. As a consequence the difference between the filter impulse response at f_S2_av, denoted by h_av(k), where k = 1, ..., P, and the maximum filter impulse response h_max(k) and the minimum impulse response h min(k) is small. Given that the relation h_diff(k) = h min(k) - h_av(k) = - (h max(k) - h_av(k)) approximately holds, it is possible in the preferred embodiments to implement two filter means 520 and to obtain a good approximation of the optimum filter impulse response by combining the outputs of two filter means 520. Fig. 3 depicts an example of this approach where RG, dsin and ds_out respectively designate register, digital signal input and digital signal output. If two filter means 520 are not enough, more different filter means 520 can be implemented and combined to improve the matching of the filtering operation. The actual combining ratio of the impulse responses is again determined by the FCW and the LUT B 620 which stores values covering a range from -1 to 1 mapped onto integer values.

The re-sampler means 530 which is represented in Fig. 1 is located after the filter means 520. Although it is also possible to place the step of re-sampling at an earlier point in the chain of the digital signal processing means 50, the step of re-sampling has the disadvantage to become more complex because accurate filtering has to be taken into account. In document US 6,774,835 Bl, a method has been described to achieve this for a fixed sampling frequency of a varying bandwidth input signal in an efficient way. The same concept can be applied here to achieve proper re-sampling for varying sampling frequencies of a fixed bandwidth signal. Nevertheless and in order to simplify the step of re-sampling as much as possible, the re-sampler means 530 used in the preferred embodiments can be preferably placed, such as drawn in Fig. 1, after all the filtering in the system has been accomplished and at a place in the system where the signal is over-sampled with regard to the bandwidth of the received signal. As a consequence, all elements before the re-sampling have to be able to cope with sampling frequency rate variations.

Fig. 4 shows a schematic block diagram of re-sampler means according to the preferred embodiments. The re-sampler means 530 comprises a digital oscillator 531 and a re-sampler 532. Since the step of re-sampling is performed after the step of filtering and the bandwidth of the signal is significantly smaller than the sampling frequency f_s, it is possible to implement the step of re-sampling in a way provided by using a sample-and-hold operation for interpolation. The digital oscillator 531 consists of an accumulator, which accumulates phase values l/f_s3 supplied or read from the LUT C 630 which stores integer values corresponding to the phase values of l/f_s3. These values can, for example, be obtained by round(l/f_s3-l MHz 2^AW), where W denotes the number of bits used for the resolution of the fractional part of l/f_s3-l MHz. If f_re is the reference frequency desired at the output of the re- sampler 532, the phase value l/f_s3 is accumulated until the cumulative sum exceeds l/f_re. In this case, the frequency f_out delivered by the digital oscillator 531 equals one. Still, it has to be decided which incoming sample has been the closest to the outgoing sample instant. This is decided based on the feedback result of the operation y = mod(x,l/f_re), where x represents the accumulated phase value. In case that y < l/f_re/2, the early sample of the input has to be taken and otherwise the late sample. This operation is organized by the control signal (ctrl) which is sent to a multiplexer (MUX) of the re-sampler 532. The outgoing digital signal to be re-sampled at f_re (dsr_out) is still clocked at f_s3, but the clocking of the outgoing register (RG) of the re-sampler 532 is controlled by f_out- This emulated clocking by f_out avoids meta- stability and simplifies the synthesis of such a circuit. Alternatively, clocking the outgoing register with f_out is also possible, which reduces the output register area requirements since the enable input (EN) is not required.

In alternative second embodiment, the invention can also be applied to a digital-to-analog (DAC) conversion if a high timing accuracy is required for a DAC. In this case, a digital receiver signal is first processed in a digital processing stage controlled by the processing control information which is derived from the FCW. Then, the processed digital signal is converted into an analog signal by the DAC at a sampling frequency derived from the variable frequency signal. The sampling frequency of the DAC may correspond to the sampling frequency of the ADC according to the first preferred embodiment if the digital signal processing means 50 is the same. Since all the DSP blocks behind a decimation or interpolation filters typically share the same clock until the next decimation or interpolation filters, the sampling frequency of the DAC may be therefore not identical to the sampling frequency of the ADC if for example the filters are made switchable so as to bypass them.

In summary, a clocking apparatus 10 and method have been described for generating clock signals based on a variable frequency signal generated by a signal generating means 20 and controlled by a frequency control information such as a frequency control word (FCW). This information also enables to obtain, through storage means 60 storing for example a plurality of look-up tables, a processing control information provided to a digital signal processing means 50 which comprises elements sensitive to sampling frequency rate variations such as a phase shifter means 510, a filter means 520 with a configurable impulse response, and dependent on sampling frequency rate variations such as a re-sampler means 530. The variable frequency signal is used to clock an analog-to-digital converter or, as an alternative, a digital-to-analog converter at a respective sampling frequency. This sampling frequency is used by a clock generator means 30 to serve as a reference for all other clocking in the digital signal processing means 50. The re-sampler means 530 will be preferably located behind the filter means 520 and will comprise a digital oscillator 531 and a re-sampler 532 clocked by a clock signal based on said variable frequency signal and having its outgoing register clocked by a frequency generated by said digital oscillator 531.

Finally but yet importantly, it is noted that the term "comprises" or "comprising" when used in the specification including the claims is intended to specify the presence of stated features, means, steps or components, but does not exclude the presence or addition of one or more other features, means, steps, components or group thereof. Further, the word "a" or "an" preceding an element in a claim does not exclude the presence of a plurality of such elements. Moreover, any reference sign does not limit the scope of the claims.

Claims

CLAIMS:

1. A clocking apparatus for generating clock signals for a receiver system, said apparatus comprising: signal generating means (20) for generating a variable frequency signal in response to a frequency control information; - clock generator means (30) for generating at least one clock signal derived from said variable frequency signal generated by said signal generating means (20); digital signal processing means (50) for processing a digital signal by using said clock signal and a processing control information derived from said frequency control information; and - converter means (40) for converting a received analog signal into said digital signal to be processed by said digital signal processing means (50) at a sampling frequency generated by said variable frequency signal, or for converting said digital signal being output from said digital signal processing means (50) into an analog output signal at a sampling frequency generated by said variable frequency signal.

2. A clocking apparatus according to claim 1, wherein said processing control information is provided by storage means (60).

3. A clocking apparatus according to claim 2, wherein said storage means (60) store at least one look-up table (610, 620, 630).

4. A clocking apparatus according to any one of claims 1 to 3, wherein said digital signal processing means (50) comprises at least one of phase shifter means (510) for implementing a frequency shift, filter means (520) with a configurable impulse response for selectively filtering said digital signal being processed by said digital signal processing means (50) by changing the coefficients of said filter means (520) at each change in sampling frequency based on said clock signal, and re-sampler means (530) for re-sampling said digital signal.

5. A clocking apparatus according to claim 4, wherein said digital signal to be re- sampled by said re-sampler means (530) is derived from the output of said filter means (520).

6. A clocking apparatus according to claim 5, wherein said phase shifter means (510) receives a first processing control information from said processing control information, said filter means (520) receives a second processing control information from said processing control information, and said re-sampler means (530) receives a third processing control information from said processing control information.

7. A clocking apparatus according to claim 6, wherein said second processing control information determines a combination of at least two of said filter means (520) for improving the matching of said filtering operation.

8. A clocking apparatus according to claim 6 or 7, wherein said third processing control information which controls said re-sampler means (530) comprises integer values corresponding to phase values of l/f_s3, wherein the frequency f_s3 is derived from said sampling frequency of said converter means (40).

9. A clocking apparatus according to claim 8, wherein said phase values can be obtained by round (l/f_s3.l MHz 2^AW), where W denotes the number of bits used for the resolution of the fractional part of l/f_s3.l MHz.

10. A clocking apparatus according to claim 9, wherein said phase values are accumulated until the cumulative sum x exceeds a reference period l/f_re desired at the output of said re-sampler means (530), such that a frequency f_out is generated and equals one, and a control signal is generated and equals one if mod(x,l/f_re) exceeds l/f_re/2.

11. A clocking apparatus according to claim 10, wherein said re-sampler means (530) comprises a digital oscillator (531) for providing said control signal and said frequency f_out, and a re-sampler (532) for outputting a digital signal re-sampled at said frequency f_re, said re-sampler being clocked by said frequency f_S3 and the register of said re-sampler (532) by said frequency f_out-

12. A clocking apparatus according to any one of the preceding claims, wherein said signal generating means (20) is a low-jitter signal generator.

13. A method for generating clock signals for a receiver system, said method comprising the steps of: a) generating a variable frequency signal in response to a frequency control information; b) generating at least one clock signal based on said variable frequency signal; c) converting a received analog signal into a digital signal by using a sampling frequency generated by said variable frequency signal; d) processing said digital signal by using said clock signal and a processing control information derived from said frequency control information.

14. A method for generating clock signals for a receiver system, said method comprising the steps of: a) generating a variable frequency signal in response to a frequency control information; b) generating at least one clock signal based on said variable frequency signal; c) processing a digital signal by using said clock signal and a processing control information derived from said frequency control information; d) converting the resulting digital signal into an analog output signal by using a sampling frequency generated by said variable frequency signal.

15. A method according to claim 13 or 14, wherein said step of processing said digital signal further comprises the steps of implementing a frequency shift, selectively filtering said digital signal by changing filter coefficients at each change in sampling frequency based on said clock signal, and re-sampling said digital signal.

16. A method according to claim 15, wherein said step of re-sampling is performed after said step of filtering.

17. A method according to any one of claims 13 to 16, wherein said processing control information is stored in at least one look-up table (610, 620, 630).

18. A method according to claim 17, wherein said step of re-sampling comprises the steps of providing a control signal and a frequency f_out with an integer value equals to 1 or 0, and controlling the outgoing digital signal to be re-sampled with said control signal and said frequency f_out.

19. A computer program product comprising code means adapted to produce the steps of any one of method claims 13 to 18 when run on a computer device.

20. A computer readable medium storing a computer program product as claimed in claim 19.