WO2006100368A1

WO2006100368A1 - Equipment, method, program and computer for complex code generation

Info

Publication number: WO2006100368A1
Application number: PCT/FR2006/000575
Authority: WO
Inventors: Eric Batut; Benoît MISCOPEIN; Jean Schwoerer
Original assignee: France Telecom
Priority date: 2005-03-22
Filing date: 2006-03-15
Publication date: 2006-09-28

Abstract

The invention relates to a piece of equipment that is used to generate a vector scrambling code (zn(i)), comprising two generators (Gx; Gy) which supply respective vector scrambling signals which are combined together with a pair of logical operators (011, 012) in order to produce a first scrambling code (zn(i)). The inventive equipment also comprises at least two delay lines (R1, R2) of the same depth and an additional pair of logical operators (021, 022), thereby enabling the production of a second scrambling code (zn+k(i)) belonging to the same code group as the first. The invention is particularly suitable for the transmission of digital data in accordance with the UMTS standard.

Description

EQUIPMENT, METHOD, PROGRAM, AND COMPUTER FOR COMPLEX CODE GENERATION.

The invention relates generally to signal processing techniques, in particular in the field of digital transmissions.

More specifically, the invention relates, according to a first aspect, to an equipment for generating at least a first complex code comprising first and second signal generators synchronized by clock signals and providing respective first and second signals. each of which comprises first and second components, and combinatorial means comprising at least a first pair of logic operators combining the first and second components of the first signal respectively with the first and second components of the second signal, and the second generator being triggered by to the first generator, with a delay of a first integer n of clock signals.

The technical field in which the invention finds its most advantageous application is that of digital communications in a cellular environment, and more specifically UMTS, a so-called "third generation" mobile telephony standard. The two modes of UMTS

(labeled FDD and TDD) use extensively two binary codes of ¹ families scrambling to ensure both

Orthogonality between transmissions at different rates and secondly a low inter-cell interference level. These codes are obtained non-trivially, and their generation represents a non-zero effort that must be minimized in order to facilitate their usage.

Detailed information is given in particular in the two references below:

[1] 3GPP: "Spreading and Modulation (FDD)", v5.0.0, March 2002, Technical Paper 3G TS 25.213, website: http: / /www.3gpp. org / ftp / Specs / archive / 25 series / 25.213 / 25213 -500. zip, and

[2] 3GPP: "Spreading and Modulation (TDD)", v5.0.0, March 2002, Technical Paper 3G TS 25.213, website: http: //www.3gpp. org / ftp / Specs / archive / 25 series / 25.223 / 25223 -500. zip.

The scrambling codes represent the second coding layer used by the UMTS standard. In the downward direction, these codes make it possible to attenuate the interference perceived by a terminal because of the base stations managing the adjacent cells. In the upstream direction, these codes allow the base station to effectively separate the signals transmitted by the different terminals it manages.

In practice, these codes are now scrambling ¹ grouped into 512 sets of 16 codes, each set i is composed of a primary code number 16. i, and 15 secondary codes numbered 16. i + j, where j is between 1 and 15. in a UMTS cell, the broadcast channels are encoded with the primary scrambling code of ^one of the code group used by the cell, while the traffic channels can be encoded with the primary code code group or with any of the codes of the same group of codes.

Figures 1 to 3 illustrate how a code is generated according to the state of the art, as known in particular from the first reference mentioned above. The number of the code to generate will be noted "n". Two binary sequences, denoted "x" and "y" and denominated "sequences of maximum length" are used. These sequences are generated as follows:

x (0) = 1 x (l) = x (2) = ... = x (16) = x (17) = 0 y (0) = y (l) = ... = y (16) = y (17) = 1, and x (i + 18) = x (i + 7) (+) x (i) y (i + 18) = y (i + 10) (+) y (i + 7) (+) y (i + 5) (+) y (i),

where (+) denotes the modulo 2 addition.

The sequence of GoId Z _n is defined by:

z _n (i) ≈ x (i + n) (+) y (i).

This binary sequence is converted into a real sequence by the following transformation:

Z _n (D = 1 - 2.z _n (i).

Finally, the complex scrambling code is obtained by:

S _n (D ≈Z _n (D + jZ _n (i + 131072).

Known equipment for generating a complex code z _n (i) typically comprises two signal generators, such as Gx (Figures 1 and 3) and Gy (Figures 2 and 3), synchronized by clock signals.

Each of the generators Gx and Gy comprises a shift register such as Mx and My, a loopback circuit such as Rx and Ry, and a logic circuit such as Lx and Ly.

The shift registers Mx and My of these generators Gx and Gy are initially loaded by the respective digital sequences x (1) a x (17) and y (1) to y (17) mentioned above.

These generators Gx and Gy provide respective signals, such that x (n + i) and y (i), each of which comprises two components, namely x ^ n + i) and x _Q (n + i) for the first signal scrambling x (n + i) and y (i), YQH) for the second scrambling signal ¹ y (i).

A pair of logical operators 011 and 012 (FIG. 3), consisting of XOR gates for modulo 2 addition, combine the first and second components X ₁ (n + 1) and x _Q (n + 1) of the first signal. x (n + i) respectively to the first and second components yi (i) and VQ (I) of the second signal y (i).

As is known to those skilled in the art, the operator 011 thus delivers the real part of the complex scrambling code, that is to say Z _n (i), while the operator 012 delivers the imaginary part of the code complex scrambling, that is to say Z _n (i + 131072).

As shown by the relationships mentioned above, it is necessary, during the initialization of the known equipment illustrated in FIG. 3, to rotate the generator Gx by itself a number of times equal to the number "n" of the code to generate, before triggering the generator Gy, the number n being a multiple of 16.

However, this shift significantly delays the availability of data concerning the code "n".

In the absence of a quick initialization technique of the code generator, it can therefore be quite expensive for a single piece of equipment to change the code to be generated repeatedly.

Apart from the duplication of generation means, there is currently no solution available to the problem of decoding traffic channels encoded not with the primary code of the cell but with a secondary code.

In particular, it is not realistic to reset the code generator so as to generate the primary code and then the secondary code for each block of data, taking into account the power consumption and the latency introduced by the reset time. of the Gx generator.

It is also not advisable, because of the relative ineffectiveness of this solution, to use a memory, which should be large enough, to store the entire primary code and the secondary codes that can be used by the cell.

In this context, the purpose of the invention is to propose means making it possible, with two generators such as Gx and Gy, to deliver at the same time the elements of the primary code of the cell and the elements of one of the secondary codes associated with the code. primary cell, that is to say belonging to the same group of codes.

For this purpose, the equipment of the invention, moreover, conforms to the generic definition given in the preamble above is essentially characterized in that the combinatorial means further comprise at least first and second delay lines of the same depth k where k is a second integer, and a second pair of logical operators, in which that the first delay line is arranged to delay the first complex code and provide a first delayed complex code, in that the second delay line is arranged to delay the second signal and to provide first and second components of a second delayed signal , and in that the second pair of logical operators combines the first and second components of the first signal respectively with the first and second components of the second delayed signal, the second pair of logical operators thus providing a second complex code delayed and synchronous with the first delayed complex code.

Preferably, this equipment further comprises a truncation module capable of generating first and second definitive complex codes by truncating the first and second delayed complex codes by their first k values.

The invention also relates to a method for generating at least a first complex code, this method comprising an operation consisting of generating, at a given cadence by clock signals, first and second signals, each of which presents first and second signals. components, and the second of which presents on the first a delay equal to a first integer number n of clock signals, and to generate the first complex code by combining the homologous components of the first and second signals, this method being characterized in that it further comprises at least the operations of generating a first delayed complex code by delaying the first complex code of k clock signals, where k is an integer, generating a second delayed signal by delaying k signals of clock the second signal, and combining the homologous components of the first signal and the delayed second signal, this combination providing a second delayed complex code synchronous with the first delayed complex code. Preferably, this method further comprises an operation of generating first and second definitive complex codes by truncating the first and second delayed complex codes by their first k values. The invention also relates to - a computer program, this program being characterized in that it comprises own software modules, when loaded on a computer, to implement the operations of the method as previously defined. The invention finally relates to a recording medium, readable by a computer, on which is recorded the previously defined computer program.

Other characteristics and advantages of the invention will emerge clearly from the description which is given hereinafter, by way of indication and in no way limitative, with reference to the appended drawings, in which:

FIG. 1 is a diagram of a first known signal generator;

FIG. 2 is a diagram of a second known signal generator; Figure 3 is a diagram of a known equipment, including using the first and second known generators, and providing a first complex code; and - Figure 4 is a diagram of an equipment according to the invention, which uses in particular the first and second generators known to provide two complex codes belonging to the same group of codes.

As will be appreciated by those skilled in the art, the Gx and Gy generators and the logic operators 011 and 012 are used in the invention as they were in the prior art, and therefore will not be described again.

In addition to these known components, the equipment of the invention comprises at least two delay lines R1 and R2 of the same depth k and a second pair of logic operators 021 and 022.

The number k is an integer here less than the number n of the first complex scrambling code, and even in this case between 1 and 15, inclusive. The first delay line R1 is arranged to receive and delay the first complex code Z _n (i) delivered by the known equipment of FIG. 3, and to provide a first delayed complex code z _n (ik).

The second delay line R2 is arranged to receive and delay the second signal y (i), and to provide the real and imaginary components, yi (ik) and y _Q (ik), of a second delayed signal y (ik). .

The second pair of logic operators 021 and 022 has the function of combining the real and imaginary components, x _x (n + i) and x _Q (n + i), of the first signal x (n + 1) respectively to the actual and imaginary, Y ₁ (I-Ic) and y _Q (ik), of the second delayed signal y (ik).

Under these conditions, the second pair of logical operators 021 and 022 provides a second delayed complex code Z _{n +} ((ik) which belongs to the same set of codes as the first delayed complex code z _n (ik), and which is synchronous with him .

In fact, the first and second complex delayed codes z _n (ik) and z _{n + k} (ik) are not exploitable from the beginning of their production.

To produce the first and second definitive complex codes z _n (i) and z _{n + k} (i), the equipment of

The invention preferably comprises a truncation module Tk whose function is to truncate the first and second delayed complex codes z _n (ik) and z _{n + k} (ik) of their k first values.

The module Tk represents, conceptually, a line advancing the data of k positions. In practice, this module consists of a counter that transmits its inputs to its outputs only after k occurrences of the event "arrival of data inputs".

Noting generically Xi (i) and yi (i) the direct outputs of the two shift registers Mx and My, involved in the calculation of the real part of the elements of the primary code, and Xς (i) = X _x (i +131072) and

YQ (i) = yi (i + 131072) the secondary outputs of the same registers, involved in the computation of the imaginary part of the elements of the primary code, the generation equations of the scrambling codes give, for the elements of the primary code n (n is a multiple of 16): S _n (D = Z _n (i) + j _n .Z (i + 131072) = (1-2.Z _n (D) + j • (1- 2.z _n (i + 131072)),

with i ranging from 0 to 38399 inclusive, so that:

S _n (D = (1-2. (Xi (n + i) (+) Yi (D)) + j. (1-2. (X _Q (n + i) (+)

with i between 0 and 38399, terminals included.

The elements of the secondary code n + k (with k between 1 and 15, including terminals) are given by:

S _{n + k} (i) = (1-2. (Xi (n + k + i) (+) Yi (i))) + j. (1-2. (X _Q (n + k + i)

with i between 0 and 38399, terminals included.

It is found that the required values of the register My for the production of the secondary code n + k are the same as for the primary code n, while an offset of k positions appears between the required values of the register Mx for the calculation of S _n (i) and those required for the calculation of S _{n +} k (D • It is to obtain this shift that the delay line R2 delays k clock cycles the outputs γi (i) and y _Q (i) of the generator Gy.

Given this delay, it is however necessary to also delay k clock cycles the elements of S _n (i), so that they are made available at the same time as the elements of

S _{n +} k (D, this delay being introduced by the delay line Rl.

Finally, at the output of the equipment, the first k output values of S _n (i) and S _{n +} k (i) / which correspond to erroneous values resulting from the filling of the delay lines R 1 and R2, this operation being performed by the module Tk.

The illustrated equipment can be realized by a specific hardware circuit.

It can nevertheless also be constituted by a computer on which is loaded a computer program comprising software modules adapted to implement the previously described operations.

Moreover, by processing the outputs of the generators Gx and Gy by delay lines such that R1 'and R2' homologous to R1 and R2 but causing a delay k 'different from k, these delay lines being associated with operators 021' and 022 'and a truncation module Tk', respectively homologous to 021, 022, and

Tk, it is possible to generate other scrambling codes with the same generators Gx and Gy.

The invention therefore provides a technique for simultaneous generation of a primary scrambling code and one or more secondary scrambling codes belonging to the same code group as the primary code. It then becomes possible to decode both broadcast data encoded by the base station with the primary code, and traffic data possibly encoded by the base station with a secondary code, and that with equipment very slightly modified by to its current form, eliminating the need for costly duplication of the code generation device, or an even more expensive succession of resets of a single generator to generate the two codes alternately.

Claims

CLAIMS.

Apparatus for generating at least a first complex code (z _n (i)) comprising first and second signal generators (Gx; Gy) synchronized by clock signals and providing respective first and second signals (x (n + i) y (i)) each of which comprises first and second components (x (n + i), x _Q (n + i) y (i) YQ (I)) / ^e t means combinational devices comprising at least a first pair of logical operators (011, 012) combining the first and second components (X ₁ (n + 1), x _Q (n + 1)) of the first signal (x (n + i)) respectively to the first and second components (yi (i), YQ (I)) of the second signal (y (i)), and the second generator (Gy) being triggered, with respect to the first generator (Gx), with a delay of a first integer number (n) of clock signals, characterized in that the combinational means further comprise at least first and second delay lines (R1, R2) of the same depth k where k is a second number integer, and a second pair of logical operators (021, 022), in that the first delay line (R1) is arranged to delay the first complex code (z _n (i)) and provide a first delayed complex code ( z _n (ik)), in that the second delay line (R2) is arranged to delay the second signal (y (i)) and to provide first and second components (yi (ik), y _Q (ik)) a second delayed signal (y (ik)), and in that the second pair of logical operators (021, 022) combines the first and second components (x _r (n + i), XQ (n + i) ) of the first signal (x (n + i)) respectively to the first and second components (yi (ik), y _Q (ik)) of the second delayed signal (y (ik)), the second pair of logical operators (021, 022) thus providing a second delayed complex code (z _{n +} k (ik)) synchronous with the first delayed complex code (z _n (ik) ).

2. Equipment according to claim 1, characterized in that it further comprises a truncation module

(Tk) capable of generating definitive first and second complex codes (z _n (i); z _{n +} k (i)) by truncating the first and second delayed complex codes (z _n (ik); z _{n + k} (ik) ) of their first k values.

3. Equipment according to claim 1 or 2, characterized in that each generator (Gx; Gy) comprises a shift register (Mx; My), a loopback circuit

(Rx; Ry) and a logic circuit (Lx; Ly), the shift registers (Mx; My) of the generators (Gx; Gy) being loaded by respective initial digital sequences.

4. A method of generating at least a first complex code (z _n (i)), said method comprising an operation of generating, at a given cadence by clock signals, first and second signals

(x (n + i); y (i)) each of which has first and second components (xχ (n + 1), x _Q (n + 1); yi (i), yς (i)), and the second presents on the first a delay equal to a first integer number (n) of clock signals, and to generate the first complex code (z _n (i)) by combining the homologous components (xi (n + i), yi (i); x _Q (n + 1); y _Q (i)) of the first and second signals (x (n + 1); y (i)), characterized in that it further comprises at least operations of generating a first delayed complex code (z _n (ik)) by delaying the first complex code

(z _n (i)) of k clock signals, where k is an integer, generating a second delayed signal (y (ik)) by delaying of k clock signals the second signal (y (i)), and to combine the homologous components (X ₁ (n + 1), yi (ik); x _Q (n + 1); y _Q (ik)) the first signal (x (n + i)) and the delayed second signal (y (ik)), this combination providing a delayed complex second code (z _{n + k} (ik)) synchronous with the first code delayed complex (z _n (i-k)).

5. Generation method according to claim 4, characterized in that it further comprises an operation of generating first and second definitive complex codes (z _n (i); z _{n +} k (i)) by truncating the first and second second delayed complex codes (z _n (ik); Z _{n + k} (ik)) of their first k values.

Computer program, characterized in that it comprises own software modules, when this program is loaded on a computer, to implement the operations defined by any one of claims 4 and 5.

7. A computer-readable recording medium on which the computer program according to claim 6 is recorded.