WO2006082538A1 - Data processing system and method for accessing an electronic resource - Google Patents

Data processing system and method for accessing an electronic resource Download PDF

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Publication number
WO2006082538A1
WO2006082538A1 PCT/IB2006/050253 IB2006050253W WO2006082538A1 WO 2006082538 A1 WO2006082538 A1 WO 2006082538A1 IB 2006050253 W IB2006050253 W IB 2006050253W WO 2006082538 A1 WO2006082538 A1 WO 2006082538A1
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WO
WIPO (PCT)
Prior art keywords
interrupt
unit
processing unit
cpu
central processing
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PCT/IB2006/050253
Other languages
French (fr)
Inventor
Anton P. Kostelijk
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Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006082538A1 publication Critical patent/WO2006082538A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Definitions

  • the invention relates to a data processing system including at least one central processing unit, at least one interrupt generating unit and an arbitration unit.
  • the arbitration unit is provided to control access of the central processing unit to a shared electronic resource, in particular to a bus or a memory.
  • the invention is also related to a method of accessing a shared electronic resource via an arbitration unit.
  • the invention relates to a method for designing an electronic circuitry, wherein the electronic circuitry comprises a central processing unit for processing software instructions, at least one interrupt generating unit and an arbitration unit.
  • the invention relates to the use of an interrupt signal.
  • the invention relates to an electronic device having electronic circuitry, the electronic circuitry comprising at least one central processing unit, at least one interrupt generating unit, an arbitration unit controlling access of the central processing unit to an electronic resource.
  • Data processing systems or electronic devices usually comprise a central processing unit to run software routines. They comprise various kinds of additional hardware processing units for different kinds of special or dedicated purposes as well as memories. Processing units and memories are usually connected by busses or other kinds of dedicated wires or wiring. An interrupt (sometimes also called “an exception") usually forces a central processing unit to run a predetermined software interrupt routine instead of continuing with its processing. Hardware processing units may use interrupt lines to transmit interrupts. Interrupt controllers are often provided to organize multiple interrupts originating from multiple components. Arbitration units, such as bus controllers or memory controllers, handle accesses to an electronic resource, as e.g. to other processing units or controllers, to a memory, or to a bus in general to link various components. The access to the resource is then based on bus and memory arbitration using budgets like time slots or priorities or the like. The access arbitration is generally considered as an important issue as the speeds of all processing units are highly dependent on the way access is controlled.
  • a network device driver performing initial IP (internet protocol) packet processing within high priority hardware interrupt service routine is disclosed.
  • a network device such as an a-synchronous transfer method (ATM) device, transmits an interrupt to a central processing unit.
  • the hardware interrupt generates a put information for the packet which is then retrieved and utilized by the software interrupt to process the packet. Instead of processing the whole packet at the respective priority level of a hardware interrupt, processing priority is lowered and passed to a low priority software interrupt service routine to allow processing of other packets.
  • ATM a-synchronous transfer method
  • US 2003/0074508 relates to configurable prioritization of core-generated interrupts.
  • a method and an apparatus are disclosed for generating an interrupt vector associated with either core or off-core-generated interrupts.
  • the apparatus includes a priority encoder that sorts all of the received interrupts whether on-core or off-core, according to their priority, utilizing the programmed interrupt priority levels.
  • Use of the priority encoder and vector generator allows a processing system to programmably specify how core-generated interrupts are to be prioritized against external interrupts.
  • US 2002/0166018 discloses a multiprocessor interrupt handling system.
  • the interrupt handling system permits the interrupts generated by one or more hardware devices to be routed and prioritized dynamically.
  • the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level.
  • US 5,070,447 relates to an interrupt circuit and an interrupt processing method for microcomputers.
  • the interrupt circuit provides a first priority assignment control circuit and a second priority assignment control circuit.
  • the data processing system comprises a central processing unit for processing a software routine, at least one interrupt generating unit, an electronic resource, in particular a bus or a memory, and an arbitration unit for controlling access of the at least one central processing unit to the electronic resource.
  • An interrupt generating unit is coupled to the central processing unit and the arbitration unit to signal the interrupt signal to the central processing unit and the arbitration unit.
  • Central processing units with integrated memories such as caches rendered processing of software routines less dependent on access to respective resources, but specific software subroutines, in particular interrupt routines, are more dependent on access rights to electronic resources, e.g. busses or memories, because the code or the data is not likely to be in cache. So, the central processing units with internal memory, such as caches, resulted in interrupt routines being executed even slower than the rest of the software.
  • the arbitration unit is prompted to raise the central processing unit's access rights to the electronic resource when the central processing unit is processing a software routine in response to the interrupt signal.
  • a data processing system having the mentioned configuration, is adapted to signal the interrupt signal also to the arbitration unit, although the signal was usually intended for the central processing unit.
  • the arbitration unit raises the access rights of the central processing unit. If a software routine is processed in the central processing unit in response to the interrupt signal, the central processing unit may require access to an electronic resource that is controlled by the arbitration unit. The central processing unit will then have boosted access to the electronic resource via the arbitration unit.
  • the at least one interrupt generating unit generates an interrupt and transmits the interrupt directly (via dedicated lines) or indirectly (e.g. via an interrupt controller) to the central processing unit.
  • the interrupt signal prompts the central processing unit to cease the current processing, and to branch or to jump to a specific subroutine, which is dedicated to the interrupt signal. Simultaneously, the interrupt signal is transferred directly (via dedicated lines) or signaled indirectly (e.g. via an interrupt controller) to the arbitration unit. This way, by use of the same or at least equivalent signals, the arbitration unit is informed that the central processing unit should have raised access rights to the shared resource. The arbitration unit maintains raised access rights as long as indicated by the interrupt signal.
  • the lines to be used to transmit the respective signals to the central processing unit and to the arbitration unit may be dedicated wires which are connected to any specific input of the central processing unit and the arbitration unit.
  • the interrupt lines may also be part of a bus, in particular a bus line or a multi purpose line that is used to transmit the interrupt signal to the arbitration unit and to the central processing unit. Accordingly, the central processing unit will be able to access the shared electronic resource faster, to retrieve, transmit or exchange necessary information with the shared resource, and to complete the software subroutine in a shorter time. Moreover, the whole system benefits from faster execution of interrupt software routines, since in electronic devices, software interrupt routines are used to control hardware processing. When a software routine is delayed, the hardware processing can be delayed as well.
  • the data system according to the present invention may include one or a plurality of central processing units, wherein each of the central processing units may have raised access rights to a shared resource, while processing a software routine in response to the interrupt signal.
  • an interrupt controller is provided.
  • the at least one interrupt generating unit is coupled to the central processing unit and the arbitration unit via an interrupt controller for receiving, for controlling and for signaling the interrupt signal to the central processing unit and to the arbitration unit. Accordingly, the at least one interrupt generating unit is not directly connected to the central processing unit or to the arbitration unit.
  • the interrupt controller is dedicated to organize and process a plurality of interrupts of one or more interrupt generating units. Each of the interrupt generating units can send an interrupt signal to the arbitration unit and to the central processing unit via the interrupt controller to impose a superior access right for the central processing unit. This way, the central processing unit is enabled to access the shared resource with a higher priority in order to perform the respective subroutines faster.
  • one or more interrupt generating units generate a plurality of interrupt signals and the interrupt controller is further adapted to select an interrupt from the plurality of interrupts and to decide whether to signal the interrupt signal to the arbitration unit.
  • the interrupt controller includes a selection mechanism, allowing the interrupt controller to associate specific interrupts or sets of interrupts with an information indicating whether the interrupt or the group of interrupts has to be signaled also to the arbitration unit.
  • the selection mechanism may be flexibly programmed into the interrupt controller.
  • the data processing system is flexible to give raised access to the central processing unit with respect to only a selection of interrupt signals.
  • At least one interrupt line is coupled to the interrupt controller, the central processing unit, and the arbitration unit.
  • the interrupt controller, the arbitration unit, and the first central processing unit are directly connected via one single wire.
  • the hard wired connection allows direct transmission of the interrupt signal to both the central processing and the arbitration unit.
  • At least one interrupt line is coupled to the at least one interrupt generating unit, the at least one central processing unit, and the arbitration unit for signaling the interrupt signal to the central processing unit and to the arbitration unit. If no interrupt controller is needed, a direct electrical connection can be arranged between the interrupt generating unit, the central processing unit and the arbitration unit.
  • At least one interrupt line is coupled to the interrupt controller and to the central processing unit for transmitting the interrupt signal, and to at least one second line is coupled to the interrupt controller and the arbitration unit for signaling the interrupt signal to the arbitration unit.
  • the invention is also related to an electronic device having electronic circuitry, the circuitry comprising a central processing unit for processing a software routine, at least one interrupt generating unit for generating an interrupt signal, an electronic resource, in particular a bus or a memory, and an arbitration unit for controlling access of at least the central processing unit to the electronic resource.
  • the interrupt generating unit is coupled to the central processing unit and the arbitration unit to signal the interrupt signal to the central processing unit and to the arbitration unit in order to prompt the arbitration unit to raise the central processing unit's access rights to the electronic resource when the central processing unit is processing a software routine in response to the interrupt signal.
  • it is envisaged to incorporate an electronic circuitry having the above features for example on at least one single chip.
  • the invention is also related to a method of accessing an electronic resource within a data processing environment via an arbitration unit, in particular a memory controller or a bus controller, controlling access of a central processing unit to the electronic resource.
  • the method comprises the steps of generating at least one interrupt signal, signaling the interrupt signal to the arbitration unit and the central processing unit, processing software instructions in response to the hardware interrupt in the central processing unit, and raising the central processing unit's access rights to the electronic resource in the arbitration unit in response to the transferred interrupt signal while the central processing unit is processing a software routine in response to the interrupt signal.
  • the step of signaling the interrupt signal to the central processing unit and the arbitration unit comprises the steps of signaling the interrupt signal to an interrupt controller, wherein the interrupt controller signals the interrupt signal to the central processing unit, and the arbitration unit.
  • the step of processing instructions in the central processing unit in response to the hardware interrupt includes the step of processing at least one specific software subroutine in response to the hardware interrupt, and the central processing unit is granted higher access rights to the electronic resource by the arbitration unit while the central processing unit is processing the specific software subroutine.
  • the software subroutine processed in the central processing unit in response to the interrupt is an interrupt service subroutine, and the central processing unit is granted access by the arbitration unit when processing the interrupt subroutine. Accordingly, it is possible to boost the software processing by raising the access rights of the central processing unit at the arbitration unit (e.g. memory and/or bus arbiters). This is particularly advantageous during an interrupt routine that has to be executed faster than other subroutines.
  • the interrupt generating unit affects the priority or budget assigned to the central processing unit's access.
  • the central processing unit has a standard access right, whereas during an interrupt, it is given more rights (e.g. priority, budgets). Access to the electronic resource may occur only once or several times during the interrupt subroutine. Consequently, the hardware processing can continue earlier, whereas the central processing unit is not given high access rights continuously.
  • the invention also relates to a method for designing electronic circuitry, wherein the electronic circuitry comprises at least one central processing unit, at least one interrupt generating unit and an arbitration unit.
  • the arbitration unit is dedicated to control access of the at least one central processing unit to an electronic resource.
  • the method comprises the step of coupling at least one interrupt generating unit, at least one central processing unit, and the arbitration unit to signal an interrupt signal from the interrupt generating unit to the central processing unit and the arbitration unit in order to prompt the arbitration unit to raise the central processing unit's access rights, when the central processing unit is processing a software routine in response to the interrupt signal.
  • the interrupt generation unit is coupled to the central processing unit, and the arbitration unit for the specific purpose to signal the interrupt signal to both, the central processing unit and the arbitration unit.
  • the invention relates also to a use of an interrupt signal in a data processing environment to raise access rights of at least one central processing unit to an electronic resource, in particular to a bus or a memory, the access being controlled by an arbitration unit.
  • the use of the interrupt signal includes the steps of generating an interrupt signal, signaling the interrupt signal to the arbitration unit and the central processing unit, processing software instructions in response to the interrupt signal in the central processing unit, raising the central processing unit's access rights to the electronic resource while the central processing unit is processing a software routine in response to the interrupt signal.
  • a hardware interrupt it is possible to select a specific software routine or subroutine, and to link an improved access to a shared electronic resource with an interrupt service routine.
  • the specific hardware interrupt is signaled to the arbitration unit to prompt the arbitration unit to let the central processing unit have access to the electronic resource.
  • This can speed up software processing of the central processing unit, but also of the whole data processing system.
  • the invention is based on the idea to boost the software interrupt routine by raising the access rights of a processing unit, in particular of a central processing unit, in an arbiter (i.e. an arbitration unit) during a routine only.
  • the object is solved for example by connecting hardware interrupt lines to the bus- and/or memory controllers (i.e. to the arbitration units), thus allowing the arbiters to affect e.g. the priority and/or budget assigned to the central processing unit's access.
  • the central processing unit Before and after the interrupt, the central processing unit has a standard access right, whereas during an interrupt it is given more rights (e.g. priority and/or budgets). This way, the hardware processing can continue earlier, whereas the central processing unit is not given high access rights continuously.
  • an arbitration unit to grant access to a central processing unit.
  • the signal to be sent to the arbitration unit in order to grant the central processing unit raised access rights to the shared electronic resource (i.e. e.g. access to a bus or a memory) is generated by an interrupt generating unit, which may be any kind of hardware unit, that has provisions to generate an interrupt signal. This way, not the central processing unit itself, but another second processing prompts the arbitration unit to grant improved access to the central processing unit.
  • Fig. 1 shows a block diagram of an electronic circuitry according to a first embodiment
  • Fig. 2 shows a block diagram of an electronic circuitry according to a second embodiment
  • Fig. 3 shows a block diagram of an electronic circuitry according to a third embodiment.
  • Fig. 1 shows a block diagram of an electronic circuitry according to a first embodiment of the invention that can be part of a data processing system or an electronic device.
  • a central processing unit CPU is connected via a bus or an equivalent connection CPUAU to an arbitration unit AU.
  • the arbitration unit AU is preferably a bus controller, a memory controller, a bus arbiter or a memory arbiter.
  • An interrupt generating unit PUl e.g. a hardware processing device, is connected via a second connection PUlAU to the arbitration unit AU.
  • the arbitration unit AU controls access to an electronic resource RES.
  • the central processing unit CPU and the interrupt generating unit PUl are further connected to each other via an interrupt line IL.
  • the interrupt line IL connects at least an input of the central processing unit CPU and an output of the interrupt generating unit PUl . Further, the interrupt line IL is connected to the arbitration unit AU, i.e. to an input of the arbitration unit AU.
  • Fig. 1 it is possible to process instructions, i.e. a software routine, faster in the central processing unit CPU.
  • the software routine enters into a subroutine, into an interrupt subroutine or any other sequence of instructions in response to an interrupt (hardware interrupt)
  • the central processing unit CPU needs to access the shared electronic resource RES.
  • the electronic resource RES is for example a memory, a bus, another processing unit or the like.
  • the shared electronic resources are accessible via the arbitration unit AU.
  • the interrupt generating unit PUl sends an interrupt signal over the interrupt line IL.
  • the central processing unit CPU is prompted to process a specific subroutine, and jumps to the respective internal address.
  • the arbitration unit AU receives the hardware interrupt signal from the interrupt generating unit PUl. Accordingly, the arbitration unit AU raises the access rights of the central processing unit CPU to the resource RES. Access to the resource RES occurs via the bus CPUAU connecting the central processing unit CPU and the arbitration unit AU.
  • the interrupt generating unit PUl may access the resource RES via the connection PUlAU and via the arbitration unit AU.
  • the configuration in Fig. 1 shows also a particular use of an interrupt signal.
  • an interrupt signal is transmitted over the interrupt line IL to the central processing unit CPU.
  • the central processing unit enters an interrupt service routine.
  • the interrupt signal is also used to indicate via interrupt line IL an urgent request to the arbitration unit AU for an access of the central processing unit CPU to the resource RES.
  • the interrupt subroutines processed in the central processing unit CPU in response to the interrupt signal profit from an enhanced access to the resource RES.
  • Faster access for specific subroutines improves the overall performance of the system and boosts the software interrupt routine processing by raising the access rights of the central processing unit in the arbitration unit (e.g. memory and/or bus arbiters). This way, it is particularly avoided that the access rights of the central processing unit CPU are unaware of whether an interrupt routine or anything else is performed.
  • the interrupt routine is executed faster than other portions of the software, which need access to the resource RES. In particular in case the central processing unit CPU has internal memory, such as cache, the interrupt routine may be executed faster than the rest of the software that needs access to the resource RES.
  • Fig. 2 shows a block diagram of an electronic circuitry according to a second embodiment of the present invention.
  • the central processing unit CPU is connected to an arbitration unit AU via a bus CPUAU.
  • a first interrupt generating unit PUl e.g. a hardware processing device, is connected to the arbitration unit AU via a bus PUlAU.
  • a second interrupt generating unit PU2 is connected to the arbitration unit AU via a bus PU2AU.
  • the arbitration unit AU controls access to the electronic resource RES.
  • the first interrupt generating unit PUl and the second interrupt generating unit PU2 are connected to the interrupt controller IC via two signal lines SLl, SL2, respectively.
  • the interrupt line IL is connected to the central processing unit CPU, the interrupt controller IC and the arbitration unit AU.
  • the interrupt line IL allows the interrupt controller IC to send an interrupt to the arbitration unit AU and the central processing unit CPU.
  • the central processing unit CPU enters into a software subroutine or an interrupt routine, that requires an access to the electronic resource RES.
  • the arbitration unit AU gives access to the resource RES, but only to the central processing unit CPU. Access occurs via the bus CPUAU between the central processing unit CPU and the arbitration unit AU. If the interrupt line IL does not indicate a request to access the electronic resource RES, the first interrupt generating unit PUl and the second interrupt generating unit PU2 can access the resource RES via the arbitration unit AU, by use of the busses PUlAU and PU2AU, respectively. PUlAU and PU2AU can be distinct or identical busses. The central processing unit CPU may also share the same bus.
  • interrupts of both interrupt generating units PUl, PU2 are controlled by one interrupt controller IC.
  • the first and second interrupt generating units PUl, PU2 indicate via the signal lines SLl and SL2 to the interrupt controller IC that the central processing unit CPU should execute a certain subroutine.
  • the interrupt controller transmits a corresponding interrupt signal over the line IL. Accordingly, the central processing unit CPU starts the respective subroutine triggered by the interrupt.
  • the interrupt signal is also signaled to the arbitration unit via interrupt line IL. In response to the interrupt signal, the arbitration unit AU gives higher access rights to the central processing unit CPU.
  • first interrupt generating unit PUl and the second interrupt generating unit PU2 need also access to the shared resource, they have to wait until the central processing unit CPU has finished the subroutine (interrupt service routine) or the access to the electronic resource RES, before they are allowed to access the electronic resource RES.
  • the interrupt line IL and the method of accessing the resource RES via the arbitration unit AU with respect to software subroutines, the same considerations apply, as set out with respect to the first embodiment of Fig. 1.
  • Fig. 3 shows a block diagram of an electronic circuitry according to a third embodiment of the present invention.
  • the interrupt line IL is only connected between the central processing unit CPU and the interrupt controller IC.
  • the interrupt controller IC is connected via a dedicated line ICAU to the arbitration unit AU.
  • the first interrupt generating unit PUl or the second interrupt generating unit PU2 indicate via the signal lines SLl or SL2, respectively, that the central processing unit CPU has to carry out a specific interrupt service routine.
  • the interrupt controller IC transmits the interrupt signal via interrupt line IL to the central processing unit CPU, which in response branches to the respective interrupt service routine.
  • the interrupt controller also indicates via the line ICAU to the arbitration unit AU that the central processing unit CPU has to get raised access rights to the resource RES via the bus CPUAU.
  • the interrupt controller IC controls the interrupts from the first interrupt generating unit PUl and the second interrupt generating unit PU2, which arrive via the signal lines SLl, SL2.
  • the procedure of executing respective subroutines in the central processing unit CPU in response to a hardware interrupt sent over the interrupt line IL and giving higher access rights to the shared electronic resource RES by the arbitration unit AU corresponds to the embodiments as explained with respect to Fig.
  • the first and second interrupt generating units PUl, PU2 may generate a plurality of interrupts.
  • the interrupt controller IC By programming the interrupt controller IC, it is possible to select a subset of interrupts. By adding this selection mechanism per set of interrupts or per single interrupt to the embodiments, only a specific interrupt service routine or subset of interrupt service routine is boosted. I.e. only for the selected interrupts a signal is transmitted from the interrupt controller IC to the arbitration unit via line ICAU to signal that the central processing unit CPU needs raised access rights.
  • the interrupt service routine for other interrupts are not boosted, i.e. no signal is sent to the arbitration unit AU via ICAU. For instance, a hardware interrupt, such as a timer interrupt does usually not need to be boosted.
  • FIG. 1, Fig. 2 and Fig. 3 illustrate the simplified structure of an electronic circuitry that may be implemented on a single chip (e.g. within one die), on several chips (several dies), on one single board, on several different boards, or even spanning several devices each containing different boards and different devices, without leaving the spirit of the present invention.
  • the interrupt generating units PUl, PU2 can be any kind of processors, controllers, controlling or processing units such as interface controllers (e.g. WiFi, ethernet, 1394, UART or USB), smart card controllers, LCD display controllers, video decoders, video encoders, audio decoders, video decoders, teletext sheers, multiplexers, demultiplexers, DMA (Direct Memory Access modules), , etc, i.e. any hardware unit that is able to generate an interrupts, or the like.
  • One or more of the interrupt generating units PUl, PU2 - even though not shown in Figures 2 and 3, may be connected with the central processing unit CPU via one single interrupt line IL, in order to receive the same interrupt signal.
  • the shared electronic resource is not restricted to a bus or a memory.
  • the resource is usually coupled to the processing unit CPU and interrupt generating units PUl and PU2 via a bus, every kind of processor, memory or bus is to be understood as resource in the present context, regardless of the connection type.
  • Central processing units CPU do not refer to any specific kind of processor, either.
  • the central processing unit CPU and the interrupt generating units PUl, PU2 may under certain circumstances be the same type of processor.
  • the interrupt generating units PU may be embodied as further or additional central processing units such that several central processing units may be present in a data processing system. In such a situation it is also possible to lower (instead of raising) the access rights of some of the central processing units CPU and to leave the access rights of one of the central processing units CPU unchanged such that the access rights thereof is adjusted indirectly, i.e. in a complementary way.
  • the arbitration unit AU may be connected to several interrupt generating units PU as well as several central processing units CPU. Some of the interrupt generating units PU may interrupt a first central processing unit while a further interrupt generating unit PU interrupts a second central processing unit.
  • the present invention does not generally require that the first or second interrupt generating units PUl, PU2 have to be connected to the arbitration unit AU to have access to the shared resource RES.
  • the gist of the present invention concerns the idea to prompt the arbitration unit AU to give higher (or lower) access rights to the central processing unit CPU during a interrupt service routine that is triggered by one or more interrupt generating units PU 1 , PU2.
  • One embodiment of the invention is directed to an arbitration unit AU which comprises an input or an input pin for an interrupt signal (an interrupt input pin), wherein the arbitration unit changes (raises or lowers) the access rights of one of the central processing units to an electronic resource.
  • an interrupt signal an interrupt input pin
  • the arbitration unit changes (raises or lowers) the access rights of one of the central processing units to an electronic resource.
  • CPU central processing units
  • interrupt signal is input to the arbitration unit although the arbitration unit AU cannot perform any interrupts.
  • the interrupt signal is not used in the arbitration unit to interrupt any processing but to notify the arbitration unit that the central processing unit requires a higher access right to the electronic resource.
  • a unified memory architecture UMA refers to a system where different processing units store their data in a shared memory, in contrast to a situation where each processing unit has it's own physical memory. An example is where graphics chips in a motherboard uses part of the computer's main memory for video memory.
  • the invention is applicable for any electronic system that contains large amounts of hardware processing that is supported or controlled by software.
  • audio video Graphics processing for TV, Settop box, DVD- and Hard disk recorders, Trimedia based processing, the Viper IC family, Nexperia platform, for semiconductors and consumer electronics.
  • the present invention is also applicable in image processing such as in the viewing systems of medical systems. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

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Abstract

The invention relates to a data processing system, comprising at least one processing unit (CPU) for processing a software routine, at least one interrupt generating unit (PUl, PU2), an electronic resource (RES), and an arbitration unit (AU) for controlling access of at least one central processing unit (CPU) to the electronic resource (RES). The interrupt generating unit (PUl, PU2) is coupled to the central processing unit (CPU) and the arbitration unit (AU) to signal the interrupt signal to the central processing unit (CPU) and the arbitration unit (AU) in order to prompt the arbitration unit (AU) to raise the central processing unit's (CPU) access rights to the electronic resource (RES) when the central processing unit (CPU) is processing a software routine in response to the interrupt signal.

Description

Data processing system and method for accessing an electronic resource
The invention relates to a data processing system including at least one central processing unit, at least one interrupt generating unit and an arbitration unit. The arbitration unit is provided to control access of the central processing unit to a shared electronic resource, in particular to a bus or a memory. The invention is also related to a method of accessing a shared electronic resource via an arbitration unit. Furthermore, the invention relates to a method for designing an electronic circuitry, wherein the electronic circuitry comprises a central processing unit for processing software instructions, at least one interrupt generating unit and an arbitration unit. Moreover, the invention relates to the use of an interrupt signal. Still further, the invention relates to an electronic device having electronic circuitry, the electronic circuitry comprising at least one central processing unit, at least one interrupt generating unit, an arbitration unit controlling access of the central processing unit to an electronic resource.
Data processing systems or electronic devices usually comprise a central processing unit to run software routines. They comprise various kinds of additional hardware processing units for different kinds of special or dedicated purposes as well as memories. Processing units and memories are usually connected by busses or other kinds of dedicated wires or wiring. An interrupt (sometimes also called "an exception") usually forces a central processing unit to run a predetermined software interrupt routine instead of continuing with its processing. Hardware processing units may use interrupt lines to transmit interrupts. Interrupt controllers are often provided to organize multiple interrupts originating from multiple components. Arbitration units, such as bus controllers or memory controllers, handle accesses to an electronic resource, as e.g. to other processing units or controllers, to a memory, or to a bus in general to link various components. The access to the resource is then based on bus and memory arbitration using budgets like time slots or priorities or the like. The access arbitration is generally considered as an important issue as the speeds of all processing units are highly dependent on the way access is controlled.
In US 6,021,446 a network device driver performing initial IP (internet protocol) packet processing within high priority hardware interrupt service routine is disclosed. A network device, such as an a-synchronous transfer method (ATM) device, transmits an interrupt to a central processing unit. The hardware interrupt generates a put information for the packet which is then retrieved and utilized by the software interrupt to process the packet. Instead of processing the whole packet at the respective priority level of a hardware interrupt, processing priority is lowered and passed to a low priority software interrupt service routine to allow processing of other packets.
US 2003/0074508 relates to configurable prioritization of core-generated interrupts. A method and an apparatus are disclosed for generating an interrupt vector associated with either core or off-core-generated interrupts. The apparatus includes a priority encoder that sorts all of the received interrupts whether on-core or off-core, according to their priority, utilizing the programmed interrupt priority levels. Use of the priority encoder and vector generator allows a processing system to programmably specify how core-generated interrupts are to be prioritized against external interrupts.
US 2002/0166018 discloses a multiprocessor interrupt handling system. The interrupt handling system permits the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. The interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level.
US 5,070,447 relates to an interrupt circuit and an interrupt processing method for microcomputers. To assign a processing priority, the interrupt circuit provides a first priority assignment control circuit and a second priority assignment control circuit.
It is an object of the invention to provide an improved data processing system for accessing electronic resources via an arbitration unit. It is also an object of the present invention to provide a method to access an electronic resource via an arbitration unit to give improved access to the respective electronic resources. It is another object of the invention to provide a design method for an improved electronic circuitry for accessing electronic resources via an arbitration unit. It is also an object of the present invention to provide improved input signals to an arbitration unit.
These objects are solved by a data processing system according to claim 1, a method of accessing an electronic resource according to claim 7, and a method for designing electronic circuitry according to claim 9.
Accordingly, the data processing system comprises a central processing unit for processing a software routine, at least one interrupt generating unit, an electronic resource, in particular a bus or a memory, and an arbitration unit for controlling access of the at least one central processing unit to the electronic resource. An interrupt generating unit is coupled to the central processing unit and the arbitration unit to signal the interrupt signal to the central processing unit and the arbitration unit.
In current electronic devices, state of the art bus and memory arbiters are programmed by software at the beginning or start of a longer processing job. Therefore, the access rights are fixed during a longer period. In an electronic system many hardware devices could process in parallel or concurrently, if the data buffering and access arbitration is well designed. However, hardware units require to be controlled regularly by software interrupt routines. The faster these routines, the earlier the hardware processing can continue with their processing. According to current electronic devices, the access right of a processing unit does not take into account whether an interrupt routine or anything else is performed. Therefore, a specific software subroutine, such as an interrupt routine, is executed as slow as any other software, regardless of its significance for the system speed and system throughput. Central processing units with integrated memories such as caches rendered processing of software routines less dependent on access to respective resources, but specific software subroutines, in particular interrupt routines, are more dependent on access rights to electronic resources, e.g. busses or memories, because the code or the data is not likely to be in cache. So, the central processing units with internal memory, such as caches, resulted in interrupt routines being executed even slower than the rest of the software.
By signaling the interrupt signal to the arbitration unit in the data processing system and method according to the invention, the arbitration unit is prompted to raise the central processing unit's access rights to the electronic resource when the central processing unit is processing a software routine in response to the interrupt signal.
A data processing system, having the mentioned configuration, is adapted to signal the interrupt signal also to the arbitration unit, although the signal was usually intended for the central processing unit. In response the signalization of the interrupt signal, the arbitration unit raises the access rights of the central processing unit. If a software routine is processed in the central processing unit in response to the interrupt signal, the central processing unit may require access to an electronic resource that is controlled by the arbitration unit. The central processing unit will then have boosted access to the electronic resource via the arbitration unit. The at least one interrupt generating unit generates an interrupt and transmits the interrupt directly (via dedicated lines) or indirectly (e.g. via an interrupt controller) to the central processing unit. The interrupt signal prompts the central processing unit to cease the current processing, and to branch or to jump to a specific subroutine, which is dedicated to the interrupt signal. Simultaneously, the interrupt signal is transferred directly (via dedicated lines) or signaled indirectly (e.g. via an interrupt controller) to the arbitration unit. This way, by use of the same or at least equivalent signals, the arbitration unit is informed that the central processing unit should have raised access rights to the shared resource. The arbitration unit maintains raised access rights as long as indicated by the interrupt signal. The lines to be used to transmit the respective signals to the central processing unit and to the arbitration unit may be dedicated wires which are connected to any specific input of the central processing unit and the arbitration unit. The interrupt lines may also be part of a bus, in particular a bus line or a multi purpose line that is used to transmit the interrupt signal to the arbitration unit and to the central processing unit. Accordingly, the central processing unit will be able to access the shared electronic resource faster, to retrieve, transmit or exchange necessary information with the shared resource, and to complete the software subroutine in a shorter time. Moreover, the whole system benefits from faster execution of interrupt software routines, since in electronic devices, software interrupt routines are used to control hardware processing. When a software routine is delayed, the hardware processing can be delayed as well. The data system according to the present invention may include one or a plurality of central processing units, wherein each of the central processing units may have raised access rights to a shared resource, while processing a software routine in response to the interrupt signal.
According to an embodiment of the invention an interrupt controller is provided. The at least one interrupt generating unit is coupled to the central processing unit and the arbitration unit via an interrupt controller for receiving, for controlling and for signaling the interrupt signal to the central processing unit and to the arbitration unit. Accordingly, the at least one interrupt generating unit is not directly connected to the central processing unit or to the arbitration unit. The interrupt controller is dedicated to organize and process a plurality of interrupts of one or more interrupt generating units. Each of the interrupt generating units can send an interrupt signal to the arbitration unit and to the central processing unit via the interrupt controller to impose a superior access right for the central processing unit. This way, the central processing unit is enabled to access the shared resource with a higher priority in order to perform the respective subroutines faster. According to an embodiment of the invention one or more interrupt generating units generate a plurality of interrupt signals and the interrupt controller is further adapted to select an interrupt from the plurality of interrupts and to decide whether to signal the interrupt signal to the arbitration unit. According to this embodiment, the interrupt controller includes a selection mechanism, allowing the interrupt controller to associate specific interrupts or sets of interrupts with an information indicating whether the interrupt or the group of interrupts has to be signaled also to the arbitration unit. The selection mechanism may be flexibly programmed into the interrupt controller. Using an interrupt controller according to the invention, the data processing system is flexible to give raised access to the central processing unit with respect to only a selection of interrupt signals.
According to a further embodiment of the invention, at least one interrupt line is coupled to the interrupt controller, the central processing unit, and the arbitration unit. The interrupt controller, the arbitration unit, and the first central processing unit are directly connected via one single wire. The hard wired connection allows direct transmission of the interrupt signal to both the central processing and the arbitration unit.
According to an embodiment of the invention at least one interrupt line is coupled to the at least one interrupt generating unit, the at least one central processing unit, and the arbitration unit for signaling the interrupt signal to the central processing unit and to the arbitration unit. If no interrupt controller is needed, a direct electrical connection can be arranged between the interrupt generating unit, the central processing unit and the arbitration unit.
According to another embodiment of the invention at least one interrupt line is coupled to the interrupt controller and to the central processing unit for transmitting the interrupt signal, and to at least one second line is coupled to the interrupt controller and the arbitration unit for signaling the interrupt signal to the arbitration unit. This way, the transmission of the interrupt signal to one or more central processing units and the signaling of the respective interrupt signals to the arbitration unit are decoupled from each other.
It is also possible to connect a plurality of interrupt generating units to the same interrupt line, such that all the interrupt generating units are enabled to trigger specific interrupt subroutines in the central processing unit and to prompt the arbitration unit at the same time to grant improved access to the shared resource.
Further, the invention is also related to an electronic device having electronic circuitry, the circuitry comprising a central processing unit for processing a software routine, at least one interrupt generating unit for generating an interrupt signal, an electronic resource, in particular a bus or a memory, and an arbitration unit for controlling access of at least the central processing unit to the electronic resource. The interrupt generating unit is coupled to the central processing unit and the arbitration unit to signal the interrupt signal to the central processing unit and to the arbitration unit in order to prompt the arbitration unit to raise the central processing unit's access rights to the electronic resource when the central processing unit is processing a software routine in response to the interrupt signal. According to this embodiment, it is envisaged to incorporate an electronic circuitry having the above features for example on at least one single chip.
The invention is also related to a method of accessing an electronic resource within a data processing environment via an arbitration unit, in particular a memory controller or a bus controller, controlling access of a central processing unit to the electronic resource. The method comprises the steps of generating at least one interrupt signal, signaling the interrupt signal to the arbitration unit and the central processing unit, processing software instructions in response to the hardware interrupt in the central processing unit, and raising the central processing unit's access rights to the electronic resource in the arbitration unit in response to the transferred interrupt signal while the central processing unit is processing a software routine in response to the interrupt signal.
According to another embodiment of the invention the step of signaling the interrupt signal to the central processing unit and the arbitration unit comprises the steps of signaling the interrupt signal to an interrupt controller, wherein the interrupt controller signals the interrupt signal to the central processing unit, and the arbitration unit. According to the method for accessing an electronic resource, it is possible to establish an improved access to any resource, which is controlled or managed by any kind of arbitration unit. Hence, it is possible to establish a link between a software routine, in particular an interrupt routine, and access to a shared resource.
According to another embodiment of the invention, the step of processing instructions in the central processing unit in response to the hardware interrupt includes the step of processing at least one specific software subroutine in response to the hardware interrupt, and the central processing unit is granted higher access rights to the electronic resource by the arbitration unit while the central processing unit is processing the specific software subroutine.
The software subroutine processed in the central processing unit in response to the interrupt is an interrupt service subroutine, and the central processing unit is granted access by the arbitration unit when processing the interrupt subroutine. Accordingly, it is possible to boost the software processing by raising the access rights of the central processing unit at the arbitration unit (e.g. memory and/or bus arbiters). This is particularly advantageous during an interrupt routine that has to be executed faster than other subroutines. By connecting a hardware interrupt signal to the arbitration unit, the interrupt generating unit affects the priority or budget assigned to the central processing unit's access. Typically, before and after the interrupt, the central processing unit has a standard access right, whereas during an interrupt, it is given more rights (e.g. priority, budgets). Access to the electronic resource may occur only once or several times during the interrupt subroutine. Consequently, the hardware processing can continue earlier, whereas the central processing unit is not given high access rights continuously.
The invention also relates to a method for designing electronic circuitry, wherein the electronic circuitry comprises at least one central processing unit, at least one interrupt generating unit and an arbitration unit. The arbitration unit is dedicated to control access of the at least one central processing unit to an electronic resource. Further, the method comprises the step of coupling at least one interrupt generating unit, at least one central processing unit, and the arbitration unit to signal an interrupt signal from the interrupt generating unit to the central processing unit and the arbitration unit in order to prompt the arbitration unit to raise the central processing unit's access rights, when the central processing unit is processing a software routine in response to the interrupt signal. Accordingly, the interrupt generation unit is coupled to the central processing unit, and the arbitration unit for the specific purpose to signal the interrupt signal to both, the central processing unit and the arbitration unit. This is an appropriate means to enable the at least one interrupt generating unit to impose a superior access right of the central processing unit to the shared resource for a certain period of time, i.e. while the central processing unit executes a subroutine in response to the interrupt signal.
The invention relates also to a use of an interrupt signal in a data processing environment to raise access rights of at least one central processing unit to an electronic resource, in particular to a bus or a memory, the access being controlled by an arbitration unit. The use of the interrupt signal includes the steps of generating an interrupt signal, signaling the interrupt signal to the arbitration unit and the central processing unit, processing software instructions in response to the interrupt signal in the central processing unit, raising the central processing unit's access rights to the electronic resource while the central processing unit is processing a software routine in response to the interrupt signal. According to this use of a hardware interrupt, it is possible to select a specific software routine or subroutine, and to link an improved access to a shared electronic resource with an interrupt service routine. According to the invention, the specific hardware interrupt is signaled to the arbitration unit to prompt the arbitration unit to let the central processing unit have access to the electronic resource. This can speed up software processing of the central processing unit, but also of the whole data processing system. The invention is based on the idea to boost the software interrupt routine by raising the access rights of a processing unit, in particular of a central processing unit, in an arbiter (i.e. an arbitration unit) during a routine only. The object is solved for example by connecting hardware interrupt lines to the bus- and/or memory controllers (i.e. to the arbitration units), thus allowing the arbiters to affect e.g. the priority and/or budget assigned to the central processing unit's access. Before and after the interrupt, the central processing unit has a standard access right, whereas during an interrupt it is given more rights (e.g. priority and/or budgets). This way, the hardware processing can continue earlier, whereas the central processing unit is not given high access rights continuously. According to the present invention, it is possible to prompt an arbitration unit to grant access to a central processing unit. The signal to be sent to the arbitration unit in order to grant the central processing unit raised access rights to the shared electronic resource (i.e. e.g. access to a bus or a memory) is generated by an interrupt generating unit, which may be any kind of hardware unit, that has provisions to generate an interrupt signal. This way, not the central processing unit itself, but another second processing prompts the arbitration unit to grant improved access to the central processing unit.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described herein after and with respect to the following figures, wherein:
Fig. 1 shows a block diagram of an electronic circuitry according to a first embodiment;
Fig. 2 shows a block diagram of an electronic circuitry according to a second embodiment; and
Fig. 3 shows a block diagram of an electronic circuitry according to a third embodiment.
Fig. 1 shows a block diagram of an electronic circuitry according to a first embodiment of the invention that can be part of a data processing system or an electronic device. A central processing unit CPU is connected via a bus or an equivalent connection CPUAU to an arbitration unit AU. The arbitration unit AU is preferably a bus controller, a memory controller, a bus arbiter or a memory arbiter. An interrupt generating unit PUl, e.g. a hardware processing device, is connected via a second connection PUlAU to the arbitration unit AU. The arbitration unit AU controls access to an electronic resource RES. The central processing unit CPU and the interrupt generating unit PUl are further connected to each other via an interrupt line IL. The interrupt line IL connects at least an input of the central processing unit CPU and an output of the interrupt generating unit PUl . Further, the interrupt line IL is connected to the arbitration unit AU, i.e. to an input of the arbitration unit AU.
According to Fig. 1, it is possible to process instructions, i.e. a software routine, faster in the central processing unit CPU. If the software routine enters into a subroutine, into an interrupt subroutine or any other sequence of instructions in response to an interrupt (hardware interrupt), the central processing unit CPU needs to access the shared electronic resource RES. The electronic resource RES is for example a memory, a bus, another processing unit or the like. The shared electronic resources are accessible via the arbitration unit AU. The interrupt generating unit PUl sends an interrupt signal over the interrupt line IL. When receiving the interrupt signal over the interrupt line IL, the central processing unit CPU is prompted to process a specific subroutine, and jumps to the respective internal address. Simultaneously, the arbitration unit AU receives the hardware interrupt signal from the interrupt generating unit PUl. Accordingly, the arbitration unit AU raises the access rights of the central processing unit CPU to the resource RES. Access to the resource RES occurs via the bus CPUAU connecting the central processing unit CPU and the arbitration unit AU.
When the central processing unit's CPU interrupt routine is finished or after sufficient access to the resource RES has been granted to the central processing unit CPU, the interrupt generating unit PUl may access the resource RES via the connection PUlAU and via the arbitration unit AU. The configuration in Fig. 1 shows also a particular use of an interrupt signal.
For example, an interrupt signal is transmitted over the interrupt line IL to the central processing unit CPU. In response to the interrupt signal the central processing unit enters an interrupt service routine. The interrupt signal is also used to indicate via interrupt line IL an urgent request to the arbitration unit AU for an access of the central processing unit CPU to the resource RES. The interrupt subroutines processed in the central processing unit CPU in response to the interrupt signal profit from an enhanced access to the resource RES. Faster access for specific subroutines improves the overall performance of the system and boosts the software interrupt routine processing by raising the access rights of the central processing unit in the arbitration unit (e.g. memory and/or bus arbiters). This way, it is particularly avoided that the access rights of the central processing unit CPU are unaware of whether an interrupt routine or anything else is performed. The interrupt routine is executed faster than other portions of the software, which need access to the resource RES. In particular in case the central processing unit CPU has internal memory, such as cache, the interrupt routine may be executed faster than the rest of the software that needs access to the resource RES.
Fig. 2 shows a block diagram of an electronic circuitry according to a second embodiment of the present invention. The central processing unit CPU is connected to an arbitration unit AU via a bus CPUAU. A first interrupt generating unit PUl, e.g. a hardware processing device, is connected to the arbitration unit AU via a bus PUlAU. A second interrupt generating unit PU2 is connected to the arbitration unit AU via a bus PU2AU. The arbitration unit AU controls access to the electronic resource RES. The first interrupt generating unit PUl and the second interrupt generating unit PU2 are connected to the interrupt controller IC via two signal lines SLl, SL2, respectively. The interrupt line IL is connected to the central processing unit CPU, the interrupt controller IC and the arbitration unit AU.
The interrupt line IL allows the interrupt controller IC to send an interrupt to the arbitration unit AU and the central processing unit CPU. The central processing unit CPU enters into a software subroutine or an interrupt routine, that requires an access to the electronic resource RES. Once the interrupt signal is asserted to the interrupt line IL, the arbitration unit AU gives access to the resource RES, but only to the central processing unit CPU. Access occurs via the bus CPUAU between the central processing unit CPU and the arbitration unit AU. If the interrupt line IL does not indicate a request to access the electronic resource RES, the first interrupt generating unit PUl and the second interrupt generating unit PU2 can access the resource RES via the arbitration unit AU, by use of the busses PUlAU and PU2AU, respectively. PUlAU and PU2AU can be distinct or identical busses. The central processing unit CPU may also share the same bus.
Instead of connecting the interrupt line IL to the first interrupt generating unit PUl and the second interrupt generating unit PU2 independently, interrupts of both interrupt generating units PUl, PU2 are controlled by one interrupt controller IC. The first and second interrupt generating units PUl, PU2 indicate via the signal lines SLl and SL2 to the interrupt controller IC that the central processing unit CPU should execute a certain subroutine. The interrupt controller transmits a corresponding interrupt signal over the line IL. Accordingly, the central processing unit CPU starts the respective subroutine triggered by the interrupt. The interrupt signal is also signaled to the arbitration unit via interrupt line IL. In response to the interrupt signal, the arbitration unit AU gives higher access rights to the central processing unit CPU. As far as the first interrupt generating unit PUl and the second interrupt generating unit PU2 need also access to the shared resource, they have to wait until the central processing unit CPU has finished the subroutine (interrupt service routine) or the access to the electronic resource RES, before they are allowed to access the electronic resource RES. Concerning the use of the interrupt line IL and the method of accessing the resource RES via the arbitration unit AU with respect to software subroutines, the same considerations apply, as set out with respect to the first embodiment of Fig. 1.
Fig. 3 shows a block diagram of an electronic circuitry according to a third embodiment of the present invention. In this embodiment the interrupt line IL is only connected between the central processing unit CPU and the interrupt controller IC. However, in contrast to the second embodiment shown in Fig. 2, the interrupt controller IC is connected via a dedicated line ICAU to the arbitration unit AU. As in the previous embodiments the first interrupt generating unit PUl or the second interrupt generating unit PU2 indicate via the signal lines SLl or SL2, respectively, that the central processing unit CPU has to carry out a specific interrupt service routine. The interrupt controller IC transmits the interrupt signal via interrupt line IL to the central processing unit CPU, which in response branches to the respective interrupt service routine. The interrupt controller also indicates via the line ICAU to the arbitration unit AU that the central processing unit CPU has to get raised access rights to the resource RES via the bus CPUAU. In this configuration, the interrupt controller IC controls the interrupts from the first interrupt generating unit PUl and the second interrupt generating unit PU2, which arrive via the signal lines SLl, SL2. The procedure of executing respective subroutines in the central processing unit CPU in response to a hardware interrupt sent over the interrupt line IL and giving higher access rights to the shared electronic resource RES by the arbitration unit AU corresponds to the embodiments as explained with respect to Fig. 1 and 2 except that two different lines are used to signal the hardware interrupt from the interrupt controller IC to the central processing unit CPU (via interrupt line IL) and from the interrupt controller IC to the arbitration unit AU (via line ICAU). This way, it is possible to decouple the electrical and logical implementation of the interrupt line (coupled to the central processing unit CPU) and the signal for the arbitration unit AU.
With respect to the embodiments shown in Figures 2 and 3, the first and second interrupt generating units PUl, PU2 may generate a plurality of interrupts. By programming the interrupt controller IC, it is possible to select a subset of interrupts. By adding this selection mechanism per set of interrupts or per single interrupt to the embodiments, only a specific interrupt service routine or subset of interrupt service routine is boosted. I.e. only for the selected interrupts a signal is transmitted from the interrupt controller IC to the arbitration unit via line ICAU to signal that the central processing unit CPU needs raised access rights. The interrupt service routine for other interrupts are not boosted, i.e. no signal is sent to the arbitration unit AU via ICAU. For instance, a hardware interrupt, such as a timer interrupt does usually not need to be boosted.
The block diagrams, as shown in Fig. 1, Fig. 2 and Fig. 3, illustrate the simplified structure of an electronic circuitry that may be implemented on a single chip (e.g. within one die), on several chips (several dies), on one single board, on several different boards, or even spanning several devices each containing different boards and different devices, without leaving the spirit of the present invention.
According to all embodiments illustrated in Fig. 1 - 3, the interrupt generating units PUl, PU2 can be any kind of processors, controllers, controlling or processing units such as interface controllers (e.g. WiFi, ethernet, 1394, UART or USB), smart card controllers, LCD display controllers, video decoders, video encoders, audio decoders, video decoders, teletext sheers, multiplexers, demultiplexers, DMA (Direct Memory Access modules), , etc, i.e. any hardware unit that is able to generate an interrupts, or the like. One or more of the interrupt generating units PUl, PU2 - even though not shown in Figures 2 and 3, may be connected with the central processing unit CPU via one single interrupt line IL, in order to receive the same interrupt signal.
Likewise, the shared electronic resource according to all embodiments is not restricted to a bus or a memory. Although, the resource is usually coupled to the processing unit CPU and interrupt generating units PUl and PU2 via a bus, every kind of processor, memory or bus is to be understood as resource in the present context, regardless of the connection type. Central processing units CPU do not refer to any specific kind of processor, either. In particular, the central processing unit CPU and the interrupt generating units PUl, PU2, may under certain circumstances be the same type of processor.
In an alternative embodiment the interrupt generating units PU may be embodied as further or additional central processing units such that several central processing units may be present in a data processing system. In such a situation it is also possible to lower (instead of raising) the access rights of some of the central processing units CPU and to leave the access rights of one of the central processing units CPU unchanged such that the access rights thereof is adjusted indirectly, i.e. in a complementary way. The arbitration unit AU may be connected to several interrupt generating units PU as well as several central processing units CPU. Some of the interrupt generating units PU may interrupt a first central processing unit while a further interrupt generating unit PU interrupts a second central processing unit. Particularly, the present invention does not generally require that the first or second interrupt generating units PUl, PU2 have to be connected to the arbitration unit AU to have access to the shared resource RES. The gist of the present invention concerns the idea to prompt the arbitration unit AU to give higher (or lower) access rights to the central processing unit CPU during a interrupt service routine that is triggered by one or more interrupt generating units PU 1 , PU2.
One embodiment of the invention is directed to an arbitration unit AU which comprises an input or an input pin for an interrupt signal (an interrupt input pin), wherein the arbitration unit changes (raises or lowers) the access rights of one of the central processing units to an electronic resource. Typically, merely central processing units CPU comprise an input for an interrupt signal as interrupt signal are usually required for central processing units to stop or interrupt an application running on the central processing units. However, here the interrupt is input to the arbitration unit although the arbitration unit AU cannot perform any interrupts. In fact the interrupt signal is not used in the arbitration unit to interrupt any processing but to notify the arbitration unit that the central processing unit requires a higher access right to the electronic resource.
A data processing system having the features according to the present invention, in particular the features of one of the above embodiments shown in Figures 1, 2 and 3, is particularly useful in a unified memory architecture (or unified memory designs), wherein the unified memory constitutes a shared resource with restricted access capacity. A unified memory architecture UMA refers to a system where different processing units store their data in a shared memory, in contrast to a situation where each processing unit has it's own physical memory. An example is where graphics chips in a motherboard uses part of the computer's main memory for video memory.
More generally, the invention is applicable for any electronic system that contains large amounts of hardware processing that is supported or controlled by software. For example, audio, video Graphics processing for TV, Settop box, DVD- and Hard disk recorders, Trimedia based processing, the Viper IC family, Nexperia platform, for semiconductors and consumer electronics. The present invention is also applicable in image processing such as in the viewing systems of medical systems. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device and system claims in numerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are resided in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. Data processing system, comprising: at least one processing unit (CPU) for processing a software routine, at least one interrupt generating unit (PUl, PU2) for generating at least one interrupt signal, - an electronic resource (RES), and an arbitration unit (AU) for controlling access of the at least one processing unit (CPU) to the electronic resource (RES), the interrupt generating unit (PUl , PU2) being coupled to the at least one processing unit (CPU) and the arbitration unit (AU) to signal the interrupt signal to the at least one processing unit (CPU) and the arbitration unit (AU) in order to prompt the arbitration unit (AU) to raise the access rights of the at least one processing unit (CPU) to the electronic resource (RES) while the at least one processing unit (CPU) is processing the software routine in response to the interrupt signal.
2. Data processing system according to claim 1, further comprising: an interrupt controller (IC), wherein the at least one interrupt generating unit (PUl, PU2) is coupled to the at least one processing unit (CPU) and the arbitration unit (AU) via the interrupt controller (IC) for receiving, for controlling and for signaling the interrupt signal to the at least one processing unit (CPU) and to the arbitration unit (AU).
3. Data processing system according to claim 2, wherein the at least one interrupt generating unit (PUl, PU2) generates a plurality of interrupt signals and the interrupt controller (IC) is further adapted to select an interrupt signal from the plurality of interrupts signals and to decide whether to signal the interrupt signal to the arbitration unit (AU).
4. Data processing system according to claim 2 or 3, further comprising at least one interrupt line (IL) being coupled to the interrupt controller (IC), the at least one processing unit (CPU) and the arbitration unit (AU) for signaling the interrupt signal to the at least one processing unit (CPU) and to the arbitration unit (AU).
5. Data processing system according to claim 1, further comprising - at least one interrupt line (IL) being coupled to the at least one interrupt generating unit (PUl, PU2), to the at least one processing unit (CPU) and the arbitration unit (AU) for signaling the interrupt signal to the at least one processing unit (CPU) and to the arbitration unit (AU).
6. Data processing system according to claim 2, further comprising at least one interrupt line (IL) being coupled to the interrupt controller (IC) and to the at least one processing unit (CPU) for transmitting the interrupt signal, and at least one second line (ICAU) being coupled to the interrupt controller (IC) and the arbitration unit (AU) for signaling the interrupt signal to the arbitration unit (AU).
7 Method of accessing an electronic resource (RES) within a data processing environment via an arbitration unit (AU), controlling access of at least one processing unit (CPU) to the electronic resource (RES), comprising the steps of: generating at least one interrupt signal, - signaling the interrupt signal to the arbitration unit (AU) and the at least one processing unit (CPU), processing software instructions in response to the interrupt signal in the at least one processing unit (CPU), and raising the access rights of the at least one processing unit (CPU) to the electronic resource (RES) in the arbitration unit (AU) in response to the signaled interrupt signal when the at least one processing unit (CPU) is processing the software routine in response to the interrupt signal.
8 Method according to claim 7 wherein the step of signaling the interrupt signal to the at least one processing unit (CPU) and the arbitration unit (AU) comprises the steps of signaling the interrupt signal to an interrupt controller (IC), and the interrupt controller (IC) signaling the interrupt signal to the at least one processing unit (CPU), and the arbitration unit (AU). 9 Method for designing electronic circuitry, the electronic circuitry comprising at least one processing unit (CPU), at least one interrupt generating unit (PUl, PU2) and an arbitration unit (AU), the arbitration unit (AU) controlling access of the at least one central processing unit (CPU) to an electronic resource (RES), the method comprising the step of - coupling at least one interrupt generating unit (PUl, PU2), the at least one processing unit (CPU) and the arbitration unit (AU) for signaling an interrupt signal from the interrupt generating unit (PUl, PU2) to the at least one processing unit (CPU) and the arbitration unit (AU) in order to prompt the arbitration unit (AU) to raise the access rights of the at least one processing unit (CPU), when the at least one processing unit (CPU) is processing the software routine in response to the interrupt signal.
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Citations (3)

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US5392436A (en) * 1989-11-03 1995-02-21 Compaq Computer Corporation Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
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