WO2006058349A1 - Detonator device - Google Patents

Detonator device Download PDF

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Publication number
WO2006058349A1
WO2006058349A1 PCT/ZA2005/000175 ZA2005000175W WO2006058349A1 WO 2006058349 A1 WO2006058349 A1 WO 2006058349A1 ZA 2005000175 W ZA2005000175 W ZA 2005000175W WO 2006058349 A1 WO2006058349 A1 WO 2006058349A1
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WO
WIPO (PCT)
Prior art keywords
oxidant
porous
substrate
layer
porous material
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PCT/ZA2005/000175
Other languages
French (fr)
Inventor
Monuko Du Plessis
Cornelius Du Plooy Conradie
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The University Of Pretoria
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Publication of WO2006058349A1 publication Critical patent/WO2006058349A1/en

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    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42AMMUNITION; BLASTING
    • F42BEXPLOSIVE CHARGES, e.g. FOR BLASTING, FIREWORKS, AMMUNITION
    • F42B3/00Blasting cartridges, i.e. case and explosive
    • F42B3/10Initiators therefor
    • F42B3/11Initiators therefor characterised by the material used, e.g. for initiator case or electric leads
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42AMMUNITION; BLASTING
    • F42BEXPLOSIVE CHARGES, e.g. FOR BLASTING, FIREWORKS, AMMUNITION
    • F42B3/00Blasting cartridges, i.e. case and explosive
    • F42B3/10Initiators therefor
    • F42B3/12Bridge initiators
    • F42B3/13Bridge initiators with semiconductive bridge

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Weting (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method of making a detonating device which includes the steps of treating a substrate (1) to form a porous structure, impregnating the porous structure (14) at least partly with an oxidant (18) and forming at least one arrangement which, when actuated, transfers heat to the oxidant (18) to initiate the oxidant (18), integrally with the substrate (14).

Description

DETONATOR DEVICE
BACKGROUND QF THE INVENTION
[0001] This invention relates to a detonator device.
[0002] Electronic detonators, which include electronic timing and initiating circuitry on a silicon chip, find widespread application. In this type of detonator it is known to make use of a resistive element as a heat generating device to initiate a small amount of pyrotechnic composition which is external to the silicon material.
Alternatively an electrically conductive track can be fused by passing a current of a predetermined magnitude through the track and the resulting heat pressure and shock effects are used to initiate a small primary explosive which is external to the chip which, in turn, initiates a base charge.
[0003] Detonators of the aforementioned kind are manufactured in multi-step discrete processes, which include various manual operations. These techniques can give rise to quality and processing problems. Also the materials, which are used as primary explosives, are sensitive and can be toxic which implies that extensive safety and health precautions have to be taken to protect personnel against the hazards, which are inherently associated with the use of these materials. This in turn adds to the cost of the end product.
SUMMARY OF INVENTION
[0004] The invention is concerned with a detonator device which, at least partly, addresses the aforementioned problems. [0005] The invention provides a detonator device which includes a body of a porous material, an oxidant which is impregnated into the porous material, and means for supplying energy to the oxidant thereby to initiate the oxidant.
[0006] The detonator device may include a bulk substrate and the body of porous material may be provided on or in the substrate.
[0007] The substrate may be of any appropriate type and preferably is a semiconductor material such as silicon or any other suitable material.
[0008] The semiconductor material may be p-type or n-type
[0009] The body of porous material may be selectively formed in one or more regions of the substrate. This may be achieved by making use of any appropriate technique, for example masking technology.
[0010] The substrate may include one or more integrated circuits for controlling the operation of the detonating device. Such circuits may be of a kind known in the art and for example may include timing, initiating and communication circuits.
[0011] The porous material may be formed using electrochemical or chemical techniques. Through the use of the masking technology a protective layer may be provided on a surface of the substrate. The protective layer may layer may be selectively deposited or grown on the substrate surface to facilitate the formation of the body of porous material in one or more defined regions.
[0012] The protective layer may comprise any suitable material such as silicon nitride, silicon dioxide, polycrystalline silicon or a combination of these materials. [0013] The protective layer may be selectively defined using photolithographic techniques which are known in the art.
[0014] Alternatively the protective layer is implanted or diffused into the substrate or epitaxially grown on a surface of the substrate.
[0015] The implanted, diffused or epitaxial layer may be a semiconductor n-type material at a surface of a p-type substrate. It is possible, by using differential electrochemical/chemical etch rates of two types of materials, to form the porous material at the surface of the substrate only in selected regions.
[0016] The oxidant may be impregnated into the porous material by immersing the porous material into a liquid containing the oxidant in solution, or by putting the liquid onto a surface of the porous material.
[0017] The oxidant may be any appropriate material and for example may be gadolinium nitrate, potassium nitrate or a similar material.
[0018] The energy which is supplied to the oxidant may be in a form selected from the following: thermal energy, electrical energy, optical energy, infrared energy, electromagnetic energy which may for example be at radio frequency or microwave frequency, ultrasonic energy, magnetic energy, and acoustic energy.
[0019] The thermal energy may be derived from electrical energy which is dissipated in or near the porous material as a result of an electrical current which is passed through a resistive layer.
[0020] The resistive layer is preferably integrated within or is embedded inside the porous material. [0021] Thermal energy may be added to the oxidant by passing an electrical current through an electronic device which is in or close to the porous material thereby causing electrical power dissipation in the device which heats at least part of the porous material. Thermal energy which is transferred to the oxidant causes initiation thereof.
[0022] The electronic device may be on or embedded in the porous material.
[0023] The porous material preferably has a low coefficient of thermal conductivity and consequently thermally isolates the electronic device from the substrate. This is important because a relatively low level of power dissipation in the electronic device can cause efficient heating of the oxidant to a high temperature.
[0024] The electronic device may be a resistor (ohmic) device or a non-ohmic device at a surface of or in the porous material, or near to the porous material.
[0025] A resistive electronic device may be formed as a resistive layer at a surface of the porous material or near the porous material.
[0026] The resistive layer may be a polysilicon or thin film resistor formed on a surface of the porous material.
[0027] The resistive layer may be an n-type semiconductor layer formed inside porous material in a p-type substrate. The same n-type layer can be used as a masking material to locally define the porous material.
[0028] The non-ohmic electronic device may be a device which passes current only in one direction, for example a forward-biased diode in series with a resistive layer, or a high electric field breakdown region in or near the porous material. [0029] The high electric field breakdown region may make use of avalanche, zener or punch-through breakdown mechanisms in the substrate or in the porous material.
[0030] The high electric field breakdown may alternatively be the dielectric breakdown of the porous material, the oxidant within the porous material, the substrate, or the dielectric breakdown of an external material covering a surface of the porous material, e.g. a dielectric or air covering the surface.
[0031] Ultrasonic or acoustic energy may be transferred to the primary impregnated oxidant if the substrate material is piezo-electric. Electrodes placed on a surface of the substrate or porous material can be used to transform an electrical input signal into surface or bulk acoustic waves, and these shock waves propagating through the substrate and porous material are used to initiate the oxidant.
[0032] The ultrasonic or acoustic energy may be from a source which is external to the detonator device, propagating shock waves towards the substrate and porous material. In this case the substrate need not be piezo-electric.
[0033] Electrical energy may also be transferred to the oxidant by placing an electromagnetic signal source close to the porous material. This electromagnetic source may be external to the detonating device, or integrated in the substrate. The electromagnetic signal may be in the form of RF radio waves, microwaves, or any other suitable electromagnetic signal. The electromagnetic signal can be detected in the detonator device using appropriate detection devices, e.g. coil antennas, to generate electrical power dissipation and/or heat dissipation in the porous material.
[0034] Optical energy may be used to transfer energy to the oxidant. This may be by means of a direct or indirect heat generation method. [0035] Direct optical heat generation entails having optical, infrared or ultraviolet radiation falling onto a surface of the detonator device and, due to absorption of radiation in the substrate and porous material, heat is generated in the porous material which initiates the oxidant. The source of the radiation may be external or internal to the detonator device.
[0036] External sources of radiation may be semiconductor light emitting devices, semiconductor lasers, or any other suitable source of radiation. Transmission of the radiation towards the substrate and porous material may be via atmospheric transmission, or wave guide transmission, e.g. optical fibres.
[0037] Internal sources of radiation may be light emitting devices (electro- or photo- luminescent devices) fabricated in or on the substrate. Porous silicon is photo- and electro-luminescent, and passing an electrical current through porous silicon results in light being emitted from the porous silicon. The photo-luminescent property of porous silicon may be used to transform an external source of radiation (for example a source with spectral properties not suitable for absorption in semiconductor silicon) into an internal source of radiation at wavelengths which are easily absorbed in silicon. Other internal electro-luminescent sources of radiation may be forward- or reverse-biased pn junctions integrated in or on the substrate. By reverse biasing pn junctions (direct and indirect bandgap materials) into the reverse breakdown region of operation, these junctions act as a source of optical signals. Forward biasing of pn junctions is also a source of optical emission.
[0038] Indirect optical heat generation may be accomplished by converting an optical input signal firstly into electrical energy using the properties of opto-electronic detecting devices. A semiconducting pn junction may be used to generate a photovoltaic voltage or current as a result of absorbing incoming radiation. This electrical signal can then be utilised to generate electrical power dissipation near or in the porous material in a manner which is similar to any of the methods described previously.
[0039] The explosive force and heat energy generated by initiation of the oxidant inside the porous material may be utilised to initiate a secondary energetic material.
This may be accomplished by means of heat or a shock wave generated by a primary explosion inside the porous material. For this method the secondary energetic material should be in close proximity to a surface of the porous material.
[0040] The secondary energetic material can also be initiated by causing the oxidant, when fired, to propel a projectile at a high velocity and with adequate kinetic energy into the energetic material. On impact, the projectile can even initiate a relatively insensitive energetic material.
[0041] The projectile can be external or internal to the porous material.
[0042] An external projectile may be located on or very close to a surface of the porous material and, when the oxidant is initiated, the projectile is propelled towards the secondary explosive material. The projectile may, for example, be a layer of metal deposited on to a surface of the porous material.
[0043] An internal projectile may be integrated into the porous material. Through the use of selective porous etching technology and appropriate masking technology, substrate material can be embedded within the porous material, fully surrounded by porous material, except at a surface thereof. When the oxidant is initiated, the explosive force drives the projectile out of the porous material, and directs the projectile towards the secondary material. [0044] A surface of the substrate may be modified, for example by selective anisotropic etching, to form a cavity in the surface. Regions of the substrate at sidewalls of the cavity may then be made porous via electrochemical or chemical means and, when the porous regions are impregnated with the primary oxidant, a geometrically shaped "shaped charge" structure is achieved. By using the concept of shaped charges, the force of an explosion can be concentrated in a specific direction, and the speed and kinetic energy of material propelled outwards from the cavity after initiation of the oxidant or primary explosive are increased.
[0045] In another embodiment of this application, a projectile can be placed inside the cavity, increasing the efficiency of the primary initiation.
[0046] A pyrotechnic delay may also be integrated into the substrate. The material may for example include two geometries, namely a first, long and narrow porous region, and a second, porous region with much larger volume connected to the first region. The long and narrow porous region acts as a pyrotechnic delay element, with a delay determined by the length of the region. The second porous region with larger volume acts as a primary explosive region. An initiation device is then used to initiate the impregnated oxidant at one end of the delay element and, after a delay determined by the length of the element, the reaction will reach the primary explosive porous region.
[0047] The pyrotechnic delay may be made mask- or electrically-programmable.
For example, several initiation sites may be used to initiate the reaction in the delay element, with each of the initiation sites having a different delay from the initiation site to the primary explosive porous region as a result of different delay lengths from the respective initiation site to the primary explosive porous region. [0048] The detonator device may be electrically- or mask-programmable by selecting a specific initiation site to be activated, and thus determining the delay of the pyrotechnic detonation. This selection may be mask-programmable, but can also be programmed electronically via fuses or active element switching.
[0049] The invention also extends to a method of making a detonating device which includes the steps of treating a substrate to form a porous structure, impregnating the porous structure at least partly with an oxidant and forming at least one arrangement which, when actuated, transfers heat to the oxidant to initiate the oxidant, integrally with the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0050] The invention is further described by way of examples with reference to the accompanying diagrammatic drawings in which:
Figure 1 is a sectional view of a discrete silicon explosive device according to a first embodiment of the invention; Figure 2 is a sectional view of an integrated silicon explosive device with selective porous regions defined by a masking technology;
Figure 3 is a sectional view of a detonator device according to the invention, in which thermal energy is used to initiate an oxidant;
Figure 4 is a sectional view of a resistive structure in a serpentine or parallel configuration to generate heat substantially uniformly in an oxidant-impregnated porous material;
Figure 5 is a plan view of a serpentine resistive structure;
Figure 6 is sectional view of an explosive device according to the invention in which an implanted n-type resistive layer is protected against a porous etching process by a masking layer; Figure 7 is a sectional view of an explosive device according to another form of the invention;
Figure 8 illustrates how a second layer of polysilicon is used to mask a first resistive polysilicon layer against a porous etch process; Figure 9 illustrates a method in which electrical power is dissipated in a resistive layer by passing current through an ohmic integrated ion implanted n-type resistor;
Figure 10 illustrates a method in which electrical power is dissipated in a resistive layer by passing current through a non-ohmic combination of an integrated ion implanted n-type resistor in series with a forward biased pn junction in a porous material;
Figure 11 illustrates a method in which electrical power is dissipated in a resistive layer by passing current through a non-ohmic combination of an integrated ion implanted n-type resistor in series with a forward biased pn junction formed in a substrate; Figure 12 shows the dissipation of electrical power in a resistive layer by passing current through an ohmic resistor formed on a surface of a porous material;
Figure 13 shows the dissipation of electrical power in a resistive layer by passing current through an ohmic resistor formed on a surface of a porous material, but electrically isolated from a substrate and from the porous material; Figure 14 shows an embodiment of an explosive device according to the invention, in which energy is generated to initiate an explosive oxidant by means of a high electric field breakdown mechanism across a region formed between two closely-spaced integrated ion implanted regions inside a porous material;
Figure 15 is a sectional view of another embodiment of the invention, in which energy is generated to initiate an explosive oxidant by means of a high electric field breakdown mechanism across a region formed between two closely-spaced electrodes on a surface of a porous material; Figure 16 is a sectional view of another of a device according to the invention, in which energy is generated to initiate an explosive oxidant by means of a high electric field breakdown mechanism (avalanche or field emission) in a reverse biased pn junction in a porous marerial; Figure 17 is similar to Figure 16 and shows the generation of energy to initiate an explosive oxidant by means of a high electric field breakdown mechanism (avalanche or field emission) in a reverse biased pn junction in a bulk substrate;
Figure 18 is a sectional view of an embodiment in which optical energy is transmitted directly to an impregnated oxidant via an optical fibre from an external optical source; Figure 19 is a sectional view of an embodiment in which indirect use is made of incoming optical energy to generate heat in a porous material;
Figure 20 is a sectional view of an embodiment in which an optical signal to initiate an oxidant is generated internally on a semiconductor substrate which contains a porous material which is impregnated with an oxidant; Figure 21 is similar to Figure 20 but showing the use of an ultrasonic signal to initiate the oxidant;
Figure 22 is a sectional view of an embodiment in which a secondary sensitive material is initiated by propelling a projectile into the secondary energetic material as a result of an initiation of an oxidant in a porous material; Figure 23 is similar to Figure 22, but wherein a projectile is propelled towards a secondary energetic material which is integrated within the porous maerial;
Figure 24 is a sectional view of an embodiment which makes use of a shaped charge concept;
Figure 25 is a similar to Figure 24, but wherein an initiation device is on surface of a substrate which is remote from a surface in which a cavity (shaped charge) is etched; Figure 26 is a sectional view of an embodiment in which a pyrotechnic delay element is integrated into the same substrate as an oxidant impregnated porous material; and;
Figure 27 is a plan view of a form of the invention in which an electronic or mask programmable pyrotechnic delay element is integrated in a substrate which contains an oxidant.
DESCRIPTION OF PREFERRED EMBODIMENTS
[0051] An explosive or detonating device according to the invention is generally designated by the reference 10 in the drawings.
[0052] Figure 1 is a sectional view of a discrete explosive silicon-based device 10 which includes a substrate 12 in the form of a standard single crystal silicon body or wafer. A continuous porous silicon region 14 is fabricated by means of an electrochemical or chemical process towards a surface 14.1.
[0053] Porous silicon is a sponge-like structure built out of bulk silicon after electrochemical or chemical etching of the bulk material. A remarkable property of porous silicon is its enormous internal surface area per unit volume (up to 103 m2/cm3). This is due to the fact that the porous layer consists of pores 16 and silicon nanocrystals with typical dimensions in the order of 2 to 50 nm.
[0054] The pores 16 are filled with an oxidant 18, e.g. gadolinium nitrate. Effectively, the combination of the porous silicon and the oxidant is a silicon-based version of black powder, which is a mixture of potassium nitrate, sulphur and charcoal. [0055] Energy can be supplied to the embedded oxidant 18 in order to initiate an explosion. The explosive properties of the porous silicon impregnated with the oxidant depend on a number of parameters, such as the porosity and thickness of the porous region or layer, the type of oxidant 18 and the oxidant concentration.
[0056] Figure 2 shows an explosive device 10 with a silicon substrate 12 which is suitable for the integral fabrication of an integrated circuit 15 which is shown only schematically and which can include timers, communication modules, and similar circuitry needed to supply initiation energy to the oxidant in a controlled way.
[0057] In order to have localised formation of the porous silicon layer 12, masking layers 20 are formed in selected surface areas 12.1 of the substrate 12. These layers prevent porous silicon formation immediately below the layers. A typical masking layer comprises silicon nitride or a silicon dioxide/polysilicon sandwich combination.
[0058] Figure 3 shows that thermal energy can be supplied to the embedded oxidant 18 by means of a resistive layer formed inside the porous layer 14 at the surface 14.1. An n-type resistive layer 22, typically formed by ion implantation or diffusion, is formed inside a p-type substrate 12. A masking layer 20 at the surface 12.1 is used to confine the porous silicon 14 to specific areas.
[0059] The porous silicon etch rates of p- and n-type silicon differ when the electrochemical/chemical etching is performed in the dark, with the n-type silicon etch rate being significantly lower than that of p-type material. In the presence of both doping type regions on one substrate, it is possible to form porous silicon 14 in only the p-doped regions and the n-type regions 22 remain basically untouched. As long as the porous silicon layer thickness TP>0.5χWN, with WN the n-type layer width, the n-type resistive layer 22 will be fully embedded within the porous layer 14, since the lateral porous silicon etch dimension is comparable to the vertical porous silicon depth Tp.
[0060] Two electrical contacts (not shown) can be made to the n-type layer 22 and electrical current can be passed through the resistor, thus dissipating electrical energy and generating localised heat in the resistor. The advantage of this device is that the n-type resistive layer 22 is fully embedded within the porous layer 14.
[0061] Porous silicon has a thermal conductance that is about 1000 times smaller than that of bulk silicon. The low thermal conductance of the porous layer 14 (this thermal conductance may be altered somewhat by the impregnated oxidant 18, but not significantly) will ensure that the resistive n-type layer 22, embedded in the thermally isolated porous layer surface 14.1, is thermally isolated from the bulk substrate 12. Consequently the resistive layer 22 needs significantly less electrical power to reach a given temperature compared to a resistor which may be provided on the surface 12.1 of the bulk silicon.
[0062] Figure 4 shows that the resistive layer 22 may consist of a number of parallel resistive structures, or a single linear resistor designed as a serpentine pattern, generating heat substantially uniformly throughout the porous region 14, from the surface 14.1.
[0063] Figure 5 is a plan view of the sectional device structure shown in Figure 4. A silicon chip 28 includes an n-type serpentine resistor 22 embedded into the surface 14.1. The porous layer is selectively etched into the bulk substrate surface 12.1 using a silicon nitride or silicon dioxide/polysilicon sandwich mask layer. Two conductors 26, e.g. of aluminium, are used to make contact with the resistive layer 22 via contact holes 24, and current can then be passed through the two-terminal resistor 22.
[0064] Figure 6 shows an embodiment of the explosive device 10 in which the typical thickness of the porous layer 14 is in the order of 25 to 50 microns, and the n- type implanted or diffused layer 22 extends into the p-type substrate from the surface
12.1 by about 1 micron. The differential porous etch rate of the n-type and p-type material may be of such a nature that surface etching of the n-type silicon layer may occur. This vertical etching of the n-type layer 22 at the n-type surface may cause a variation in the resistance of the n-type resistor. In the extreme case, for a very thick porous layer 14, the n-type layer 22 may be totally etched into a porous structure.
[0065] To prevent this, silicon nitride (or another mask layer) may be used as porous etch mask material 20 on top of the n-type region 22. The n-type region 22 will then act as a mask material against porous etching of the n-type layer in the lateral dimension, preserving the integrity of the resistive layer. The width of the n- type layer will be in the order of 10 to 20 microns, with the result that any lateral etching that may occur will have almost no influence on the resistor value. Since the silicon nitride mask layer 20 is relatively thin (approximately 200 nm), phosphorous can be implanted through the layer 20 with the layer serving as an implant screening layer. In this case, state of the art patterned photoresist technology on top of the silicon nitride layer can act as an implant mask to define the implanted region 22.
[0066] As is shown in Figure 6, openings etched into the mask layer 20 define one or more regions through which the surface 14.1 will be exposed to the environment, and the porous layer is impregnated with the oxidant 18 through these openings. Before the openings are etched in the mask layer 20, photoresist on top of the layer 20 can be used to define the implanted n-type regions 22. [0067] Figure 7 schematically shows an embodiment in which a resistive element 30 is deposited on the silicon surface. The resistive layer 30 may be put directly on the surface 14.1, since the porous layer 14 has a larger resistance than the resistive element, but for improved isolation an isolation layer 32, e.g. of silicon dioxide, is deposited or grown before depositing the resistive layer 30. The resistive layer 30 may be polysilicon or a thin film metal resistive material, like Pt and can also act as a masking layer for the selective etch of the porous regions.
[0068] Figure 8 shows an embodiment in which a sandwich structure of silicon dioxide 32 and polysilicon 30 is used as a masking material to define district porous regions. During a porous etch process the polysilicon layer 30 is transformed into a porous layer through to the oxide, and the bulk surface 12.1 is then protected from the porous silicon etch via the oxide/porous polysilicon sandwich structure.
[0069] To fabricate the polysilicon layer 30 use may be made of state of the art double polysilicon integrated circuit technology. In this technology a second polysilicon layer 34 is grown on top of a first polysilicon layer 30, with a silicon dioxide isolation layer 32 as dielectric between the two layers. The layer 34 is etched into a porous polysilicon layer, but a portion 30.1 of the first polysilicon layer, underneath the second polysilicon layer 34 is protected from the etch. This means that the protected resistive layer 30.1 is used at the surface 14.1 to generate heat and ignite the oxidant 18. The first polysilicon layer 30 may be used as a mask to protect the substrate surface 12.1 from the porous silicon etch, without the use of the second polysilicon layer 34, in the regions where the resistive layer is not needed.
[0070] Provided the porous silicon layer thickness TP>0.5xWP, with WP the width of the second polysilicon layer 34, the polysilicon resistive layer 30.1 will cover all of the porous material 14, since the lateral porous silicon etch dimension is comparable to the vertical porous silicon depth Tp.
[0071] It will be appreciated by those skilled in the art that the polysilicon resistor 30.1 can also be realised in parallel or serpentine configurations of the type shown in Figure 4 and Figure 5.
[0072] Figure 9 shows electrical current IR from an electrical power source 36 passing through the n-type resistive layer 22. Thermal energy which is dissipated in the resistor 22 generates heat for initiating the oxidant. The resistor 22 is thermally isolated from the substrate 12 due to the low thermal conductivity of the porous layer 14 and the impregnated oxidant 18. The advantage of this is that only a relatively small amount of electrical energy is needed to heat the oxidant near the porous layer surface 14.1 to its explosive temperature.
[0073] Since the p-type substrate and the n-type resistive layer 22 form a semiconductor pn junction (the porous layer 14 is still p-type doped), the device is a three terminal device. In this embodiment the pn junction should be reverse biased, with the potential of the power supply 36 as shown in Figure 9.
[0074] Figure 10 shows an embodiment in which resistive heating takes place in a two-terminal configuration. The current IR passes through the p-type substrate 12 and the n-type layer 22. A pn-junction 38 between the layer 14 and the layer 22 is forward biased by the power supply 36, giving a non-linear current-voltage characteristic. The total resistance consists of two series components, namely the resistance of the porous layer 14 impregnated with the oxidant 18, in series with the n-type resistance 22. The porous layer resistance should be higher than the n-type layer resistance, so that most of the heat is generated inside the porous layer 14, rather than at the porous layer surface 14.1 The resistance of the substrate 12 is negligible.
[0075] Figure 11 illustrates another two-terminal embodiment in which resistive heating will take place, but where the effect of the high resistance of the porous region 14 is substantially eliminated which may result in fairly high voltages that have to be applied to generate sufficient thermal energy. The porous layer 14 thickness TP and n-type layer 22 widths WN (see Figure 3) are chosen such that the porous region 14 does not laterally etch fully underneath the n-type layer 22. There is a p-type bulk substrate region 40 that is not porisified, forming a pn-junction 38 with the n-type surface layer 22. With the correct choice of dimensions, the resistance of the p-type region 40 can be made comparable to the n-type resistance 22. The power supply 36 will forward bias the pn junction 38, causing current IR to flow. If the two series resistors are of comparable value, heat is generated at the surface 14.1 and in the region 40, causing heat to be transferred to the impregnated oxidant 18. In a variation, a number of regions 40 can be etched in parallel, with the result that heat will be transferred more uniformly to the oxidant throughout the porous region 14.
[0076] In this case there is not complete thermal isolation between the n-type layer 22 and the substrate 12, since the resistive bulk region 40 can conduct heat to the substrate. By making the regions 40 very narrow, thermal conductance via the region 40 can however be made small.
[0077] Figure 12 illustrates an embodiment in which the resistive layer 30 is placed on the surface 14.1. The electrical current IR flows through the resistive layer 30 from an electrical power supply 36 and electrical energy which is dissipated in the resistor 30 generates heat. The resistor 30 is thermally isolated from the substrate 12 due to the low thermal conductivity of the porous layer 14 and the impregnated oxidant 18. The advantage of this is that a relatively small amount of electrical energy is needed to heat the oxidant near the surface 14.1 to the explosive temperature of the oxidant.
[0078] Since the substrate 12 is in electrical contact with the resistive layer 30, current will also flow through the relatively high resistance of the porous layer 14 filled with the oxidant 18. The substrate 12 can be left open circuit, or can be connected to a common terminal as is shown in Figure 12.
[0079] It will be appreciated by those skilled in the art that the device in Figure 12 can also be realised using opposite and complementary doping levels.
[0080] Figure 13 shows a two-terminal embodiment of the detonating device with a resistive layer 30 on the porous layer surface 14.1. The resistive layer 30 is electrically isolated from the surface 14 by an isolation layer 32. The substrate 12 is electrically isolated from the resistive layer 30 and need not be terminal.
[0081] Figure 14 shows an example of the invention in which a high electric field mechanism is used to generate heat in the device. Two n-type regions 22 are placed at the surface 14.1 with an intermediate section 42 of width DN between the regions.
A voltage source 36 generates a voltage across the section 42. The electric field across the section 42 is a function of the applied voltage and the dimension DN. When a certain critical electric field value is exceeded, breakdown occurs and a current flows from one n-type region to the other across the section 42. The applied voltage at which this breakdown will occur depends on the dimension DN, and on the critical breakdown electric field strength of the porous layer 14 filled with the oxidant 18. The pn-junction formed between the n-type layers 22 and the substrate 12 must be reverse biased, as shown. [0082] Breakdown can also occur just outside the surface 14.1 in a region 44 which covers at least the section 42 and which can be of any material (gas, vacuum, solid or liquid) with dielectric properties. At a certain critical electric field value this region 44 can also break down and pass current. With this type of breakdown mechanism, an electric spark can also be formed when the breakdown current flows. This means that the energy supplied to the oxidant 18 can be in the form of normal electrical power dissipation through the section 42 or the region 44, converting the electrical energy into heat, and via an electrical spark contributing to heat generation.
[0083] Figure 15 shows an embodiment in which electrodes 46 are placed on the porous layer surface 14.1. The electrodes may be of conductor or semiconductor material, and are spaced a gap distance DL apart. A voltage source 36 generates a voltage across the region 44. The electric field across the region 44 is a function of the applied voltage from the source 36 and the distance DL and when this exceeds a critical value breakdown occurs and a current flows from one n-type region to the other across gap region 44. The applied voltage at which this breakdown will occur depends on the gap dimension DN, as well as on the critical breakdown electric field strength of the material filling the gap region 44. This type of breakdown mechanism may cause an electric spark when the breakdown current flows. This means that the energy supplied to the oxidant 18 can be in the form of normal electrical power dissipation through the region 44, converting the electrical energy into heat, and via an electrical spark contributing to heat generation. In certain cases breakdown may also occur through the porous section 42 filled with the oxidant 18.
[0084] When the electrode layer 46 is not isolated from the surface 14.1, current will also flow through the section 42, and may prevent breakdown from occurring in the region 44. To prevent current flowing through the section 42, the electrodes 46 can be isolated from the porous layer surface 14.1 by means of a thin isolation layer, similar to the structure shown in Figure 13 where the resistive layer 30 is isolated from the surface 14.1 by means of a relatively thin isolation layer 32.
[0085] Figure 16 depicts an embodiment in which a high electric field breakdown in the semiconductor is achieved via a pn junction which is reverse biased by the power supply 36. As soon as the critical electric field breakdown voltage (avalanche or field emission) of the junction is reached, a relatively high current IB flows through the pn junction 38. This junction will dissipate electrical power and heat will be generated in the porous layer 14 to initiate the impregnated oxidant 18. Since the junction 38 is close to the surface 14.1 , it is thermally isolated from the substrate 12 and is an efficient heat source. Due to the relatively high resistance of the porous material 14, heat is also generated in the porous material 14.
[0086] Figure 17 shows a similar embodiment to that of Figure 16. However the porous region 14 is not fully etched laterally underneath the n-type layer 22, with the result that the reverse biased pn junction 38 is formed in single crystal bulk material between the n-type layer 22 and the p-type bulk substrate 12 within the p-type region
40. The junction 38 is reverse biased by the power supply 36. This reverse breakdown should be under better control and also more repeatable since it occurs in well defined single crystal material. It is also possible to increase the p-type doping level in the p-region 40 locally using, for example, boron ion implantation. This type of local increase in doping level will lower the reverse breakdown of the pn junction 38 in the region 40 to relatively low voltage levels. Most of the electrical power is then dissipated in the junction 38, and not in the series resistance of the region 40.
[0087] In this case there is not complete thermal isolation between the n-type layer 22 and the substrate 12, since the resistive bulk region 40 will conduct heat to the substrate. By making the region 40 very narrow, the thermal conductance via the region 40 can however be made small.
[0088] Figure 18 shows an embodiment in which optical energy is supplied to the impregnated oxidant in the integrated detonator. Photons 50 from an external optical source are directed towards the surface 14.1 via an optical fibre 48. The photons are absorbed inside the porous material 14 and, if the optical signal has enough energy, the absorbed photons will cause heat to be transferred from the porous material 14 to the impregnated oxidant 18. For integration with other devices on the same substrate 12, masking techniques will be needed to protect some regions of the substrate surface 12.1 from the porous etch.
[0089] Figure 19 relates to an embodiment in which indirect use is made of optical energy to initiate the explosive 18. Incoming photons 50 are detected in the detonator structure, and a resultant photoelectric signal is used to initiate the oxidant 18. A reverse biased pn junction 38 is formed between the n-type surface layer 22 and the region 40. The dopant concentration in the region 40 may be increased to lower the reverse breakdown voltage of the junction 38 which is reverse biased by the power supply 36. The photons are absorbed inside the pn junction 38 depletion region, mostly inside the region 40, thus generating electron-hole pairs and increasing the reverse current IA. The increase in the reverse current IA results in an increase in electrical energy dissipation in the pn junction 38, thus generating heat which initiates the impregnated explosive 18.
[0090] In another embodiment, the power supply 36 biases the pn junction 38 to just below avalanche or field emission breakdown, and the photons absorbed in the pn junction depletion region then stimulate breakdown in the pn junction 38, causing avalanche or field emission to occur with resulting large reverse currents. This is analogous to the pn junction 32 acting as an avalanche photodiode (APD).
[0091] Figure 20 shows an embodiment in which an optical signal to initiate the oxidant 18 is generated internally on or in the same substrate 12 in which the porous region 14 was formed. If the substrate is a semiconductor, a pn junction 51 may be used as a source of the optical signal. A power supply 52 can be used to forward or reverse bias the pn junction 51. The optical signal emitted by the pn junction 51 can be directed towards the porous layer 14 by means of bulk transmission 54 i.e. directly through the substrate or via a surface optical wave guide 56.
[0092] Figure 21 depicts an embodiment in which an ultrasonic signal is generated on the substrate 12 which contains the porous material 14. An electric signal source 58 is applied across two or more electrodes 60 on the surface 12.1. If the substrate material is piezo-electric, surface and bulk acoustic waves 62 will be generated which are directed towards the porous material 14 and the embedded oxidant 18 is initiated.
[0093] Figure 22 illustrates an embodiment wherein a secondary energetic material 66 is initiated by propelling a high velocity projectile 64 with adequate kinetic energy into the energetic material 66. The oxidant 18 is initiated by one of the methods described hereinbefore. The force and energy of the primary explosion are transmitted in directions 68 towards the surface 14.1 and the projectile 64 is forced at a high velocity in a direction 70 towards the material 66. On impacting the sensitive secondary material, the projectile 64 will initiate the material 66.
[0094] By shaping the three-dimensional geometry porous material 14 (e.g. by using masking layers, masking techniques and differential porous etching techniques) the directions 68 of the force of the embedded explosive 18 can be guided to be not necessarily vertical to the surface 12.1, but at an angle to a vertical direction 70.
[0095] In this embodiment the projectile 64 is external to the substrate surface 12.1 and porous layer surface 14.1. There are many methods of placing a projectile on the surface, but one method may be the deposition or sputtering of a patterned, relatively thick metal layer (e.g. gold) on the surface. The projectile 64 may also be fixed to the surface 14.1 using an epoxy, and in this case the projectile 64 may be of any suitable material and of any suitable shape.
[0096] Figure 23 shows an embodiment in which a projectile 72 is integrated within the porous layer 14. Usually the material of the projectile 72 will be of the same base material as the substrate 12. However, in the case of a semiconducting substrate 12, the material of the projectile 72 and the material of the substrate 12 may be of different polarity (n- or p-type) and different doping levels. The secondary energetic material 66 is initiated by propelling the integrated high velocity projectile 72 with adequate kinetic energy into the energetic material 66. The embedded oxidant 18 within the porous layer 14 is initiated by one of the methods described hereinbefore. The force and energy of the primary explosion are directed towards the surface 14.1 and the projectile 72 is forced at a high velocity in the direction 70. On impacting the sensitive secondary material, the projectile 72 will initiate the material 66.
[0097] By shaping the geometry of the three-dimensional porous region 14 (e.g. using masking layers, masking techniques and differential porous etching techniques) the directions 68 of the force of the primary explosive 18 can be guided to be not. necessarily vertical to the substrate surface 12.1, but at an angle to the vertical direction 70. In this embodiment the projectile 72 is integrated into the surface 12.1 and the surface 14.1.
[0098] There are many methods of integrating a projectile into the substrate and porous layer, but one method makes use of an n-type masking layer (such as the masking layer 22 in Figure 3) using the differential etch rates of n- and p-type semiconductors to form the imbedded projectile 72 within the porous layer 14. In this example the projectile 72 will also perform the function of the masking layer (i.e. the layer 22 in Figure 3), and can also be used as a resistive element (see the resistive layer 22 in Figure 9) to generate heat in the porous layer 14, or as one side of a pn- junction (see for example Figure 10 in which a pn-junction 38 is formed between the n-type layer 22 and the porous layer 14.
[0099] Figure 24 shows an embodiment wherein the surface 12.1 is selectively etched to form a cavity 74 at the surface. The substrate is then etched to form porous silicon with two porous surfaces, namely a porous region surface 14.1 at the original substrate surface and a porous region surface 14.2 along slopes or sides of the cavity 74. When the impregnated oxidant 18 is initiated, the shape of the porous region 14 will concentrate the force of the explosion along a direction 70 towards the secondary sensitive material 66. The geometry of the cavity 74 determines the strength of the concentrated force, and if correctly configured increases the speed and kinetic energy of the material being propelled towards the secondary material 66.
This process is similar to the concept of shaped charges, concentrating the force of an explosion and increasing the kinetic energy of material being propelled, outwards from the cavity after initiation of the primary explosive.
[0100] In another variation of this application, a projectile can be placed inside the cavity 74. This projectile may be a metal layer deposited onto the surface 14.2, or an object which is placed inside the cavity 74. in silicon technology the projectile may also be polysilicon deposited inside the cavity 74.
[0101] Figure 25 depicts another embodiment wherein the substrate is processed from two sides, with an initiation device 22 formed on one substrate side 12.2, and the cavity 74 formed on the side 12.1. When the energy transfer device 22 generates heat, the oxidant 18 inside the porous region 14 is initiated and the geometry of the porous region surface 14.2 is such as to concentrate the force of the explosion along the direction 70 towards the secondary sensitive material 66. It will be appreciated that any of the other methods described hereinbefore may be used to initiate the oxidant 18 in this example.
[0102] Figure 26 shows an embodiment in which a pyrotechnic delay is integrated into the same substrate 12 as the primary explosive porous region 14 which consists of two geometries, namely a long and narrow porous region 76 and a region 78 with much larger volume. The region 76 will act as a pyrotechnic delay element, with the delay determined by the length LP of the region 76. The region 78 will act as the primary explosive region. An initiation device, in this case shown as a resistive n-type layer 22 (but it may be any of the energy transfer devices discussed hereinbefore) initiates the impregnated explosive 18 in the region 76. After a delay determined by the length LP, the reaction will reach the porous region 78, and then initiate the primary oxidant 18 in the region 78.
[0103] Figure 27 illustrates an embodiment in which the pyrotechnic delay element 76 is used to realise a programmable delay element. Several energy transfer devices or initiation sites 80.1 to 80.4 (in this embodiment only four are shown) can be used to initiate the reaction in the delay element 76. Each of the initiation sites 80.1 , 80.2, 80.3 and 80.4 has a different delay from the initiation site to the primary explosive porous region 78, as a result of different delay lengths from the initiation site to the primary porous region 78. The detonating device 10 can be made electrically- or mask-programmable by selecting the initiation site 80 to be activated, thus determining the delay of the pyrotechnic detonation. This selection can be made by electronic circuitry, or by mask-programming during the manufacturing phase. The programming may also be performed using fuses on the same substrate.
[0104] It will be appreciated that there are many variations can be made to the device and to the method of producing the device without departing from the scope and spirit of this disclosure.

Claims

1. A detonator device which includes a body of a porous material, an oxidant which is impregnated into the porous material, and means for supplying energy to the oxidant thereby to initiate the oxidant.
2. A detonator device according to claim 1 which includes a bulk substrate of a semiconductor material and at least one integrated circuit in the substrate, and wherein the body of porous material is selectively formed in one or more regions of the substrate.
3. A detonator device according to claim 2 which includes a protective layer on a surface of the substrate provided by a technique selected from: selective deposition or growth, a photolithographic technique, implanting or diffusing.
4. A detonator device according to claim 3 wherein the protective layer includes a material selected from silicon nitride, silicon dioxide, polycrystalline silicon or a combination of these materials.
5. A detonator device according to any one of claims 2 to 4 wherein at least one programmable pyrotechnic delay is integrated into the substrate.
6. A detonator device according to any one of claims 1 to 5 wherein the oxidant is selected from gadolinium nitrate and potassium nitrate and is impregnated into the porous material by immersing the porous material into a liquid containing the oxidant in solution, or by putting the liquid onto a surface of the porous material.
7. A detonator device according to any one of claims 1 to 6 wherein the energy which is supplied to the oxidant is in a form selected from the following: thermal energy, electrical energy, optical energy, infrared energy, electromagnetic energy, ultrasonic energy, magnetic energy, and acoustic energy.
8. A detonator device according to any one of claims 1 to 7 which includes a resistive electronic device formed as a resistive layer at a surface of the porous material or near the porous material.
9. A detonator device according to any one of claims 1 to 7 which includes a non-ohmic device at a surface of or in the porous material, or near to the porous material, which passes current only in one direction.
10. A detonator device according to any one of claims 1 to 9 which includes a secondary energetic material in close proximity to a surface of the porous material so that initiation of the oxidant inside the porous material initiates the secondary energetic material.
11. A method of making a detonating device which includes the steps of treating a substrate to form a porous structure, impregnating the porous structure at least partly with an oxidant and forming at least one arrangement which, when actuated, transfers heat to the oxidant to initiate the oxidant, integrally with the substrate.
PCT/ZA2005/000175 2004-11-24 2005-11-24 Detonator device WO2006058349A1 (en)

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WO2011140549A3 (en) * 2010-05-07 2013-01-17 Orica International Pte Ltd Method of blasting
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