WO2006048822A1 - Integrated circuit and method for providing guarantees at application level - Google Patents

Abstract

The invention relates to an integrated circuit and to a method for providing guarantees at application level in an integrated circuit, the integrated circuit comprising a plurality of modules coupled to an interconnect means for a transaction-based communication between each other via connections over the interconnect means. The invention relies on the concept that it is necessary to set up and configure separate connections for respectively write request messages, read request messages, data synchronization request messages and data synchronization response messages. If separate connections are deployed, they can be configured such that they provide a guaranteed performance. In this manner the communication behavior of the system as a whole becomes predictable.

Description

Integrated circuit and method for providing guarantees at application level

The invention relates to an integrated circuit, comprising a plurality of modules coupled to an interconnect means for a transaction-based communication between each other via connections over the interconnect means, wherein a first module is arranged to send write request messages to a shared resource, the first module further being arranged to send data synchronization request messages to a second module, wherein the second module is arranged to send read request messages to the shared resource, the second module further being arranged to send data synchronization response messages to the first module. The invention also relates to a method for providing guarantees at application level in an integrated circuit, the integrated circuit comprising a plurality of modules coupled to an interconnect means for a transaction-based communication between each other via connections over the interconnect means, the method comprising the steps of: sending write request messages from a first module to a shared resource, and sending data synchronization request messages from the first module to a second module; sending read request messages from the second module to the shared resource, and sending data synchronization response messages from the second module to the first module.

The concept of buffering is used within the area of streaming applications to adjust or compensate for different rates of data production and data consumption. Typically, such systems are modeled using the so-called Kahn process network KPN model as described in G. Kahn, "The semantics of a simple language for parallel programming, in information proceeding", J. L. Rosenfeld, 1974. Possible implementations of these KPN models are C- HEAP as described by Om Prakash Gangwal, Andre Nieuwland, and Paul Lippens, "A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems", In ISSSOl (International Symposium on system synthesis), 2001 or ECLIPSE as described M. J. Rutten, J. T. J. van Eijndhoven, E. J. D. Pol, E. G. T. Jaspers, P. van der Wolf, O. P. Gangwal, A. Timmer, "Eclipse: a heterogeneous multiprocessor architecture for flexible media processing", IEEE Design and Test of Computers vol. 19, no. 4, pp. 39-50, July- Aug. 2002. The underlining ideas of these methods are to separate the data transfer and the data synchronization between producers and consumers of data. Accordingly, the granularity of data transfers and the respective synchronization between the producer and consumer is made independent which is advantageous in the case of video processing applications where synchronization points may range widely from one block of 8x8 pixels to one field or one frame. A typical synchronization action consists of updating administrative information regarding the produced or consumed data and forwarding a signal to the respective consumer or producer. A memory for this administrative information may be provided centrally as a shared memory or distributed at places adjacent to the producer and/or consumer.

According to C-HEAP the data information and the administrative information within bus-based systems will be placed centrally within a shared memory as shown in Fig. L A data transfer between a producer P and a consumer C is performed via the bus B and the shared memory M, i.e. there is no direct data transfer between the producer and the consumer while the synchronization signals Sl, S2 are directly transferred between the producer and the consumer. In other words, the data transfer actions Dl, D2 and the signaling actions Sl, S2 are separated. Due to the nature of the shared infrastructure, the single shared bus, the data transfer actions and the signaling actions occur within a specified order, i.e.

Dl- >S1— >D2— >S2. The producer P writes data Dl into the memory M and issues a signaling action Sl to the consumer to notify the consumer that there is data present in the memory M. Thereafter, the consumer C accesses the memory by the data transfer action D2 in order to read the memory. When the data Dl previously written into the memory M by the producer P has been read or has been accessed by the consumer C, a respective signaling action S2 is issued directly to the producer P via the shared bus B in order to notify the producer P that the data has been read or accessed by the consumer. It is noted that predictability and guarantees at application level and data transfer level are not mentioned at all.

As an alternative for bus-based communication the concept of a network is gaining importance. A communication network on an integrated circuit, which is often referred to as a Network-on-Chip (NoC), comprises a collection of nodes (e.g. routers) and connections between these nodes. The modules are typically connected to the network via so- called network interfaces. A network interface has (among other tasks) the task of splitting messages to be sent over the network into packets. These packets have the correct format for transport via the network. The packets typically comprise a header, a tail and a payload. The payload comprises the data which should be transported via the network from a first module to one or more second modules.

It has been found that when using the above-mentioned concept to separate data transfer from data synchronization in a Network-on-Chip environment, it is not possible to guarantee the communication behavior of the system. In particular, performance guarantees (such as throughput guarantees) at application level cannot be provided.

It is an object of the invention to provide performance guarantees at application level in a network-on-chip of the kind set forth, even if data transfer operations and data synchronization operations have been separated. This object is achieved by providing an integrated circuit as claimed in claim 1 and a method as claimed in claim 5.

The invention relies on the concept that it is necessary to set up and configure separate connections for respectively write request messages, read request messages, data synchronization request messages and data synchronization response messages. If separate connections are deployed, they can be configured such that they provide a guaranteed performance. In this manner the communication behavior of the system as a whole becomes predictable. In an embodiment of the invention as defined in claim 2, the interconnect means is arranged to provide guaranteed throughput for the separate connections. In this manner throughput guarantees can be provided for the complete cycle of data transfer and data synchronization, thus providing throughput guarantees at application level. In other words, guarantees at network level which do not take into account the interrelationship of certain messages (such as data transfer/synchronization) can be translated to guarantees at the application level.

In a further embodiment of the invention as claimed in claim 3, the shared resource is arranged to acknowledge the receipt of the write request messages. In a yet further embodiment of the invention as claimed in claim 4, the data comprised in the write request messages includes a tag, and the shared resource is arranged to acknowledge the receipt of the write request messages via a tag acknowledge message. This mechanism can be deployed to make sure that data has reached the shared resource before a data synchronization message is sent to another module. The present invention is described in more detail with reference to the drawings, in which:

Fig. 1 illustrates a basic block diagram of a bus-based system according to the prior art;

Fig. 2 illustrates a basic arrangement of a Network-on-Chip (NoC) environment;

Fig. 3 illustrates a basic block diagram of a Network-on-Chip (NoC) environment according to the invention.

Fig. 1 illustrates a basic block diagram of a bus-based system according to the prior art. The concept of separation of data transfer operations and data synchronization operations in such a bus-based system has been introduced, but it is interesting to note that predictability and guarantees at application level and data transfer level are not recognized as a problem. In a Network-on-Chip environment, interrelated data transfer messages and data synchronization messages are transmitted via a complex network to their destinations, and without additional measures it is for example not possible to guarantee the throughput for a complete cycle of data transfer requests/responses and data synchronization requests/responses.

The following embodiments relate to systems on chip, i.e. a plurality of modules on a single chip or on multiple chips communicate with each other via some kind of interconnect. The interconnect is embodied as a network on chip NoC. The network on chip may include wires, bus, time-division multiplexing, switches, and/or routers within a network. At the transport layer of said network, the communication between the modules is performed over connections. A connection is considered as a set of channels, each having a set of connection properties, between a first module and at least one second module. For a connection between a first module and a single second module, the connection comprises two channels, namely one from the first module to the second module, i.e. the request channel, and a second channel from the second module to the first module, i.e. the response channel. The request channel is reserved for data and/or messages from the first to the second, while the response channel is reserved for data and/or messages from the second to the first module. However, if the connection involves one first and N second modules, 2*N channels are provided. The modules as described in the following can be so-called intellectual property blocks IPs (computation elements, memories or subsystems which may internally contain interconnect modules) that interact with network at network interfaces NI. A network interface NI can be connected to one or more IP blocks. Similarly, an IP can be connected to more than one network interfaces.

Fig. 2 shows a basic arrangement of a Network-on-Chip environment. In particular, a master module MA and a slave module SL each with an associated network interface NI are depicted. Each module MA, SL is connected to a network N via its associated network interface NI, respectively. The network interfaces NI are used as interfaces between the master and slave modules MA, SL and the network N. The network interfaces NI are provided to manage the communication between the respective modules MA, SL and the network N, so that the modules can perform their dedicated operation without having to deal with the communication with the network or other modules. The network comprises a plurality of interconnected routers R. The routers R serve to forward packets (commands and data) to the next router R or to a network interface NI. For more details on a router architecture please refer to Rijpkema et al, "A Router Architecture for Networks on Silicon", Proceedings of Process 2001, 2nd Workshop on Embedded Systems, or "Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services For Networks on Chip", by Rijpkema et al in Design, Automation and Test in Europe Conference and Exhibition (DATE'03) March 03 - 07, 2003 Munich, Germany.

The network interfaces NI are designed to provide services at the transport layer in the OSI reference model as it represents the first layer with services which are independent of the network implementation. This improves the decoupling between the computation and the communication allowing the IP blocks and the network to be designed independently from each other. Transport layer services are provided by defining connections like a point-to-point connection or a multicast connection with specific properties, e.g. throughput, ordering etc.

The communication between the IP blocks over the network is performed on the basis of a transaction-based protocol. Here, the master IP block issues a request message which is executed by the slave IP block as addressed in the request message. The slave IP block can respond with a response message. The request message may constitute write or read commands at an address and possibly data. The response message may indicate the status of the command execution like an acknowledgement of the transaction execution and possibly also some data. The network interface NI is designed to convert the packet-based communication of the network to the higher level protocol of the IP modules. The network interface NI mainly comprises a network interface kernel and a network interface shell. The kernel packetizes the messages and schedules them to the routers. The shell implements the connections, transaction ordering and higher-level issues which are specific to the protocol of the IP module. The shell sequentializes commands and flags, addresses and write data in request messages and desequentializes messages into read data and write responses.

The signals to be transferred over the network are sequentialized into request and response messages which are supplied to the network and transported as packets. Each packet consists of several flits, which constitute the minimal transmission unit. This packetization is performed by the network interface and is therefore transparent to the IP modules. The communication over the network N is performed via connections. These connections may be uni-cast (i.e. one master, one slave), multicast, (i.e. one master, multiple slave each slave execute each transaction), and narrowcast connections (i.e. one master, multiple slaves the transaction is executed by only one slave).

Fig. 3 illustrates a basic block diagram of a Network-on-Chip (NoC) environment according to the invention. The network is configured such that the write request messages, the read request messages, the data synchronization request messages and the data synchronization response messages are sent via separate connections. Each connection can be configured such that is provides guaranteed performance, for example a guaranteed throughput value. Throughput is defined as the maximum amount of data which can be transmitted in a unit of time. The implementation of connections with guaranteed performance can be found in "An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration", by A. Radulescu et al., Design, Automation and Test in Europe (DATE '04), Paris, February 2004. If guaranteed throughput for a communication over the Network-on-Chip NoC is to be implemented at application level, two separate guaranteed throughput connections (one for the data transfer Dl and one for the data synchronization Sl) are required: between the producer P and the memory M, respectively between the producer P and the consumer C. Furthermore, two separate guaranteed throughput connections (one for the data transfer D2 and one for the data synchronization S2) are required: between the consumer C and the memory M, respectively between the consumer C and the producer P.

It is noted that other performance parameters, for example maximum latency, can also be configured for the separate connections. The invention is not limited to throughput guarantees. The memory M is just an example of a shared resource; the resource may be of another kind or it may be another module in the system.

One side effect of using separate connections for data transfer and data synchronization is the following. The producer P has to make sure that first the data Dl reaches the memory M before it can send the data synchronization message S 1 to the consumer C. This requires a mechanism like tagging data Dl and waiting for the response (i.e. tag acknowledge) from the memory M to make sure that the data has reached the memory M. Therefore, in an embodiment of the invention the shared resource M is arranged to acknowledge the receipt of the write request messages. In a further embodiment of the invention the data comprised in the write request messages comprises a tag, and the shared resource M is arranged to acknowledge the receipt of the write request messages via a tag acknowledge message. The tag acknowledge mechanism may introduce some latency, but when guaranteed services are used all latencies can be derived with exact values.

In the above embodiments the principles of the invention have been described on the basis of transferring data and sending associated synchronization signals. However, the principles of the invention are also applicable to other kinds of interrelated messages which are sent over the connections.

It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Neither is the scope of protection of the invention restricted by the reference symbols in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)' preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed general- purpose processor. The invention resides in each new feature or combination of features.

Claims

CLAIMS:

1. An integrated circuit, comprising a plurality of modules (P, C; MA, SL) coupled to an interconnect means (N) for a transaction-based communication between each other via connections over the interconnect means (N), wherein a first module (P) is arranged to send write request messages to a shared resource (M), the first module (P) further being arranged to send data synchronization request messages to a second module (C), wherein the second module (C) is arranged to send read request messages to the shared resource (M), the second module (C) further being arranged to send data synchronization response messages to the first module (P), characterized in that the interconnect means (N) is arranged to send the write request messages, the read request messages, the data synchronization request messages and the data synchronization response messages via separate connections, and wherein the interconnect means (N) is arranged to provide guaranteed performance for the separate connections.

2. An integrated circuit as claimed in claim 1, wherein the interconnect means

(N) is arranged to provide guaranteed throughput for the separate connections.

3. An integrated circuit as claimed in claim 1, wherein the shared resource (M) is arranged to acknowledge the receipt of the write request messages.

4. An integrated circuit as claimed in claim 3, wherein the data comprised in the write request messages includes a tag, and the shared resource (M) is arranged to acknowledge the receipt of the write request messages via a tag acknowledge message.

5. A method for providing guarantees at application level in an integrated circuit, the integrated circuit comprising a plurality of modules (P, C; MA, SL) coupled to an interconnect means (N) for a transaction-based communication between each other via connections over the interconnect means (N), the method comprising the steps of: sending write request messages from a first module (P) to a shared resource (M), and sending data synchronization request messages from the first module (P) to a second module (C); sending read request messages from the second module (C) to the shared resource (M), and sending data synchronization response messages from the second module (C) to the first module (P); characterized in that the write request messages, the read request messages, the data synchronization request messages and the data synchronization response messages are sent via separate connections, the separate connections having guaranteed performance.