WO2006039713A3 - Configurable computing machine and related systems and methods - Google Patents

Configurable computing machine and related systems and methods Download PDF

Info

Publication number
WO2006039713A3
WO2006039713A3 PCT/US2005/035818 US2005035818W WO2006039713A3 WO 2006039713 A3 WO2006039713 A3 WO 2006039713A3 US 2005035818 W US2005035818 W US 2005035818W WO 2006039713 A3 WO2006039713 A3 WO 2006039713A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
computing machine
processor
pipeline
operable
Prior art date
Application number
PCT/US2005/035818
Other languages
French (fr)
Other versions
WO2006039713A9 (en
WO2006039713A2 (en
Inventor
John Rapp
Scott Hellenbach
Chandan Mathur
Mark Jones
Joseph A Capizzi
Troy Cherasaro
Original Assignee
Lockheed Corp
John Rapp
Scott Hellenbach
Chandan Mathur
Mark Jones
Joseph A Capizzi
Troy Cherasaro
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lockheed Corp, John Rapp, Scott Hellenbach, Chandan Mathur, Mark Jones, Joseph A Capizzi, Troy Cherasaro filed Critical Lockheed Corp
Publication of WO2006039713A2 publication Critical patent/WO2006039713A2/en
Publication of WO2006039713A9 publication Critical patent/WO2006039713A9/en
Publication of WO2006039713A3 publication Critical patent/WO2006039713A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that compose the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often 'fit' the circuit into the pipeline accelerator regardless of its composition. A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power. According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the oineline scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra 'space' than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.
PCT/US2005/035818 2004-10-01 2005-10-03 Configurable computing machine and related systems and methods WO2006039713A2 (en)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US61515704P 2004-10-01 2004-10-01
US61519304P 2004-10-01 2004-10-01
US61515804P 2004-10-01 2004-10-01
US61519204P 2004-10-01 2004-10-01
US61505004P 2004-10-01 2004-10-01
US60/615,192 2004-10-01
US60/615,158 2004-10-01
US60/615,050 2004-10-01
US60/615,157 2004-10-01
US60/615,193 2004-10-01
US60/615,170 2004-10-01

Publications (3)

Publication Number Publication Date
WO2006039713A2 WO2006039713A2 (en) 2006-04-13
WO2006039713A9 WO2006039713A9 (en) 2006-08-17
WO2006039713A3 true WO2006039713A3 (en) 2006-09-28

Family

ID=36143162

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/035818 WO2006039713A2 (en) 2004-10-01 2005-10-03 Configurable computing machine and related systems and methods

Country Status (1)

Country Link
WO (1) WO2006039713A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7418574B2 (en) 2002-10-31 2008-08-26 Lockheed Martin Corporation Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction
US7676649B2 (en) 2004-10-01 2010-03-09 Lockheed Martin Corporation Computing machine with redundancy and related systems and methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704816B1 (en) * 1999-07-26 2004-03-09 Sun Microsystems, Inc. Method and apparatus for executing standard functions in a computer system using a field programmable gate array
US20040181621A1 (en) * 2002-10-31 2004-09-16 Lockheed Martin Corporation Computing machine having improved computing architecture and related system and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704816B1 (en) * 1999-07-26 2004-03-09 Sun Microsystems, Inc. Method and apparatus for executing standard functions in a computer system using a field programmable gate array
US20040181621A1 (en) * 2002-10-31 2004-09-16 Lockheed Martin Corporation Computing machine having improved computing architecture and related system and method

Also Published As

Publication number Publication date
WO2006039713A9 (en) 2006-08-17
WO2006039713A2 (en) 2006-04-13

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