WO2006035500A1

WO2006035500A1 - Data storage system and memory card

Info

Publication number: WO2006035500A1
Application number: PCT/JP2004/014228
Authority: WO
Inventors: Shinichi Suzuki
Original assignee: Renesas Technology Corp.
Priority date: 2004-09-29
Filing date: 2004-09-29
Publication date: 2006-04-06
Also published as: JPWO2006035500A1

Abstract

In an illustrative case of updating the memory content at a target end, which is now, for example, 5A'h, to 5B'h via data transmission from an initiator to the target, the initiator transmits, to the target, data of 01'h indicating whether an updating is to be performed per bit (a bit to be updated is '1' and a bit not to be updated is '0'). When receiving the data of 01'h, the target retrieves, from among the data of its own memory contents, and reverses the data of the bit (in this case, the last bit) corresponding to a bit to be updated, and then restores the data as reversed.

Description

Specification

Data storage system and memory card

Technical field

The present invention relates to a data storage system and a memory card, and in particular, is effective when applied to a data storage system including a storage device typified by a memory card and an initiator for reading and writing data to and from the storage device. It is about technology.

Background art

According to a study by the present inventor, the following technologies can be considered as the data storage system.

[0003] For example, various memory card standards such as SD (Secure Digital) memory card and Memory Stick (registered trademark), network type communication type such as USB (Universal Serial Bus) and IEEE (the Institute of Electrical and Electronics Engineers) 1394 Data transfer on the bus is performed using raw data, which is not particularly optimized in the serial bus standards that take the state and storage-related standards such as ATA (AT Attachment) and SCSI (Small Computer System Interface) .

That is, for example, data transfer as shown in FIG. 6 is performed. FIG. 6 is a diagram for explaining an example of the data transfer system in the conventional data storage system examined as a premise of the present invention. (A) is a simplified diagram of the system configuration, and (b) is a diagram of the system configuration. It is an operation | movement flowchart. In FIG. 6, the data transmission side is the initiator 60, the reception side is the target 61, and the initiator 60 has a value of 5A'h (hexadecimal "5A", the same notation is used hereinafter) of the target 61. In this example, 1-byte data A (= 5B'h) is written to N space (N is an integer greater than or equal to 0). In this case, the following processing (1) -1 (6) is performed.

(1) The initiator 60 sets a write start address (= N) and a write size (= 1 byte) in the target 61, and transmits a write command.

(2) When the target 61 receives a write command from the initiator 60, the target 61 prays the content and extracts the write address and size.

[0007] (3) After extraction, the target 61 prepares to receive data from the initiator 60. (4) The initiator 60 transmits raw data A (= 5B, h) to the target 61.

(5) The target 61 receives data A from the initiator 60.

[0010] (6) The target 61 updates its corresponding memory space (here, 1 byte from address N) to data A.

Disclosure of the invention

Problems to be solved by the invention

[0011] By the way, as a result of examination of the data storage system technology as described above by the present inventors, the following has been clarified.

[0012] For example, in the data transfer method as described in FIG. 6, since raw data is transferred between the initiator and the target, the change in the data content of the corresponding address is particularly noticed before and after the transfer. In the case where the number is small, for example, the following problems occur.

(1) On the target side, when the received data is written and updated in its own memory or register, if all are overwritten, power and time are wasted. In addition, in the data bus, the logic signals of 'L' and 'L' change frequently, causing noise and wasted power.

[0014] (2) Therefore, a method of updating data by focusing only on the bit to be updated on the target side can be considered, but it takes time to detect the bit to be updated. In other words, the efficiency of data update is improved by using a method that inverts only the bits that need to be updated. However, when this method is applied, it is necessary to compare the contents of the memory before update with the contents of the raw data when detecting the bit to be inverted based on the raw data.

[0015] (3) In general, memory is often accessed by system software such as a device driver. Since system software is written in a language suitable for bit operations, such as assembler language or C language, handling raw data is not efficient.

Accordingly, an object of the present invention is to provide a data storage system and a memory card capable of improving the time efficiency when storing data.

[0017] Another object of the present invention is to provide a data storage system and a memory card that can save power when data is stored.

[0018] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for solving the problem

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0020] A data storage system according to the present invention includes: a second controller that transmits first data having different signal levels when data inversion is required and data holding is required; And a target for receiving the first data and updating the second data by inverting or holding the second data based on the signal level of the first data.

[0021] That is, when updating the target memory or the like, the data already stored in the target memory or the like that is not updated by transmitting raw data to the target as in the prior art is stored. Update is performed by transmitting information about whether to invert. As a result, in the target memory etc., for example, the process of overwriting and updating 'H' data to 'H' data or 'L' data to 'L' data can be reduced, and the write time can be reduced. Efficiency and write power efficiency can be improved.

[0022] Here, examples of the target include a storage device.

[0023] A data storage system according to the present invention includes an initiator that transmits data and a target that receives the transmitted data. Then, the initiator corresponds to the first signal level and the second signal level for the bit that needs to be inverted and the bit that does not need to be inverted for the second data of multiple bits stored in the target. The plurality of bits of the first data is formed, and the plurality of bits of the first data is transmitted to the target. On the other hand, the target receives first data of a plurality of bits, detects a bit corresponding to the first signal level from the received first data of the plurality of bits, and detects the second data of the plurality of bits. Thus, the storage of the second data is updated by inverting the bit data corresponding to the detected bit.

That is, for example, when writing 1-byte data to the target memory or the like, there is a bit having the first signal level among 8 bits in the 1-byte. In the event of a failure, the bit data in the memory corresponding to that bit is inverted, and the data in the memory is updated. [0025] Here, in the target, for example, a system software process is performed using a computer provided in the target, and the system software process is performed for each bit signal for a plurality of bits of first data. Only when the signal level of the determined bit and the determined signal level is the first signal level, the bit data corresponding to the determined bit is read from the second data of the plurality of bits, And the step of reversing the read data and writing it back.

That is, the signal level of data received by the target is determined by processing of system software such as a device driver, and based on the determination result! Realize the function to control writing to the memory.

[0027] Further, the memory card according to the present invention receives a command including a write address and data assigned with different signal levels corresponding to inversion or holding of data, from the initiator. The data stored in the write address is updated by inverting or holding the data stored in the write address based on the signal level of the input data.

[0028] Here, examples of the memory card include an SD memory card and an MMC card. In this case, a new write command to a block or a plurality of blocks may be provided as the command by using a protocol similar to a write command to a block or a plurality of blocks generally provided in such a memory card.

The invention's effect

[0029] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0030] Initiator power The time required to store data by transferring data with different signal levels depending on whether the data in the target memory or the like is inverted and held toward the target. Efficiency can be improved. In addition, it is possible to save power when storing data.

Brief Description of Drawings

FIG. 1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention. FIG. 2 is a conceptual diagram for explaining a data transfer method between an initiator and a target in comparison with the prior art in the data storage system according to the embodiment of the present invention.

FIG. 3 is a diagram showing an example of the operation of the data storage system according to the embodiment of the present invention, where (a) is a simplified diagram of the system configuration and (b) is an operation flow diagram.

[FIG. 4] In the data storage system according to the embodiment of the present invention, the system software processing of the target is compared between the case of using the conventional data transfer method and the case of using the data transfer method of the present invention. (A) is an example of a processing flow when using the prior art, and (b) is an example of a processing flow when using the present invention.

FIG. 5 is an explanatory diagram showing an example of a command specification of a memory card defined when a memory card is used as a target in the data storage system of one embodiment of the present invention;

(a) shows a specification example of CMD60, and (b) shows a specification example of CMD61.

FIG. 6 is a diagram for explaining an example of the data transfer system in the prior art data storage system examined as a premise of the present invention, (a) is a simplified diagram of the system configuration, and (b) Is an operation flow diagram. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

FIG. 1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention. The data storage system shown in FIG. 1 includes an initiator 10 that transmits data and a target 11 that receives data, and the initiator 10 and the target 11 are connected by a communication network 12. Examples of the initiator 10 and the target 11 include a memory card host device, a USB device, or an IEEE 1394 device.

[0034] The initiator 10 and the target 11 have the same configuration, and include, for example, an application 13a, a file system 13b, a device driver 13c, an interface controller 13d, a memory and / or a register, and the like. Including the storage unit 13e Of

[0035] The application 13a is software including, for example, an explorer having a function of operating folders and files, an audio player having a function of reproducing music data, and the like. The file system 13b is system software that converts data input / output via the device driver 13c into a file so that processing can be performed by the application 13a, for example. Specific examples include those conforming to FAT (File Allocation Table) such as FAT16 and FAT32. The device driver 13c is software that performs control of the interface controller 13d, management of transactions and command sequences, and the like.

Although not shown in FIG. 1, the initiator 10 and the target 11 include, for example, a computer such as a microphone processor, and thereby the software as described above is executed. In addition, the software described above may be configured with an OS including a file system, an application, and a device driver when the initiator 10 and the target 11 are PCs (Personal Computers) or the like.

[0037] The interface controller 13d is hardware that performs command transmission, response reception, data transmission / reception, and the like via the communication network 12 in which the initiator 10 and the target 11 are connected. Examples of the communication network 12 include a wiring line to a memory card, a USB cable, an IEEE1394 cable, and the like, and data transfer is performed on the communication network 12 by an electrical signal. The memory of the storage unit 13e stores, for example, files and data necessary for the system, and the register is used for specific purposes such as device operation control.

[0038] Further, the data transfer between the initiator 10 and the target 11 is not necessarily performed using a wired communication network. For example, the interface controller 13d may be a wireless controller and the data may be transferred wirelessly. .

[0039] In such a system configuration, the feature of the present invention is that the device driver 13c and the interface controller 13d are provided with new functions to support a new data transfer method as shown in FIG. is there. FIG. 2 shows a conventional technique for transferring data between an initiator and a target in a data storage system according to an embodiment of the present invention. It is a conceptual diagram for demonstrating compared with a technique.

In FIG. 2, for example, it is assumed that the memory content on the target side is 5A′h, and the memory content is updated to 5B′h by data transfer from the initiator to the target. First, in the prior art, the initiator power is also transferred to the target as raw data (5B, M Binary "01011011") and overwritten and stored in the memory content B'h on the initiator side.

On the other hand, in the present invention, data indicating the presence / absence of update for each bit is transferred toward the target with the initiator power. That is, in Fig. 2, if '1' ('H, level) is set to the bit with update and' 0, ('L, level) is set to the bit without update, only the last bit is updated. Therefore, the data of 01'h is transferred. Then, the target side receives the data of 0 l 'h, inverts the data of the bit (here, the last bit) corresponding to the bit with the intermediate update of the data in its own memory and stores it again.

[0042] Normally, data is allocated to memory and registers in various memory card standards for SD memory cards, memory sticks, etc., serial bus standards such as USB and IEEE1394, and storage standards such as ATA and SCSI. There is a one-to-one correspondence with the specified address. Access to memory and registers is handled as a bitmap image.

Therefore, the data is considered as a bitmap image, and the bit updated (inverted) by data transfer is changed to “1”, and the bit holding the value as it is is changed to “0”. Then, data having bit information to be updated (inverted) is transferred to the target. As a result, when there is little change in the data contents, it is easy to update the value of the memory or register in units of bits, and it is possible to improve the efficiency of data update. Specifically, for example, the following effects can be obtained.

(1) When the received data is written and updated in its own memory or register, it is easy and efficient to detect bits that need to be updated, and processing can be performed at high speed. Furthermore, when writing and updating, it is only necessary to write only the bits that need to be updated. Therefore, for example, the number of bits that need to be updated is small! / In some situations, the writing time can be shortened compared to the case where all bits are overwritten and updated, and the power associated with writing can be saved. [0045] (2) In the data bus, the frequency with which the logic signal changes can be reduced, so that generation of noise and unnecessary power can be suppressed.

[0046] (3) Since data suitable for bit operation is received, processing by the system software can be performed efficiently.

[0047] (4) Time to write and update received data is reduced, and this time can be allocated to other functions of the product (decoding multimedia data, etc.).

(5) As a whole system including the initiator and the target, it is possible to save power. In addition, the system development period (especially software) can be shortened.

It should be noted that such an effect becomes more significant as the number of locations to be updated in the transferred data is smaller. In general, when updating and saving sentences, there are few parts to be updated. Therefore, it is particularly useful when applied to storage devices such as USB flash memory and ATA connection hard disks.

Further, the present invention is not limited to this, and the present invention can be applied to all products in which the data to be transferred and the corresponding addresses of the memory Z register are associated one-to-one. In particular, the system area of the file system is updated in units of sectors (512 bytes, etc.), and only a few bytes are updated, and the one-to-one correspondence described above is provided. ing. Therefore, the effect becomes large when applied to a product having such a file system.

[0051] Next, an example of the operation of the entire data storage system using the data transfer method as described above will be described with reference to FIG. FIG. 3 is a diagram showing an example of the operation of the data storage system according to the embodiment of the present invention. (A) is a simplified diagram of the system configuration, and (b) is an operation flow diagram.

[0052] In Figs. 3 (a) and 3 (b), 1 byte of data A (= = N) in the memory space with the values of 5A and h in the initiator 30 force target 31 (N is an integer greater than or equal to 0) It is assumed that 5B 'h) is written. Hereinafter, the operation will be described with reference to the numbers in FIG.

(1) The initiator 30 sets a write start address (= N) and a write size (= 1) to the target 31 and transmits a write command.

(2) When the target 31 receives the write command from the initiator 30, the target 31 prays the content and extracts the write address and size. (3) After extraction, the target 31 prepares to receive data from the initiator 30.

(0056) Initiator 30 transmits data A ′ (= 01′M binary number “00000001”) having information of bits that need to be updated to target 31. In this case, there is less data change ('0' → '1' or '1, →' 0,) than when transferring raw data A (= 5B'h (binary number "01011011"))! /, So data bus noise can be suppressed.

(5) The target 31 receives the data A from the initiator 30.

(6) The target 31 updates its corresponding memory to data A. When updating this data, it is possible to use a method that inverts only the bits that need to be updated. The data A 'itself contains information on the bits that need to be updated, so it is possible to use this updating method easily. become.

That is, by using the data transfer method of the present invention, the system software processing power on the target side associated with such an updating method becomes easy and efficient as shown in FIG. FIG. 4 shows the target system software processing in the data storage system according to the embodiment of the present invention when the conventional data transfer method is used and when the data transfer method of the present invention is used. It is a figure to compare, (a) is an example of the processing flow at the time of using a prior art, (b) is an example of the processing flow at the time of using this invention.

[0060] Here, the case where the contents of address N of target 31 (= data N) are updated will be described as an example. First, in the prior art, the processing flow is as shown in FIG. 4 (a), for example, and the following processing is performed.

[0061] In S401a, the target 31 receives data A. Then, control goes to S402a.

In S402a, data N is extracted from the memory of the target 31 for updating data at address N. Then, the process proceeds to S403a.

[0063] S403a Kokoo! /, Initializes the bit extraction counter. And move on to S404a

[0064] In S404a, the I-th bit of data A is taken out and is designated as A [I]. Then, the process proceeds to S405a.

In S405a, the I-th bit of data N is taken out and is designated as N [I]. Then, control goes to S406a. [0066] In S406a, it is compared whether N [I] and A [I] are different from each other. If they are different, the process proceeds to S407a. Otherwise, the process proceeds to S408a.

[0067] In S407a, if they are different from each other as a result of comparison, in the target memory

The data corresponding to the I bit at address N is inverted. Then, the process proceeds to S408a.

In S408a, it is determined whether or not the bit extraction counter is effective. S if valid

The process proceeds to 409a, and otherwise ends.

In S409a, if the bit extraction counter is valid, it is incremented by one. Then, move to S404a and repeat the process.

On the other hand, in the present invention, for example, the processing flow as shown in FIG. 4B is performed, and the following processing is performed.

In S401b, the target 31 receives data A. Then, the process proceeds to S403b.

In S403b, a bit extraction counter is initialized. Then, the process proceeds to S404b.

[0073] In S404b, the I-th bit of data A is extracted and is designated as A, [I]. Then, the process proceeds to S4 06b.

In S406b, it is determined whether or not A ′ [I] is “1”. If so, the process proceeds to S407b. Otherwise, the process proceeds to S408b.

If the determination result is “1” in S407b, the data corresponding to the I-th bit of the Nth address in the memory of the target 31 is inverted. Then, the process proceeds to S408b.

In S408b, the bit extraction counter determines whether or not the force is effective. If it is valid, the process proceeds to S409b, and if not, the process ends.

In S409b, if the bit extraction counter is valid, it is incremented by one. Then, move to S404b and repeat the process.

As described above, by using the data transfer method of the present invention, the process of extracting the data N of S402a and the process of extracting the I-th bit of the data N of S405a can be omitted as compared with the prior art. it can. As a result, the processing of the system software and the hardware processing accompanying this software processing become easy and efficient. [0079] Next, an example of applying the data transfer method as described above to, for example, an SD memory card or MMC (MultiMediaCard (registered trademark)) card and! /, And a card system that targets two memory cards. Will be explained.

[0080] In the SD memory card standard or MMC card standard, CMD24 (= WRITE— BLOCK) is defined as a command to write to a block, and CM D25 (= WRITE— MULTIPLE— BLOCK) is defined as a command to write to multiple blocks. Yes. Therefore, a command reserved in the SD memory card standard or the MMC card standard is used as a write command to which the data transfer method of the present invention is applied.

That is, for example, CMD60 (= DIFFERENTIAL—WRITE—BLOCK) is defined as a write command to a block, and CMD61 (DIFFERENTIAL—WRITE—MULTIPLE—BLOCK) is defined as a write command to a plurality of blocks. . The write command protocol between the initiator and target using CMD60 and CMD61 is exactly the same as CMD24 and CMD25, respectively, and only the data contents are changed to those with bit inversion information. In other words, the command formats of CMD60 and CMD61 are as shown in Fig. 5 (a) and (b), respectively.

FIGS. 5A and 5B are diagrams illustrating an example of command specifications of a memory card defined when a memory card is used as a target in the data storage system according to the embodiment of the present invention. (A) shows the specification example of CMD60, and (b) shows the specification example of CMD61.

[0083] As shown in FIG. 5 (a), the CMD60 is an adtc (addressed (point-to-point) data transfer commands) type command. In this type, a command is issued to a specific memory card specified from the CMD line, and after this specific memory card returns a response, data is transferred to the memory card through the DAT line. With this data transfer, the memory card writes data for the block size specified by the SET-BLOCKLEN command from the address specified by the argument when issuing CMD60. The data transferred to the memory card is data having bit inversion information as described above.

On the other hand, as shown in FIG. 5 (b), CMD61 is an adtc type command and It has become. Data transfer from the host to the memory card causes the memory card to continuously write data from the address specified by the argument when issuing CMD61 until it is stopped by the STOP-TRANSMISION command. Multiple blocks are written. The data transferred to the memory card is data having the bit inversion information as described above.

[0085] In this way, a new command is defined for a memory card such as an SD memory card or an MMC card, and a command determination function or a bit inversion information as described above is provided in the memory card as a function for responding to the command. It is possible to improve the data transfer efficiency of the memory card by providing a function for processing this.

[0086] While the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!

Industrial applicability

[0087] The data storage system and the memory card of the present invention are applied to a data storage system including various memory cards such as an SD memory card and a memory stick, a USB flash memory, and so on, and a serial transfer storage device. It is particularly useful. Not only these, but also hard disks with ATA connection, memory-powered host devices such as SD audio, DVD drives connected with IEEE 1394, various storage devices, and storage media not limited to storage devices. It is widely applicable to data storage systems including various devices in which addresses and data are assigned one-to-one.

Claims

The scope of the claims

[1] An initiator that transmits first data with different signal levels when data inversion is required and when data retention is required,

Second data is stored in advance, the first data is received, and the stored second data is inverted or held based on the signal level of the first data, thereby storing the stored second data. A data storage system characterized by having a target for updating data.

[2] In the data storage system according to claim 1,

The data storage system, wherein the target is a storage device.

[3] A data storage system having an initiator for transmitting data and a target for receiving the transmitted data,

The initiator sets a bit that requires inversion and a bit that does not need to be inverted to a first signal level and a second signal, respectively, with respect to second data of a plurality of bits stored in the target. Forming first data of a plurality of bits corresponding to a level, transmitting the first data of the plurality of bits to the initiator,

The target receives the first data of the plurality of bits, detects a bit corresponding to the first signal level from the received first data of the plurality of bits, and detects second data of the plurality of bits. On the other hand, the data storage system is characterized by updating the storage of the second data of the plurality of bits by inverting the data of the bit corresponding to the detected bit.

[4] In the data storage system according to claim 3,

In the target, software processing is performed using a computer provided in the target,

The processing of the software is as follows:

A step of determining a signal level of each bit for the plurality of bits of first data;

Only when the signal level of the determined bit is the first signal level, the bit data corresponding to the determined bit is read from the second data of the plurality of bits. And a step of inverting the read data and writing back the data.

[5] In the data storage system according to claim 3 or 4,

The data storage system, wherein the target is a storage device including a file system.

[6] When an initiator receives a command including a write address and data assigned with different signal levels corresponding to the inversion or retention of data, the data stored in the write address Is updated or stored based on the signal level of the input data, thereby updating the data stored in the write address.

[7] The memory card according to claim 6,

The memory card is an SD memory card or an MMC card.

[8] The memory card according to claim 7,

The memory card, wherein the command is a write command to a block.

[9] The memory card according to claim 7,

The memory is characterized in that the command is a write command to a plurality of blocks.