WO2006034535A1 - Method of and apparatus for mapping identifiers - Google Patents

Method of and apparatus for mapping identifiers Download PDF

Info

Publication number
WO2006034535A1
WO2006034535A1 PCT/AU2005/001478 AU2005001478W WO2006034535A1 WO 2006034535 A1 WO2006034535 A1 WO 2006034535A1 AU 2005001478 W AU2005001478 W AU 2005001478W WO 2006034535 A1 WO2006034535 A1 WO 2006034535A1
Authority
WO
WIPO (PCT)
Prior art keywords
identifier
mapping
bits
mapped
address
Prior art date
Application number
PCT/AU2005/001478
Other languages
French (fr)
Inventor
Benjamin Aaron Gittins
Original Assignee
Synaptic Laboratories Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2004905638A external-priority patent/AU2004905638A0/en
Application filed by Synaptic Laboratories Limited filed Critical Synaptic Laboratories Limited
Publication of WO2006034535A1 publication Critical patent/WO2006034535A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Definitions

  • the present invention relates to a method of and apparatus for mapping a set of identifiers which identify resources. It is particularly applicable to pseudo-randomly mapping hardware addresses, such as memory addresses.
  • identifiers are generally referred to as 'tags', and throughout this specification (including the claims) we use the terms 'tag' and 'identifier' as being synonymous.
  • each of 128 Megabyte of memory contains a number of memory locations which is not representable by base 2 raised to an integral exponent.
  • a memory pool of 128 Megabytes requires an address which is twenty-seven bits long address in order to reference the entire memory pool in 8 bit operations.
  • a memory pool of 256 Megabytes requires an address length of twenty- eight bits, and a memory pool of 512 Megabytes requires an address length of twenty -nine bits.
  • the co-pending application ensures that an n-bit address, after it has been mapped as a different n bit address, has nevertheless been mapped to identify hardware which does exist.
  • Figures 1 to 4 illustrate the background to the operation of the present invention.
  • the memory rank 2 carries 128 Megabytes of RAM which is addressable by the twenty-seven address bits which are represented by items 3 and 4 in figure 1.
  • the three lowest address bits 3 are illustrated as being displaced from the higher twenty-four address bits, this is done for the purposes of illustration only and it is to be understood that the twenty-seven address bits are contiguous.
  • the lower bits 3 and the higher bits 4 are illustrated as separated in the figures.
  • Single Data Rate-SDRAM DIMM modules have a 64 bit data input / output bus addressable in units of 8 bits. SDRAM read and write memory access operations are performed over a number of clock-cycles (called a BURST-LENGTH). In this example, assuming a BURST-LENGTH of 1, the lower three bits refer to the 8 locations addressable within this 64 bit read or write access.
  • Figure 2 illustrates the situation where a computer memory includes two memory ranks 11 and 12, each of which ranks are one hundred and twenty-eight megabytes in size.
  • reference numerals 3 and 4 illustrate a total of twenty-seven address bits, capable of addressing a maximum 128 Megabytes in 8 bit operations.
  • the twenty-seven bits of items 3 and 4 combined are not capable alone of addressing the full available memory.
  • the item 8 in figure 2 shows the addition of a further four address bits at the higher end of the address, making a total of thirty-one address bits. As is illustrated in figure 2, these additional four address bits can assume any one of the sixteen states ranging from (binary) 0000 to 1111.
  • the state 0000 for the four higher address bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the first memory rank 11 and the state 0001 for these bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the second memory rank 12.
  • the state 0000 for the four higher address bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the first memory rank 11 and the state 0001 for these bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the second memory rank 12.
  • Figures 3 and 4 similarly illustrate that with a thirty-one bit address referencing three or four 128 Megabyte memory ranks, there are only three or four valid states respectively for the upper four address bits.
  • the partial table of values of the uppermost four bits of the address shown at 9 in figure 3 indicates that only the values 0000, 0001 and 0010 will result in addressing valid memory addresses.
  • the partial table of values of the uppermost four bits of the address shown at 0 in figure 4 indicates that only the values 0000, 0001, 0010 and 0011 will result in addressing valid memory addresses.
  • a possible methodology of avoiding the problem of having an n-bit address map to a different n-bit address which identifies a non-existent memory location is to fully populate ⁇ the potential n-bit address space with memory.
  • fully populating a 27-bit address space requires only 128 Megabytes of RAM
  • fully populating a 28-bit address space requires 256 Megabytes
  • fully populating a 29-bit address space requires 512 Megabytes of RAM
  • fully populating a 30-bit address space requires 1 Gigabyte of RAM
  • fully populating a 31 -bit address space requires 2 Gigabytes of RAM.
  • the memory required to populate the available address space accordingly doubles for each additional bit of address width. Accordingly to cater for applications which required marginally more than 1 Gigabyte of resources would actually require a machine which had 2 Gigabytes of resources.
  • the present invention accordingly provides a method of mapping an identifier being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, into a mapped identifier being ⁇ k + ⁇ ) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers are less than m2", where m is an integer greater than 2 and less than 2 k , which method comprises the steps of: selecting two parts from the identifier, those parts comprising: a first part being the k most significant bits of the identifier; and a second part, contiguous with the first part, being n bits wide, mapping the first part into a mapped identifier which is in the range of '0' to m; mapping the second part into a mapped identifier which is in the range of '0' (zero) to (2" -1); and concatenating the first mapped part and the second mapped part.
  • the present invention provides apparatus for mapping an identifier being (k + n) bits wide, where k is equal to at least 2 and ⁇ is a positive integer, into a mapped identifier being (k + n) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers is less than ml n , where m is an integer greater than 2 and less than 2 k , which apparatus comprises: a first mapper for mapping the k most significant bits of the identifier, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m; and a second mapper for mapping n bits of the identifier, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the range of "O' (zero) to (2"
  • the present invention provides a memory controller for generating a mapped memory address being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, from an unmapped memory address being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, each of which address and mapped address comprise binary bits and both of which identifiers is less than m2", where m is an integer greater than 2 and less than 2 k , which memory controller comprises: a first mapper for mapping the k most significant bits of the address, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m; and a second mapper for mapping n bits of the address, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the
  • FIG. 6 represents a thirty-one bit memory address 70 which has a lower three bits represented as item 71, a higher twenty-four bits represented as item 72 and with its four highest address bits represented as item 75.
  • a thirty-one bit memory address (referenced as items 71, 72 and 75 in figure 6) is received as input to the process at 52.
  • n bits (where n is a non-zero integer) running from and including the fourth lowest bit are selected. (In this embodiment the lowest 8 addresses that reside within a 64 bit DIMM read/write access are not being mapped.) These n selected bits are referenced as item 72 in figure 6 while the lowermost three address bits are referenced as item 71 in that figure. In the presently-described embodiment, the n bits are 24 in number.
  • step 54 of figure 5 the n selected bits (referenced by numeral 72 in figure 6) are mapped bijectively (that is, in a one-to-one relationship) onto n bits (which are represented at 74 in figure 6).
  • mapping function satisfies strict 'avalanche criteria' such that any single bit change in the input to module 73 results in change in 50% of the bits in the output.
  • mapping function also ensures that sequential memory accesses result in each bit position of the output demonstrating a pseudo random uniform distribution.
  • Mapping functions which satisfy these strict avalanche criteria are described in cryptographic literature such as the descriptions of block-ciphers including DES and AES. Descriptions of block ciphers are to be found in chapters 12 to 15 of the book Applied Cryptography: Protocols, Algorithms, and Source Code in C by Bruce Schneier, second edition, 1996.
  • step 55 of figure 5 the four highest address bits (represented at 75 in figure 6) of the thirty-three bit address are selected.
  • the four highest bits (represented at 76 in figure 6) of the mapped address (represented at 74 in figure 6) are selected.
  • the second-highest 4 bits (represented at 78 in figure 6) of the mapped address (represented at 74 in figure 6) are selected.
  • step 58 of figure 5 the maximum valid memory address (represented as an input 79 in figure 6) for the available memory is received.
  • mapping process which is represented as step 59 in figure 5 and which is implemented by the mapping hardware which is shown schematically at 81 in figure 6.
  • This mapping process is described in detail in our co-pending Australian provisional patent application Method of and Apparatus for Mapping N-bit Identifiers of Fewer than 2" Resources, application number 2004905506.
  • the four selected bits 76 and the four selected bits 78 are used as keys to the mapping process 59; the four uppermost address bits 75 are mapped to a pseudo-random value indicated at 83 by the mapping process 59; and the nature of the mapping process 59 is such that it ensures that the pseudo-random value 83 is not higher the maximum valid value (indicated at 79) for the uppermost four address bits.
  • mapping function 73 satisfies the cryptographic strict avalanche criteria, each of the four-bit keys which are selected from the output bits 74 of that function 73 also satisfy the strict avalanche criteria. The result is that even if the input 75 to the mixing function 81 stays fixed from one clock cycle to another clock cycle, then the output 83 of that mixing function will have the same probability of changing as does a random distribution.
  • the four mapped address bits 83 are concatenated together with the twenty-six mapped bits 74 to produce the highest thirty bits of the mapped address.
  • the lowest bits of the memory address are passed untouched to the memory controller to select byte offset within a DIMM read/write access.
  • step 61 in figure 5 the assembled address is output from the mapping process which is illustrated in that figure.

Abstract

A method of pseudo-randomly mapping a resource identifier such as a memory address (70) considers the address (70) as including at least two components (75) and (72). The component (75) consists of k bits but represents a value which is lower than 2k. The second component (72) is an even number 2n of bits contiguous with the component (75) but less significant. The 2n bits are pseudo-randomly mapped into another 2n bit value (74). The most significant k bits of the mapped component (74) and the next lesser significant k bits of the mapped component (74) are used as keys to a mapping process (81). The mapping process (81) pseudo-randomly maps the k bit component (75) to a k bit value which is less than 2k.

Description

METHOD OF AND APPARATUS FOR MAPPING IDENTIFIERS
Field of the invention
The present invention relates to a method of and apparatus for mapping a set of identifiers which identify resources. It is particularly applicable to pseudo-randomly mapping hardware addresses, such as memory addresses. In the field of memory controllers, such identifiers are generally referred to as 'tags', and throughout this specification (including the claims) we use the terms 'tag' and 'identifier' as being synonymous.
This application: is related to our Australian provisional patent application entitled Method of and
Apparatus for Mapping N-Mt Identifiers of Fewer than 2" Resources, application number 2004905506, filed 24 September 2004; and claims priority from our Australian provisional patent entitled Method of and Apparatus for Mapping Identifiers, application number 2004905638, filed
30 September 2004; the contents of each of which is incorporated herein by reference.
Background of the invention In the field of computer hardware, there are situations in which it is of benefit to map logical addresses randomly into a physical address space, such as in the fields of load- sharing, quality of service applications and indexed address mixing. Although the present invention is described by reference to embodiments concerning mapping of memory addresses, the invention is generally applicable in any environment in which hardware can be referenced by numerical identifiers or tags.
In this specification we will consistently refer to indexed memory locations of 8 bits in length. In this way 128 Megabytes of memory (a total of 232 bits of memory) are addressable as an array of 227 eight-bit locations.
Our above referenced Australian provisional patent application Method of and Apparatus for Mapping n-bit Identifiers of Fewer than 2" Resources, application number 2004905506, discloses methods of and apparatus for mapping a sub-set of numerical identifiers of fewer than 2" physical resources, although the numerical identifiers are n bits long. That patent application accordingly caters for a situation where, for example, physical hardware does not include all of the physical 2" address locations which could be addressed by an address which is n bits long. Considering the number of 8 bit memory locations in 128 Megabytes of physical memory, this is a number which is represented by base 2 raised to an integral exponent. However a combined memory pool of three ranks each of 128 Megabyte of memory contains a number of memory locations which is not representable by base 2 raised to an integral exponent. A memory pool of 128 Megabytes requires an address which is twenty-seven bits long address in order to reference the entire memory pool in 8 bit operations. A memory pool of 256 Megabytes requires an address length of twenty- eight bits, and a memory pool of 512 Megabytes requires an address length of twenty -nine bits. The co-pending application ensures that an n-bit address, after it has been mapped as a different n bit address, has nevertheless been mapped to identify hardware which does exist. In order to be able to reference all memory locations within a pool of three 128 Megabyte modules (a total of 384 Megabytes) an address width of twenty-nine bits is thus required, although a twenty-nine bit address is capable of addressing a total memory space of 512 Megabytes. Our co-pending application accordingly ensures that when a twenty- nine bit long address has been mapped into a different twenty-nine bit long address, the mapped address references a memory location which is within the pool of 384 Megabytes, and not a memory address within a non-existent fourth module of 128 Megabytes which could be addressed by a twenty-nine bit long address.
Figures 1 to 4 illustrate the background to the operation of the present invention. As is illustrated in figure 1, the memory rank 2 carries 128 Megabytes of RAM which is addressable by the twenty-seven address bits which are represented by items 3 and 4 in figure 1. Although the three lowest address bits 3 are illustrated as being displaced from the higher twenty-four address bits, this is done for the purposes of illustration only and it is to be understood that the twenty-seven address bits are contiguous. The lower bits 3 and the higher bits 4 are illustrated as separated in the figures.
Single Data Rate-SDRAM DIMM modules have a 64 bit data input / output bus addressable in units of 8 bits. SDRAM read and write memory access operations are performed over a number of clock-cycles (called a BURST-LENGTH). In this example, assuming a BURST-LENGTH of 1, the lower three bits refer to the 8 locations addressable within this 64 bit read or write access. Another example; a DDR-SDRAM- DIMM module with 4 Burst rate has a read/write access of 512 bits. (64 bit bus * 2 DDR * 4 burst = 512 bit window). In practice we do not perform mapping operations over locations that fall within a single DIMM read / write access operation.
Figure 2 illustrates the situation where a computer memory includes two memory ranks 11 and 12, each of which ranks are one hundred and twenty-eight megabytes in size. Again in figure 2 reference numerals 3 and 4 illustrate a total of twenty-seven address bits, capable of addressing a maximum 128 Megabytes in 8 bit operations. However because the total memory available in the example of figure 2 is 256 Megabytes, the twenty-seven bits of items 3 and 4 combined are not capable alone of addressing the full available memory. For the purposes of illustration, the item 8 in figure 2 shows the addition of a further four address bits at the higher end of the address, making a total of thirty-one address bits. As is illustrated in figure 2, these additional four address bits can assume any one of the sixteen states ranging from (binary) 0000 to 1111. As is also illustrated in figure 2, the state 0000 for the four higher address bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the first memory rank 11 and the state 0001 for these bits are indicated as specifying that the twenty-seven lower address bits reference memory space within the second memory rank 12. In this example of 2 ranks of 128 Megabytes of RAM, if any of the four high address bits 3 were ever in a state other than 0000 or 0001, then they would be attempting to specify an invalid memory address in the sense that they did not correspond to any memory that was currently physically installed within the computer.
Figures 3 and 4 similarly illustrate that with a thirty-one bit address referencing three or four 128 Megabyte memory ranks, there are only three or four valid states respectively for the upper four address bits. The partial table of values of the uppermost four bits of the address shown at 9 in figure 3 indicates that only the values 0000, 0001 and 0010 will result in addressing valid memory addresses. The partial table of values of the uppermost four bits of the address shown at 0 in figure 4 indicates that only the values 0000, 0001, 0010 and 0011 will result in addressing valid memory addresses. - A - A possible methodology of avoiding the problem of having an n-bit address map to a different n-bit address which identifies a non-existent memory location is to fully populate ■ the potential n-bit address space with memory. Although fully populating a 27-bit address space requires only 128 Megabytes of RAM, fully populating a 28-bit address space requires 256 Megabytes, fully populating a 29-bit address space requires 512 Megabytes of RAM, fully populating a 30-bit address space requires 1 Gigabyte of RAM and fully populating a 31 -bit address space requires 2 Gigabytes of RAM. The memory required to populate the available address space accordingly doubles for each additional bit of address width. Accordingly to cater for applications which required marginally more than 1 Gigabyte of resources would actually require a machine which had 2 Gigabytes of resources.
Summary of the invention In one aspect, the present invention accordingly provides a method of mapping an identifier being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, into a mapped identifier being {k + ή) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers are less than m2", where m is an integer greater than 2 and less than 2k, which method comprises the steps of: selecting two parts from the identifier, those parts comprising: a first part being the k most significant bits of the identifier; and a second part, contiguous with the first part, being n bits wide, mapping the first part into a mapped identifier which is in the range of '0' to m; mapping the second part into a mapped identifier which is in the range of '0' (zero) to (2" -1); and concatenating the first mapped part and the second mapped part.
In another aspect, the present invention provides apparatus for mapping an identifier being (k + n) bits wide, where k is equal to at least 2 and π is a positive integer, into a mapped identifier being (k + n) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers is less than ml n, where m is an integer greater than 2 and less than 2k, which apparatus comprises: a first mapper for mapping the k most significant bits of the identifier, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m; and a second mapper for mapping n bits of the identifier, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the range of "O' (zero) to (2" -1).
In yet another aspect, the present invention provides a memory controller for generating a mapped memory address being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, from an unmapped memory address being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, each of which address and mapped address comprise binary bits and both of which identifiers is less than m2", where m is an integer greater than 2 and less than 2k, which memory controller comprises: a first mapper for mapping the k most significant bits of the address, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m; and a second mapper for mapping n bits of the address, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the range of "O' (zero) to (2" -1).
It will accordingly be seen that the present specification teaches how to efficiently distribute resource requests across multiple resources for the purposes of uniform load sharing.
Brief description of the drawings In order that the invention may be more readily understood, preferred embodiments of it are described with reference to the accompanying drawings in which: figures 1, 2 3 and 4 illustrate prior art; figure 5 illustrates the operation of a process according to embodiments of the present invention; and figure 6 illustrates the operation of hardware according to embodiments of the present invention. Description of preferred embodiments of the invention
A memory mapping process according to a preferred embodiment of the present invention is illustrated in the flow-chart of figure 5 and in the partial block-schematic drawing of figure 6. Figure 6 represents a thirty-one bit memory address 70 which has a lower three bits represented as item 71, a higher twenty-four bits represented as item 72 and with its four highest address bits represented as item 75.
In the first step of that memory mapping process, a thirty-one bit memory address (referenced as items 71, 72 and 75 in figure 6) is received as input to the process at 52.
In the step referenced as 53, n bits (where n is a non-zero integer) running from and including the fourth lowest bit are selected. (In this embodiment the lowest 8 addresses that reside within a 64 bit DIMM read/write access are not being mapped.) These n selected bits are referenced as item 72 in figure 6 while the lowermost three address bits are referenced as item 71 in that figure. In the presently-described embodiment, the n bits are 24 in number.
In step 54 of figure 5, the n selected bits (referenced by numeral 72 in figure 6) are mapped bijectively (that is, in a one-to-one relationship) onto n bits (which are represented at 74 in figure 6).
In the presently preferred embodiment the mapping function satisfies strict 'avalanche criteria' such that any single bit change in the input to module 73 results in change in 50% of the bits in the output. In this embodiment the mapping function also ensures that sequential memory accesses result in each bit position of the output demonstrating a pseudo random uniform distribution. Mapping functions which satisfy these strict avalanche criteria are described in cryptographic literature such as the descriptions of block-ciphers including DES and AES. Descriptions of block ciphers are to be found in chapters 12 to 15 of the book Applied Cryptography: Protocols, Algorithms, and Source Code in C by Bruce Schneier, second edition, 1996.
In step 55 of figure 5, the four highest address bits (represented at 75 in figure 6) of the thirty-three bit address are selected. In the step 56 of figure 5, the four highest bits (represented at 76 in figure 6) of the mapped address (represented at 74 in figure 6) are selected. In step 57 of figure 5, the second-highest 4 bits (represented at 78 in figure 6) of the mapped address (represented at 74 in figure 6) are selected.
At step 58 of figure 5, the maximum valid memory address (represented as an input 79 in figure 6) for the available memory is received.
The selected values for the four highest bits 76 of the mapped address, and for the four second highest bits 78 the maximum valid memory address 79, are inputs to the mapping process which is represented as step 59 in figure 5 and which is implemented by the mapping hardware which is shown schematically at 81 in figure 6. This mapping process is described in detail in our co-pending Australian provisional patent application Method of and Apparatus for Mapping N-bit Identifiers of Fewer than 2" Resources, application number 2004905506. According to that patent application: the four selected bits 76 and the four selected bits 78 are used as keys to the mapping process 59; the four uppermost address bits 75 are mapped to a pseudo-random value indicated at 83 by the mapping process 59; and the nature of the mapping process 59 is such that it ensures that the pseudo-random value 83 is not higher the maximum valid value (indicated at 79) for the uppermost four address bits.
Because the mapping function 73 satisfies the cryptographic strict avalanche criteria, each of the four-bit keys which are selected from the output bits 74 of that function 73 also satisfy the strict avalanche criteria. The result is that even if the input 75 to the mixing function 81 stays fixed from one clock cycle to another clock cycle, then the output 83 of that mixing function will have the same probability of changing as does a random distribution.
The closer to random the output of the mapping function 73, the more balanced is the distribution of possible output values. In process step 60 of figure 5, the four mapped address bits 83 are concatenated together with the twenty-six mapped bits 74 to produce the highest thirty bits of the mapped address. The lowest bits of the memory address are passed untouched to the memory controller to select byte offset within a DIMM read/write access.
At step 61 in figure 5, the assembled address is output from the mapping process which is illustrated in that figure.
'Comprises/comprising' when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

Claims

Claims:
1. A method of mapping an identifier being (k + n) bits wide, where k is equal to at least 2 and n is a positive integer, into a mapped identifier being {k + ή) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers are less than m2n, where m is an integer greater than 2 and less than 2k, which method comprises the steps of: selecting two parts from the identifier, those parts comprising: a first part being the k most significant bits of the identifier,; and a second part, contiguous with the first part, being n bits wide, mapping the first part into a mapped identifier which is in the range of '0' to rø; mapping the second part into a mapped identifier which is in the range of '0' (zero) to (2" -1); and concatenating the first mapped part and the second mapped part.
2. A method of mapping an identifier as claimed in claim 1, in which the step of mapping the first part into a mapped identifier comprises keyed mapping.
3. A method of mapping an identifier as claimed in claim 1 or claim 2, in which the step of mapping the second part into a mapped identifier comprises a keyed mapping
4. A method of mapping an identifier as claimed in claim 2 or claim 3 as appended to claim 2, in which the key used in mapping the first part comprises bits chosen from the n mapped bits.
5. A method of mapping an identifier as claimed in claim 2 or claim 4 as appended to claim 2, in which the key used in mapping the first part is at least 2k bits wide.
6. A method of mapping an identifier as claimed in any one of claims 2, or claims 4 or 5 as appended to claim 2, in which the key used in mapping the first part comprises bits which are chosen from at least two sources.
7. A method of mapping an identifier as claimed in any one of claims 2, or claims 4 to 6 as appended to claim 2, in which the key used in mapping the first part comprises the k most significant bits of the mapped second part.
8. A method of mapping an identifier as claimed in any one of claims 2, or claims 4 to 7 as appended to claim 2, in which the key used in mapping the first part comprises the k bits which are contiguous with the k most significant bits of the mapped second part.
9. A method of mapping an identifier as claimed in any one of claims 1 to 8, in which the identifier is a sub-set of an identifier which has a number of bits which is in excess of (k + n).
10. A method of mapping an identifier as claimed in any one of claims 1 to 9, in which the identifier is an identifier of computer hardware resources.
11. A method of mapping identifiers as claimed in any one of claims 1 to 10, in which the identifier is a memory address.
12. A method of mapping identifiers as claimed in any one of claims 1 to 10, in which the identifier is an identifier of a processing element to which has been assigned a task of performing a process upon an object.
13. A method of mapping identifiers as claimed in claim 12, in which the identifier further identifies the object upon which the task is to be performed.
14. Apparatus for mapping an identifier being (k + ή) bits wide, where k is equal to at least 2 and n is a positive integer, into a mapped identifier being (k + n) bits wide, each of which identifier and mapped identifier comprise binary bits and both of which identifiers are less than m2n where m is an integer greater than 2 and less than 2k, which apparatus comprises: a first mapper for mapping the k most significant bits of the identifier, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m; and a second mapper for mapping n bits of the identifier, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the range of "O' (zero) to (2" -1).
15. Apparatus for mapping an identifier as claimed in claim 14, further comprising a concatenater which concatenates the mapped k most significant bits and the mapped n bits.
16. Apparatus for mapping an identifier as claimed in claim 14 or claim 15 in which the first mapper performs keyed mapping.
17. Apparatus for mapping an identifier as claimed in any one of claims 14 to 16 in which the second mapper performs keyed mapping.
18. Apparatus as claimed in claim 16, or in claim 17 as appended to claim 16, in which the key used in mapping the first part comprises bits chosen from the n mapped bits.
19. Apparatus as claimed in any one of claims 16 and claims 17 or 18 as appended to claim 16, in which the key used in mapping the first part is at least 2k bits wide.
20. Apparatus as claimed in any one of claims 16 and claims 17 to 19 as appended to claim 16, in which the key used in mapping the first part comprises bits which are chosen from at least two sources.
21. Apparatus as claimed in any one of claims 16 and claims 17 to 20 as appended to claim 16, in which the key used in mapping the first part comprises the k most significant bits of the mapped second part.
22. Apparatus as claimed in any one of claims 16 and claims 17 to 20 as appended to claim 16, in which the key used in mapping the first part comprises the k bits which are contiguous with the k most significant bits of the mapped second part.
23. Apparatus as claimed in any one of claims 14 to 22, in which the identifier is a subset of an identifier which has a number of bits which is in excess of (k + ή).
24. Apparatus as claimed in any one of claims 14 to 23, in which the identifier is an identifier of computer hardware resources.
25. Apparatus as claimed in any one of claims 14 to 24, in which the identifier is a memory address.
26. Apparatus as claimed in any one of claims 14 to 25, in which the identifier is a processing element which has been assigned a task of performing a process upon an object.
27. Apparatus as claimed in claim 26, in which the identifier further identifies the object upon which the task is to be performed.
28. A memory controller for generating a mapped memory address being (k + ή) bits wide, where k is equal to at least 2 and n is a positive integer, from an unmapped memory address being (Jc + n) bits wide, where k is equal to at least 2 and n is a positive integer, each of which address and mapped address comprise binary bits and both of which identifiers is less than nil" where m is an integer greater than 2 and less than 2k, which memory controller comprises: a first mapper for mapping the k most significant bits of the address, those bits representing a value which is in the range of '0' (zero) to m into a mapped identifier which is in the range of '0' (zero) to m\ and a second mapper for mapping n bits of the address, which n bits are contiguous with the k most significant bits of the identifier and where n is a positive integer, into a mapped identifier which is in the range of "O' (zero) to (2" -1).
29. A memory controller as claimed in claim 28, further comprising a concatenater for concatenating the k most significant bits and the n bits.
30. A memory controller as claimed in claim 28 or claim 29, in which the first mapper performs keyed mapping.
31. A memory controller as claimed in any one of claims 28 to 30, in which the second mapper performs keyed mapping.
32. A memory controller as claimed in claim 30 or claim 31 , in which the key used in mapping the first part comprises bits chosen from the n mapped bits.
33. A memory controller as claimed in claim 30, claim 31 or claim 32 as appended to claim 30, in which the key used in mapping the first part is at least 2k bits wide.
34. A memory controller as claimed in any one of claims 30 or 31 to 33 as appended to claim 30, in which the key used in mapping the first part comprises bits which are chosen from at least two sources.
35. A memory controller as claimed in any one of claims 30 or 31 to 34 as appended to claim 301, in which the key used in mapping the first part comprises the k most significant bits of the mapped second part.
36. A memory controller as claimed in any one of claims 30 or 31 to 35 as appended to claim 30, in which the key used in mapping the first part comprises the k bits which are contiguous with the k most significant bits of the mapped second part.
37. A method of mapping an identifier as claimed in any one of claims 1 to 13, substantially as described with reference to the drawings.
38. Apparatus for mapping an identifier as claimed in any one of claims 14 to 27, substantially as described with reference to the drawings.
39. A memory controller as claimed in any one of claims 28 to 36, substantially as described with reference to the drawings.
40. A mapped identifier which has been mapped from an identifier according to the method of any one of claims 1 to 13 or 37.
41. A mapped identifier which has been mapped from an identifier by the apparatus which is claimed in any one of claims 14 to 27 or 38.
42. A mapped memory address which has been generated by a memory controller as claimed in any one of claims 28 to 36 or 39.
PCT/AU2005/001478 2004-09-30 2005-09-27 Method of and apparatus for mapping identifiers WO2006034535A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2004905638 2004-09-30
AU2004905638A AU2004905638A0 (en) 2004-09-30 Method of and Apparatus for Mapping Identifiers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU2007100165A Division AU2007100165A5 (en) 2004-09-30 2007-03-01 Method of And Apparatus for Mapping Identifiers

Publications (1)

Publication Number Publication Date
WO2006034535A1 true WO2006034535A1 (en) 2006-04-06

Family

ID=36118499

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AU2005/001478 WO2006034535A1 (en) 2004-09-30 2005-09-27 Method of and apparatus for mapping identifiers

Country Status (1)

Country Link
WO (1) WO2006034535A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0291742A (en) * 1988-09-29 1990-03-30 Toshiba Corp Virtual address cache control system
US5276826A (en) * 1988-01-04 1994-01-04 Hewlett-Packard Company Apparatus for transforming addresses to provide pseudo-random access to memory modules
US5897662A (en) * 1995-08-18 1999-04-27 International Business Machines Corporation Pseudo-random address generation mechanism that reduces address translation time
WO2001069392A2 (en) * 2000-03-16 2001-09-20 Boden Scott T Method and apparatus for secure and fault tolerant data storage
US6643740B1 (en) * 2001-07-30 2003-11-04 Lsi Logic Corporation Random replacement generator for a cache circuit
US20040006680A1 (en) * 2002-06-28 2004-01-08 Kevin Duncan Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276826A (en) * 1988-01-04 1994-01-04 Hewlett-Packard Company Apparatus for transforming addresses to provide pseudo-random access to memory modules
JPH0291742A (en) * 1988-09-29 1990-03-30 Toshiba Corp Virtual address cache control system
US5897662A (en) * 1995-08-18 1999-04-27 International Business Machines Corporation Pseudo-random address generation mechanism that reduces address translation time
WO2001069392A2 (en) * 2000-03-16 2001-09-20 Boden Scott T Method and apparatus for secure and fault tolerant data storage
US6643740B1 (en) * 2001-07-30 2003-11-04 Lsi Logic Corporation Random replacement generator for a cache circuit
US20040006680A1 (en) * 2002-06-28 2004-01-08 Kevin Duncan Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN 30 March 1990 (1990-03-30) *

Similar Documents

Publication Publication Date Title
US6381668B1 (en) Address mapping for system memory
US20110060876A1 (en) Exact Match Lookup Scheme
US7577819B2 (en) Vector indexed memory unit and method
CN115512754A (en) Apparatus and method for performing wear leveling operations
US11861051B2 (en) Buffer access for side-channel attack resistance
US20060047886A1 (en) Memory controller
CN107506310B (en) Address searching and keyword storing method and equipment
US6665768B1 (en) Table look-up operation for SIMD processors with interleaved memory systems
KR20030053457A (en) Memory system for increased bandwidth
US6622232B2 (en) Apparatus and method for performing non-aligned memory accesses
US7634634B2 (en) Data search apparatus and a method thereof
WO2007009262A1 (en) Dma simultaneous transfer to multiple memories
WO2006034535A1 (en) Method of and apparatus for mapping identifiers
US6016537A (en) Method and apparatus for address multiplexing to support variable DRAM sizes
CN111966607A (en) Double-rate memory access method and system
AU2007100165A5 (en) Method of And Apparatus for Mapping Identifiers
US6687786B1 (en) Automated free entry management for content-addressable memory using virtual page pre-fetch
CA2371029C (en) Data storage and retrieval
EP2082484A2 (en) Dual mode aes implementation to support single and multiple aes operations
US20050135135A1 (en) Content addressable memory for CIDR address searches
CN110308889B (en) Modulation processing apparatus and method
US20200272576A1 (en) Accelerating Access to Memory Banks in a Data Storage System
US7099321B2 (en) Symmetric dual-slot data hash method and network switching apparatus using same
JP3938124B2 (en) Data retrieval device
TWI402673B (en) Memory control device and information processing apparatus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DPEN Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase