WO2006012771A1

WO2006012771A1 - A multi-channel hdlc controller

Info

Publication number: WO2006012771A1
Application number: PCT/CN2004/000889
Authority: WO
Inventors: Jiajin Chen; Zong Zhao; Gangyue He; Xu Chen; Jian He; Jian Wang
Original assignee: Zte Corporation
Priority date: 2004-08-02
Filing date: 2004-08-02
Publication date: 2006-02-09
Also published as: CN100446578C; CN1994002A

Abstract

The mufti-channel HDLC controller of the present invention is used for realizing butt joint between the mufti-channel HDLC and the system, organizing data in manner of mufti-channel HDLC, then transmitting the data through the TDM interface, and connecting with the memory of the system which using the HDLG controller through the AHB bus interface at the same time. In the present invention, a part of temporary parameters that the HDLC controller needs are placed outside of the HDLC controller, and calling the parameters from the outside through inner logic. The present invention adopts non-RSIC design, all circuit realization, and needn't to adopt general RSIC, and it sets special interface for the HDLC, the difficulty of the setting is small; the present invention stores the temporary parameters that the HDLC controller needs for operation into the memory, which saves the hardware resource of the mufti-channel HDLC controller itself. Moreover, for the transmitting and receiving of the mufti-channel data of the mufti-channel HDLC controller, all channels of one mufti-channel HDLC controller share a set of controlling logic, which also saves many hardware resources.

Description

Multi-channel advanced data link controller

The present invention relates to the field of T1/E1 communications, and in particular to a multi-channel advanced data link (HDLC) controller.

Background technique

In the prior art, the controllers using the multi-channel HDLC mainly have the following two types.

One is a multi-channel HDLC controller of the type Conexant CN8472/8474, which uses a non-RISC (reduced instruction set computer structure), full circuit implementation, a total of 128 channels, the 128 channel HDLC is processed by the serial port interface, bit (bit) Level processing, interrupt processing controller, DMA controller, PCI (peripheral component expansion interface) bus interface.

However, the multi-channel HDLC controller has the following two problems: First, a large amount of hardware resources are required for storing temporary parameters, and a lot of temporary parameters are required in the working process of the controller, including: receiving temporary loop redundancy for each channel Remainder code CRC (32 bits), receive temporary buffer pointer for each channel (32 bits), available length of receive temporary buffer for each channel (14 bits), transmit temporary cyclic redundancy for each channel Code CRC (32 bits), send temporary buffer pointer (32 bits) per channel, transmit temporary buffer available length (14 bits) per channel; then for 128 such channels, internal hardware needs There are (32+32+14+32+32+14) times 128 (channels) of RAM to store these temporary parameters. The above are the temporary parameters necessary for the HDLC controller to work. If you want to improve the performance of the HDLC controller, each channel needs to store more temporary parameters, which will consume a lot of hardware resources. Secondly, the HDLC controller uses ping-pong FIFO to implement data transfer. The receive FIFO and transmit FIFO are shown in Figure 1 and Figure 2. The FIFO is divided into two equal-space RAM structures. The data is first written to one of the RAMs. When the write is full, it is switched to another RAM structure to operate. The interrupt is given to the DMA controller, and the DMA controller will fetch its data. After such a ping-pong FIFO-side is occupied by the write data port, the read data port can only access the other half of the FIFO, or wait for the port to be released before being accessed, thereby causing waste of resources.

The second is the MPC8260 communication processor produced by Motorola, USA. As shown in Figure 3, there are two 128-channel HDLC communication interfaces inside. The disadvantage of this solution is that its multi-channel HDLC cannot operate independently. There is a RISC for implementing the same configuration and control of multi-channel HDLC, data organization and data scheduling, and controlling other peripherals to achieve the same functionality as the Conexant CN8472/8474 multi-channel HDLC controller. Therefore, the communication processor requires a RISC module on the hardware, and the module has a corresponding interface to the multi-channel HDLC and other peripherals to facilitate control of the RISC module; it is also necessary to write code for the RISC module. This design is complex and requires a long design cycle.

Summary of the invention

The technical problem to be solved by the present invention is to provide a multi-channel advanced data link controller, which solves the disadvantages of large hardware resources consumption, insufficient use of FIFO resources, and difficulty in implementation in the prior art, and uses external resources to implement internal operations. .

The multi-channel advanced data link controller of the present invention comprises a time division multiplexed data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending monitor, and a sending Channel processor, time division multiplexed data transmission processing module, and AHB bus interface;

The time division multiplexed data receiving processing module is configured to receive data from a serial interface, and convert the data into 8-bit parallel data, and output the data to the receiving channel processor;

The receiving channel processor is configured to remove, by the channel number, the zero inserted in the received data, and output the result to the receiving monitor; The receiving monitor is configured to store data into the receiving buffer by channel number, monitor the capacity of the receiving buffer, and send a data request to the receiving and receiving;

The receiving buffer is configured to temporarily store the received data;

The receiving engine is configured to perform cyclic redundancy check processing on the data, perform read and write operations on the buffer descriptor, and perform data transfer according to the requirements of the buffer descriptor, and then write the corresponding interrupt into the memory. Medium

The sending engine is configured to perform read and write operations on the buffer descriptor, perform data transfer according to the requirements of the buffer descriptor, perform cyclic redundancy check processing, and write the corresponding interrupt into the memory;

The sending buffer is configured to temporarily store and send data;

The sending monitor is configured to read data from the sending buffer and transmit the data to the sending channel processor according to an application of the sending channel processor, and according to the capacity of the sending buffer, Transmitting engine application data;

The sending channel processor is configured to perform a zero insertion operation on the data transmitted by the sending monitor by using a channel as a number;

The time division multiplexed data transmission processing module is configured to read a channel number from a slot number, and read channel data according to the channel number, and convert 8-bit parallel data into serial data output;

The AHB bus interface is coupled to the receiving engine and the transmitting engine for converting internal bus behavior to AHB bus behavior.

The invention adopts a non-RISC design and a full circuit implementation, does not need to adopt a universal RISC, and sets a special interface for the HDLC, and has a low design difficulty; the present invention stores the temporary parameters required for the operation of the multi-channel HDLC controller in the memory, thereby saving The hardware resources of the multi-channel HDLC controller itself, the hardware resources saved are (( 32+32+14 ) (number of bits in the transmission part) + ( 32+32+14 ) (number of bits in the receiving part)) *128 (pass At the same time, the system only needs to allocate a memory space when using the multi-channel HDLC controller. If the system does not use the multi-channel HDLC controller, or does not need to use the multi-channel HDLC controller for a period of time, then this Memory resources can be freed for other uses. In addition, for multi-channel data transmission or reception in a multi-channel HDLC controller, not every channel uses a set of control logic, but all channels of a multi-channel HDLC controller share a set of control logic, because at any At the point in time, only one channel is in operation, so each channel does not need to do a set of control logic, which also saves a lot of hardware resources. In the present invention, the receiving buffer and the transmitting buffer adopt a FIFO structure, and the read and write operations can be simultaneously operated. In addition, the space size of the FIFO is dynamically allocated, and the number of timeslots is allocated, and the FIFO space is allocated more and occupied. A channel with a small number of time slots allocates less FIFO space.

DRAWINGS

1 is a schematic diagram of a receiving FIFO of a Conexant CN8472/8474 multi-channel HDLC controller in the prior art;

2 is a schematic diagram of a transmit FIFO of a Conexant CN8472/8474 multi-channel HDLC controller in the prior art;

3 is a schematic diagram of a multi-channel HDLC structure of a Motorola MPC 8260 in the prior art; and FIG. 4 is a schematic structural view of a multi-channel HDLC controller of the present invention.

detailed description

The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

The solutions of the multi-channel HDLC controller in the prior art are shown in FIG. 1 to FIG. 3, which are described in the background art, and are not described herein again.

The multi-channel HDLC controller of the present invention organizes data in a multi-channel HDLC manner and then passes The time division multiplexing (TDM) interface transmits data and is connected to the system memory using the HDLC controller through the AHB (AMBA) bus interface. In the present invention, the temporary parameters required for the operation of some HDLC controllers are placed in the HDLC controller. In addition, these parameters are called externally by internal logic.

As shown in FIG. 4, the multi-channel HDLC controller of the present invention includes: a time division multiplexing data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending monitor, The transmit channel processor, the time division multiplexed data transmission processing module, and the AHB bus interface. The various components of a multi-channel HDLC controller are described below in terms of both received data and transmitted data.

Receive data:

After the time-division multiplexed data receiving and processing module receives data from the TDM serial interface, since the subsequent data processing is in units of bytes, it is necessary to convert the data from the serial data into 8-bit parallel data and output it to the receiving channel processor. . In addition, TDM is numbered in time slots, and subsequent processing is numbered by channel number, so the processing of 4 bar TDM is also required to be separated from the subsequent process of channel numbering.

After receiving the parallel data transmitted by the processing module, the receiving channel processor processes the channel number as the number. Although these parallel data are in units of bytes, the zero insertion operation has actually been performed, so the receiving channel processor needs to remove the zeros inserted in the data, so that the subsequent functional modules can actually operate in the smallest unit of bytes. . The data after the divide-by-zero operation is transferred to the receive monitor.

The receiving monitor stores the received data in the receiving buffer by channel, and monitors the capacity of the receiving buffer. When it reaches the threshold, it generates a corresponding data transmission request to the receiving engine, and the threshold is generally 4 Bytes or 16 bytes or one frame ends. To increase bus utilization, data is typically sent out when it accumulates to one word (4 bytes).

The receiving buffer temporarily stores the data transmitted from the receiving monitor, and accumulates 4 bytes for the receiving engine. The above data. The capacity of this buffer is dynamically assignable and can be adjusted according to the actual situation. In practice, the buffer can be implemented in FIFO.

In order to save the hardware resources of the HDLC controller, some information required for the operation of the HDLC controller can be stored in the memory, such as temporarily receiving the cyclic redundancy check code CRC (32 bits), the receive buffer temporary pointer (32 bits), Receive buffer temporary usable length (14 bits) and some control status information of the channel.

After receiving the data request from the receiving monitor, the receiving engine operates in two phases: If the receiving engine finds that the received data is the beginning of a frame, or there is no valid buffer descriptor (buffer descr i Ptor (abbreviated as BD), the receiving engine reads the BD from the specified channel BD table of the memory through the AHB bus interface, obtains the parameters on the BD, starts to carry the data according to the address given by the BD, and confirms whether the length of the BD is sufficient. The data to be transmitted next: If the BD is not enough or just meets the operation, or the BD length exceeds the data transfer amount, but the data is found to have a frame end information in the data transfer, after the data transfer is completed, the status is Write back, close BD at the same time; If the BD length exceeds the value of this data transmission, and there is no information in the data transmission that there is a frame end in the data transmission, after the data transmission is completed, the current CRC value is stored in the designated channel. (Temporary) As a temporary CRC (32-bit) in the parameter table, save the current address to the specified channel (temporary) As a temporary pointer (32 bits) of the receive buffer, the length of the data that can be transferred at that time is stored in the specified channel (temporary) parameter table as the temporary usable length of the receive buffer (14 bits), and other Parameters. Then exit this channel operation.

If the received data is not the beginning of a frame, and the BD is not used up yet, the receiving engine reads the received temporary CRC (32 bits) from the specified channel (temporary) parameter table of the memory through the AHB bus interface. The engine will be used as the initial value of the CRC for the CRC operation), the receive buffer temporary pointer (32 bits) (the receiving engine uses this pointer as the starting point of the address for data transfer), and the receive buffer is temporarily available (14 bits). Control information such as (receiving engine for length control), and then start receiving buffer The data transmitted by the device is subjected to CRC processing, and data is carried at the same time, and it is confirmed whether the length of the BD is sufficient to carry the amount of data transmitted: if the length of the BD is insufficient or just satisfied, or the length of the BD exceeds the data transmission amount However, in the data transmission, if there is a message ending in the data, the status is written back to the BD after the data transfer is completed, and the BD is closed at the same time, if the BD length exceeds the magnitude of the data transmission, and the data is transmitted. If no information is found in the end of the data, after the data transfer is completed, the current CRC value is stored in the specified channel (temporary) parameter table as a temporary CRC (32-bit), and the current address is stored in the designated channel ( Temporary) parameter table as a temporary pointer of the receive buffer (32 bits), the length of the data that can be transferred at that time is stored in the specified channel (temporary) parameter table as the temporary usable length of the receive buffer (14 bits), There are other parameters. Then exit the operation of this channel.

The AHB bus interface acts as a connection between the multi-channel HDLC controller and the AHB bus to convert the HDLC internal bus behavior to the standard AHB bus behavior.

send data:

After receiving the application sent by the sending monitor, the sending engine will also have two phases of operation, which is similar to the receiving, except that the flow of data is opposite to the receiving. Similarly, in order to save the hardware resources of the HDLC controller, the HDLC controller works. Some of the required information is stored in the memory, such as the cyclic redundancy code CRC (32 bits), the send buffer temporary pointer (32 bits), the send buffer temporary available length (14 bits), and the channel. Some control status information, after the end of each BD operation, will return the corresponding frame information back to the BD.

Since the sending engine is a batch of incoming data, and the sending channel only needs to read one byte at a time, it is necessary to temporarily store the bulk data transmitted by the sending engine. The buffer is provided for the temporary storage space. Make the bus more efficient. The transmit buffer is implemented in FIFO, and its capacity is dynamically assignable, which can be adjusted according to actual conditions. The sending monitor reads data from the sending buffer according to the data request of the sending channel processor, and transmits the data to the sending channel processor; and applies data to the sending engine according to the free amount of the sending buffer at the time, and the application condition is the channel. It is enabled, and the transmit buffer has 4 bytes for this channel or more than 16 slots.

The transmit channel processor processes the data transmitted by the transmit monitor with the channel number. The data sent from the monitor is in bytes, but it is not the final data format. It needs to be inserted before the data is sent.

The time division multiplexed data transmission processing module obtains data from the transmission channel processor, and then converts the data into serial data for transmission. Since the previous data processing is in units of bytes, the data needs to be converted from 8-bit parallel data to serial. Data, similar to reception, TDM is numbered in time slots, and subsequent processing is numbered by channel number, so it is also necessary to separate the time division multiplexed data transmission processing module from other channel numbered modules.

For the purposes of the present invention, a multi-channel HDLC controller can support up to 32 channels, and four multi-channel HDLC controllers can support up to 128 channels.

The multi-channel HDLC controller of the invention can be used as a communication module of the S0C chip to realize the docking of the multi-channel HDLC and the system, and supports the BD mode, and can actively transfer the data to the user-specified memory space. The multi-channel HDLC controller must have a separate AHB s lave port, which can be considered as part of the AHB bus interface for the system to configure the HDLC controller. The multi-channel HDLC controller must also be an AHB Mas ter. It can be regarded as part of the AHB bus interface, and can actively perform data transfer according to the requirements of the BD, and identify the state of the frame data on the BD after the data transfer is completed.

The multi-channel HDLC controller uses the standard AHB bus interface. The AHB bus interface is the most common in the S0C chip, which makes the HDLC controller a standard module and easy to port to other S0Cs. In the chip.

The S0C chip is actually a multi-layer AHB bus system. At the same time, as long as different AHB Mas ters access different AHB Slave spaces, the operation of each AHB Mas ter will not be affected. At the same time, there are multiple memories in the S0C chip. Space, where SRAM space and SDRAM space can be used to store information about the operation of the HDLC controller.

SRAM space is relatively small, supporting BURST operation. Reading and writing data from the SRAM space can return a 32-bit data per clock, which provides a feasible material basis for storing some temporary parameters into the memory. Therefore, some temporary parameters required for each channel operation are stored in the SRAM space. Within, for example, each channel receives a temporary CRC (32 bits), sends a temporary CRC (32 bits), receives a buffer temporary pointer (32 bits), sends a buffer temporary pointer (32 bits), receives a buffer temporarily Available length (14 bits), send buffer temporarily available length (14 bits) and other information. The SDRAM space has a larger capacity than the SRAM space and is used to store the BD table for each channel and the buffer pointed to by the BD table.

For a multi-channel HDLC controller, you don't actually know which area is the high-speed memory space, and which area is the medium-speed and large-capacity space. Users can even put the base address, operation pointer, and operation required for each channel. Some temporary parameters, BD tables, and pointed buffers are all placed in the same memory space. However, from the perspective of the optimization process, it is better to store some temporary parameters required for operation in the high-speed memory space, and store the BD table and buffer of each channel in the medium-speed large-capacity space.

It should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention and are not intended to be limiting, and the present invention will be described in detail with reference to the preferred embodiments. The modifications and equivalents of the present invention are intended to be included within the scope of the appended claims.

Claims

Claim

A multi-channel advanced data link controller, comprising: a time division multiplexed data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, and a sending a monitor, a transmit channel processor, a time division multiplexed data transmission processing module, and an AHB bus interface;

The receiving channel processor is configured to remove, by the channel number, the zero inserted in the received data, and output the result to the receiving monitor;

The receiving monitor is configured to store data into the receiving buffer by a channel number, monitor a capacity of the receiving buffer, and send a data request to the receiving engine; the receiving buffer is configured to temporarily Store received data;

The receiving engine is configured to perform cyclic redundancy check processing on the data, perform read and write operations on the buffer descriptor, and perform data transfer according to the requirements of the buffer descriptor, and then write the corresponding interrupt into the memory. ;

The sending engine is configured to perform read and write operations on the buffer descriptor, perform data transfer according to the requirements of the buffer descriptor, perform cyclic redundancy check processing, and write the corresponding interrupt into the memory. The sending buffer is configured to temporarily store and send data;

The sending channel processor is configured to perform a zero insertion operation on the data transmitted by the sending monitor by using a channel number; The time division multiplexed data transmission processing module is configured to read a channel number from a slot number, and read channel data according to the channel number, and convert 8-bit parallel data into serial data output;

2. The multi-channel advanced data link controller of claim 1, wherein the receiving monitor transmits a data request to the receiving engine after monitoring a capacity of the receiving buffer to reach a threshold.

3. The multi-channel advanced data link controller of claim 2, wherein the threshold is 4 bytes or 16 bytes or a frame ends.

The multi-channel advanced data link controller according to claim 1, wherein the condition that the sending monitor applies for data to the sending engine is that the channel is enabled, and the sending buffer The corresponding channel has 4 bytes or more than 16 bytes of free space.

The multi-channel advanced data link controller according to claim 1, wherein the memory stores temporary parameters required for each channel operation, a buffer descriptor table for each channel, and a buffer table. The buffer pointed to by the flush descriptor table.

6. The multi-channel advanced data link controller according to claim 4, wherein the temporary parameters required for each channel operation are stored in a high-speed memory space, and the buffer descriptor of each channel is Tables and buffers are stored in medium-speed and large-capacity space.

7. The multi-channel advanced data link controller according to claim 1, wherein the receiving engine/transmitting engine needs to pass the AHB after receiving the data request sent by the receiving monitor/transmitting monitor. The bus interface reads temporary parameters and buffer descriptor tables from memory.

8. The multi-channel advanced data link controller of claim 1 wherein said receive buffer/transmission buffer is implemented in a first in first out buffer having a capacity that is dynamically assignable.