WO2006003579A1 - Field effect transistor method and device - Google Patents

Field effect transistor method and device Download PDF

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Publication number
WO2006003579A1
WO2006003579A1 PCT/IB2005/052096 IB2005052096W WO2006003579A1 WO 2006003579 A1 WO2006003579 A1 WO 2006003579A1 IB 2005052096 W IB2005052096 W IB 2005052096W WO 2006003579 A1 WO2006003579 A1 WO 2006003579A1
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WO
WIPO (PCT)
Prior art keywords
gate
work function
metal
layer
suicide
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PCT/IB2005/052096
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French (fr)
Inventor
Marcus J. H. Van Dal
Jacob C. Hooker
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Koninklijke Philips Electronics N.V.
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Publication of WO2006003579A1 publication Critical patent/WO2006003579A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2

Definitions

  • the invention relates to a method of manufacturing a field effect transistor and to a field effect transistor thus made.
  • CMOS complementary metal oxide semiconductor
  • polysilicon is a semiconductor and can deplete leading to a higher equivalent gate oxide thickness. Accordingly, it is desireable to replace polysilicon with metal to lower the equivalent oxide thickness.
  • FUSI fully suicided
  • US 6,562,718 relates to a method of forming a FUSI gate.
  • the top surface of the polysilicon gate electrode is exposed, a refractory metal layer deposited on the whole surface and annealing is carried out for sufficient time and at a high enough temperature for the metal to react with the gate and fully silicidize the gate.
  • US 6,562,718 relates in particular to the use of a shield layer to protect the active regions of the device.
  • the method of US 6,562,718 uses a multi-step process, the first step involving a metal layer deposited over the surface and followed by an annealing step silicidizing the source and drain and partially suiciding the gate.
  • a shield layer is applied, the gate exposed, and a further layer of the same metal is applied. Then, a further annealing step fully silicidizes the gate.
  • this process is not easy to introduce into existing process flows and it adds significant complexity to the existing processes. According to the invention there is provided a method of making a semiconductor device according to claim 1.
  • the diffused material of the work function layer at the suicide - semiconductor interface may be in the form of the metal of the work function layer or its suicide. Either way, it affects the work function of the metal/silicide interface. Accordingly, the method according to the invention allows the work function of the FUSI gate to be engineered. By choosing different work function metals and different amounts of such metals, the work function of the gate can be selected. It is essential for metal gate integration in CMOS processes that the gate has the proper work function to obtain a low threshold voltage and thereby obtain high on state currents for N- and P MOSFET's.
  • the work function is adjusted in a process that occurs after the formation of the gate.
  • the process only needs relatively low temperature annealing to diffuse the work function metal. This makes the method easy to integrate into existing process flows, since additional steps can be carried out at the end of the existing process.
  • the invention may be applied for example to a nickel suicide process using platinum as the work function metal.
  • the invention may also use other refractory metals to form the suicide, such as nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium, molybdenum or cobalt or alloys thereof.
  • the invention can also use other materials as the work function layer, especially metals such as platinum, tungsten, tantalum, ruthenium, molybdenum, nickel, cobalt or titanium.
  • the use of a work function metal different from the refractory metal originally used to form the suicide allows the variation of the work function.
  • the thickness of the work function metal deposited can also be selected and this can affect the amount of work function metal that diffuses to the interface.
  • the refractory metal is nickel and the work function is platinum.
  • the annealing may be carried out in two stages. Accordingly, the method may include a suiciding annealing step of annealing the semiconductor device to suicide the gate after the step of depositing a refractory metal layer over the gate, and a further annealing step to diffuse the work function layer to the boundary of the gate and the gate dielectric to change the work function after depositing a work function metal layer over the gate.
  • the first annealing step can be part of the conventional process. Only the deposition of the work function layer and the further annealing step need to be added to conventional processes. This makes the integration of the process according to the invention into conventional CMOS processes particularly straightforward.
  • the suiciding annealing step may be carried out for a time to fully suicide the gate.
  • the suiciding annealing step may be carried out for a time less than that required to fully suicide the gate leaving part of the gate adjacent to the gate dielectric as silicon.
  • the silicon adjacent to the gate dielectric may in this instance be fully suicided in the further annealing step. In this way, the work function metal layer can react with the silicon to form suicide adjacent to the gate dielectric forming a WF suicide.
  • a planarisation layer may be deposited before the step of depositing the work function metal layer.
  • the gate needs to be exposed; this can be done by not depositing the planarisation layer over the gate or by subsequently exposing the gate.
  • the planarisation layer may be for example of oxide.
  • a polishing or etching step is used to remove the work function layer, If used, the polishing step may be mechanical or chemical-mechanical polishing.
  • the work function layer is removed by a selective wet etch.
  • the invention also relates to a semiconductor device, comprising: a semiconductor body; a gate dielectric adjacent to the semiconductor body; a fully suicided gate adjacent to the gate dielectric for controlling conduction in the semiconductor body, the fully suicided gate being of metal suicide; and a work function metal or metal suicide at the interface between the suicided gate and the gate dielectric, the metal of the work function metal or metal suicide being a different metal to the metal of the fully suicided gate.
  • Figure 1 is a side view of a first step in a method according to a first embodiment of the invention
  • Figure 2 is a side view of a second step in a method according to the first embodiment of the invention
  • Figure 3 is a side view of a third step in a method according to the first embodiment of the invention
  • Figure 4 is a side view of a first step in a method according to a second embodiment of the invention
  • Figure 5 is a side view of a second step in a method according to the second embodiment of the invention
  • Figure 6 is a side view of a first step in a method according to a third embodiment of the invention
  • Figure 7 is a side view of a second step in a method according to the third embodiment of the invention.
  • Figure 8 is a side view of a step in a method according to a fourth embodiment of the invention.
  • Each of the methods according to embodiments of the invention starts with a semiconductor device processed to the stage at which a gate dielectric 4 has been formed over a semiconductor body 2.
  • a semiconductor body 2 needs to be provided with source contacts, drain contacts, and various diffusions depending on the intended application of the semiconductor device. Since the various methods of forming such contacts and diffusions are well known to those skilled in the art, these too will not be described, particularly since the present invention is concerned with the formation of the gate.
  • a polysilicon gate 6 is formed over the gate dielectric 4 over silicon body 2.
  • the gate 6 is then patterned using a mask in a manner well known to those skilled in the art.
  • the sides of the gate are protected.
  • this is done by forming insulating spacers 10 on the sides of the gate, for example by depositing insulator on the whole surface and using an anisotropic etch to etch the insulator away from the regions where the silicon is on the top of the substrate leaving the insulator only on the sides of the gate.
  • the insulator may be, for example, of oxide, nitride or a combination. Further steps may be carried out here to complete the semiconductor device if required, leaving the gate 6 exposed.
  • a refractory metal layer 8 is deposited on top of the gate as shown in figure 1.
  • the refractory metal layer is nickel.
  • the sample is annealed in a suiciding annealing step to react all of the polysilicon with the refractory metal of the metal layer.
  • a selective etch is then used to remove the refractory metal leaving the suicide gate 6.
  • a work function layer of platinum 12 is then deposited over the full surface to a thickness of 10nm, and in particular in contact with the exposed gate, as shown in Figure 2.
  • Low temperature annealing is then carried out, for example at a temperature of 370 0 C, for a period of 50 minutes. In alternative embodiments, the temperature may be in the range 250 to 65O 0 C for a time from 0.1 to 60 minutes, and the thickness of the work function layer from 1nm to 200nm, preferably 2nm to 50nm.
  • the platinum 12 diffuses to the boundary of the suicide gate 6 and gate dielectric 4 to form interface layer 14. In this location, it affects the work function between the gate 6 and body 2.
  • the remainder of the platinum 12 is removed from the surface, for example using a selective wet etch, to result in the stage shown in Figure 3.
  • the device is then finished, for example by being packaged, etc.
  • the first annealing step does not fully suicide the gate. This can be done by annealing for less time, but it is generally more convenient to simply deposit a thickness of refractory metal 8 that is sufficient to convert most, but not all, of the silicon gate 6 to suicide. The process leaves an unreacted region 7 of silicon in contact with the dielectric layer 4 (Fig. 4).
  • the work function layer can react with the remaining silicon in the unreacted region 7 to form a suicide layer of the material of the work function adjusting layer 12 at the interface between gate 6 and dielectric 4.
  • the work function layer is titanium and titanium suicide 16 will be formed, as illustrated in Figure 5. Note that apart from the use of a different material, the structure is essentially the same as that shown in Figure 3. A modification to use a damascene process may be applied to either of the first or second embodiments.
  • a third embodiment will now be described, which is a modified version of the first embodiment.
  • a planar insulating layer 18 made of silicon dioxide is applied before the deposition of the work function layer 12, resulting in the structure shown in Figure 6. Note that although the layer is described as a planar layer exact flatness is not required and some differences in the thickness over the surface are acceptable.
  • the further annealing step is carried out to diffuse the work function layer material to the gate 6 / dielectric 4 interface.
  • a mechanical polishing step is used to remove the work function layer 12 from above the planar insulating layer 16 leaving the structure shown in Figure 7.
  • the process of the third embodiment is particularly suitable for process flows for the manufacture of semiconductors that use damascene processing in any event.
  • the damascene process is applied to a method in which the gate is only partially suicided in the suiciding annealing step.
  • the structure after depositing the planar insulating layer 18 and work function layer is as shown in Figure 8, with unreacted region 7 in contact with dielectric layer.
  • Subsequent processing continues as in the second and third embodiments, by carrying out an annealing step to diffuse the material of the work function layer to the interface where it can react with the silicon in the unreacted region 7 to form a suicide, and then to remove the remainder of the work function layer 12 by a mechanical polishing process.
  • the invention is not limited to the embodiments described above and any suitable form of silicon may be used as silicon gate 6.
  • the refractory metal layer may be of any material that forms suicide, including nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium or cobalt or alloys thereof.
  • the work function layer may be of any material that can diffuse through the suicide and change the work function of the gate. Platinum works particularly well, but other options include platinum, tungsten, tantalum, ruthenium, molybdenum, nickel, cobalt or titanium or alloys thereof.
  • the semiconductor body need not be silicon, but may be any other semiconductor, for example GaAs, GaN, InSb etc.
  • any suitable deposition process form the various layers may be used, including for example plasma vapour deposition or chemical vapour deposition.

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Abstract

A fully or partially silicided gate (6) is provided on gate dielectric (4) over semiconductor body (2). Then, a work function adjustment layer (12) is deposited, and annealed. The work function adjustment layer may be, for example, of platinum. In the annealing step, the metal of the work function adjustment layer diffuses through the silicide to the interface between the gate (6) and the dielectric (4), converting any silicon at the interface to silicide resulting in a fully silicided gate. The work function of the gate (6) may accordingly be adjusted using a process that can be added to conventional processes after the gate is fully formed.

Description

DESCRIPTION
FIELD EFFECT TRANSISTOR METHOD AND DEVICE
The invention relates to a method of manufacturing a field effect transistor and to a field effect transistor thus made.
Conventional complementary metal oxide semiconductor (CMOS) transistors use a conductive polysilicon gate. However, polysilicon is a semiconductor and can deplete leading to a higher equivalent gate oxide thickness. Accordingly, it is desireable to replace polysilicon with metal to lower the equivalent oxide thickness.
A prior proposal to achieve this goal is known as a fully suicided (FUSI) gate. In the FUSI gate process, the polysilicon is fully suicided, i.e. is turned into metal suicide throughout its thickness. This process is compatible with existing CMOS processes since such processes generally incorporate silicidation, which may be used in such conventional processes for producing a low resistance ohmic contact to the source, gate and drain.
US 6,562,718 relates to a method of forming a FUSI gate. The top surface of the polysilicon gate electrode is exposed, a refractory metal layer deposited on the whole surface and annealing is carried out for sufficient time and at a high enough temperature for the metal to react with the gate and fully silicidize the gate. US 6,562,718 relates in particular to the use of a shield layer to protect the active regions of the device. The method of US 6,562,718 uses a multi-step process, the first step involving a metal layer deposited over the surface and followed by an annealing step silicidizing the source and drain and partially suiciding the gate. Then, a shield layer is applied, the gate exposed, and a further layer of the same metal is applied. Then, a further annealing step fully silicidizes the gate. However, this process is not easy to introduce into existing process flows and it adds significant complexity to the existing processes. According to the invention there is provided a method of making a semiconductor device according to claim 1.
The diffused material of the work function layer at the suicide - semiconductor interface may be in the form of the metal of the work function layer or its suicide. Either way, it affects the work function of the metal/silicide interface. Accordingly, the method according to the invention allows the work function of the FUSI gate to be engineered. By choosing different work function metals and different amounts of such metals, the work function of the gate can be selected. It is essential for metal gate integration in CMOS processes that the gate has the proper work function to obtain a low threshold voltage and thereby obtain high on state currents for N- and P MOSFET's.
In contrast, US 6,582,718 simply creates a metal suicide through the full thickness of the gate and accordingly suggests no way of adjusting the work function value of the gate. A study of the diffusion of platinum metal through suicide was carried out some time ago by Finstadt et al, Thin Solid Films, volume 51 (1978) page 391 , and the methods taught in that document may be used in the context of the present invention. That document gave results of experiments in which platinum was deposited on top of nickel on top of silicon. The platinum did not diffuse through the nickel. After annealing for long enough to fully convert the nickel layer into nickel suicide by reaction with silicon, the platinum deposited on top of the nickel diffused to the boundary between nickel and silicon. Further processing resulted in platinum in the middle of a nickel suicide layer. Finstadt et al do not describe a gate, nor any dielectric, simply two different metal layers deposited on silicon.
The end point of the Finstadt et al process is wholly unsuitable in the present application having as it does a platinum layer in the middle of the nickel suicide layer. Nevertheless, the inventors have realised that diffusion through suicide in general can be used to adjust the work function of a FUSI gate.
It is a particular benefit of the invention that the work function is adjusted in a process that occurs after the formation of the gate. The process only needs relatively low temperature annealing to diffuse the work function metal. This makes the method easy to integrate into existing process flows, since additional steps can be carried out at the end of the existing process.
The invention may be applied for example to a nickel suicide process using platinum as the work function metal.
The invention may also use other refractory metals to form the suicide, such as nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium, molybdenum or cobalt or alloys thereof. The invention can also use other materials as the work function layer, especially metals such as platinum, tungsten, tantalum, ruthenium, molybdenum, nickel, cobalt or titanium. The use of a work function metal different from the refractory metal originally used to form the suicide allows the variation of the work function. The thickness of the work function metal deposited can also be selected and this can affect the amount of work function metal that diffuses to the interface. In a specific embodiment, the refractory metal is nickel and the work function is platinum.
The annealing may be carried out in two stages. Accordingly, the method may include a suiciding annealing step of annealing the semiconductor device to suicide the gate after the step of depositing a refractory metal layer over the gate, and a further annealing step to diffuse the work function layer to the boundary of the gate and the gate dielectric to change the work function after depositing a work function metal layer over the gate.
The first annealing step can be part of the conventional process. Only the deposition of the work function layer and the further annealing step need to be added to conventional processes. This makes the integration of the process according to the invention into conventional CMOS processes particularly straightforward.
The suiciding annealing step may be carried out for a time to fully suicide the gate. Alternatively, the suiciding annealing step may be carried out for a time less than that required to fully suicide the gate leaving part of the gate adjacent to the gate dielectric as silicon. The silicon adjacent to the gate dielectric may in this instance be fully suicided in the further annealing step. In this way, the work function metal layer can react with the silicon to form suicide adjacent to the gate dielectric forming a WF suicide.
In a development of the invention, a planarisation layer may be deposited before the step of depositing the work function metal layer. The gate needs to be exposed; this can be done by not depositing the planarisation layer over the gate or by subsequently exposing the gate. The planarisation layer may be for example of oxide. After carrying out the further annealing step, a polishing or etching step is used to remove the work function layer, If used, the polishing step may be mechanical or chemical-mechanical polishing.
In a particularly convenient arrangement, the work function layer is removed by a selective wet etch.
The invention also relates to a semiconductor device, comprising: a semiconductor body; a gate dielectric adjacent to the semiconductor body; a fully suicided gate adjacent to the gate dielectric for controlling conduction in the semiconductor body, the fully suicided gate being of metal suicide; and a work function metal or metal suicide at the interface between the suicided gate and the gate dielectric, the metal of the work function metal or metal suicide being a different metal to the metal of the fully suicided gate.
For a better understanding of the invention, embodiments will now be described with reference to the accompanying drawings, in which:
Figure 1 is a side view of a first step in a method according to a first embodiment of the invention;
Figure 2 is a side view of a second step in a method according to the first embodiment of the invention; Figure 3 is a side view of a third step in a method according to the first embodiment of the invention; Figure 4 is a side view of a first step in a method according to a second embodiment of the invention;
Figure 5 is a side view of a second step in a method according to the second embodiment of the invention; Figure 6 is a side view of a first step in a method according to a third embodiment of the invention;
Figure 7 is a side view of a second step in a method according to the third embodiment of the invention;
Figure 8 is a side view of a step in a method according to a fourth embodiment of the invention.
Like components are given like reference numerals in different figures and embodiments and for brevity will not always be mentioned in the description relating to each Figure. The figures are schematic and not to scale.
Each of the methods according to embodiments of the invention starts with a semiconductor device processed to the stage at which a gate dielectric 4 has been formed over a semiconductor body 2. A wide variety of suitable processes for arriving at this structure will be known to those skilled in the art, and so these processes will not be described further. Further, the skilled person will appreciate that the semiconductor body 2 needs to be provided with source contacts, drain contacts, and various diffusions depending on the intended application of the semiconductor device. Since the various methods of forming such contacts and diffusions are well known to those skilled in the art, these too will not be described, particularly since the present invention is concerned with the formation of the gate.
In a first embodiment of a method according to the invention, a polysilicon gate 6 is formed over the gate dielectric 4 over silicon body 2.
The gate 6 is then patterned using a mask in a manner well known to those skilled in the art.
Next, the sides of the gate are protected. In the embodiment, this is done by forming insulating spacers 10 on the sides of the gate, for example by depositing insulator on the whole surface and using an anisotropic etch to etch the insulator away from the regions where the silicon is on the top of the substrate leaving the insulator only on the sides of the gate. The insulator may be, for example, of oxide, nitride or a combination. Further steps may be carried out here to complete the semiconductor device if required, leaving the gate 6 exposed.
Next, a refractory metal layer 8 is deposited on top of the gate as shown in figure 1. In the example, the refractory metal layer is nickel. The sample is annealed in a suiciding annealing step to react all of the polysilicon with the refractory metal of the metal layer. A selective etch is then used to remove the refractory metal leaving the suicide gate 6.
A work function layer of platinum 12 is then deposited over the full surface to a thickness of 10nm, and in particular in contact with the exposed gate, as shown in Figure 2. Low temperature annealing is then carried out, for example at a temperature of 370 0C, for a period of 50 minutes. In alternative embodiments, the temperature may be in the range 250 to 65O0C for a time from 0.1 to 60 minutes, and the thickness of the work function layer from 1nm to 200nm, preferably 2nm to 50nm. The platinum 12 diffuses to the boundary of the suicide gate 6 and gate dielectric 4 to form interface layer 14. In this location, it affects the work function between the gate 6 and body 2.
The remainder of the platinum 12 is removed from the surface, for example using a selective wet etch, to result in the stage shown in Figure 3. The device is then finished, for example by being packaged, etc.
It is a particular benefit of the method according to the invention that the introduction of the work-function altering layer can take place very late in the process flow and that it requires only low temperature annealing. This makes it easy to integrate into existing CMOS processes.
In an alternative procedure, in a second embodiment the first annealing step does not fully suicide the gate. This can be done by annealing for less time, but it is generally more convenient to simply deposit a thickness of refractory metal 8 that is sufficient to convert most, but not all, of the silicon gate 6 to suicide. The process leaves an unreacted region 7 of silicon in contact with the dielectric layer 4 (Fig. 4).
The processing then continues exactly as before, except that the work function layer can react with the remaining silicon in the unreacted region 7 to form a suicide layer of the material of the work function adjusting layer 12 at the interface between gate 6 and dielectric 4. In the second embodiment, the work function layer is titanium and titanium suicide 16 will be formed, as illustrated in Figure 5. Note that apart from the use of a different material, the structure is essentially the same as that shown in Figure 3. A modification to use a damascene process may be applied to either of the first or second embodiments. A third embodiment will now be described, which is a modified version of the first embodiment.
In the modification, a planar insulating layer 18 made of silicon dioxide is applied before the deposition of the work function layer 12, resulting in the structure shown in Figure 6. Note that although the layer is described as a planar layer exact flatness is not required and some differences in the thickness over the surface are acceptable.
Next, the further annealing step is carried out to diffuse the work function layer material to the gate 6 / dielectric 4 interface. Then, a mechanical polishing step is used to remove the work function layer 12 from above the planar insulating layer 16 leaving the structure shown in Figure 7.
The process of the third embodiment is particularly suitable for process flows for the manufacture of semiconductors that use damascene processing in any event. In a fourth embodiment, the damascene process is applied to a method in which the gate is only partially suicided in the suiciding annealing step. In this case, the structure after depositing the planar insulating layer 18 and work function layer is as shown in Figure 8, with unreacted region 7 in contact with dielectric layer. Subsequent processing continues as in the second and third embodiments, by carrying out an annealing step to diffuse the material of the work function layer to the interface where it can react with the silicon in the unreacted region 7 to form a suicide, and then to remove the remainder of the work function layer 12 by a mechanical polishing process.
The invention is not limited to the embodiments described above and any suitable form of silicon may be used as silicon gate 6. The refractory metal layer may be of any material that forms suicide, including nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium or cobalt or alloys thereof.
The work function layer may be of any material that can diffuse through the suicide and change the work function of the gate. Platinum works particularly well, but other options include platinum, tungsten, tantalum, ruthenium, molybdenum, nickel, cobalt or titanium or alloys thereof.
The semiconductor body need not be silicon, but may be any other semiconductor, for example GaAs, GaN, InSb etc.
Any suitable deposition process form the various layers may be used, including for example plasma vapour deposition or chemical vapour deposition.
From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductors and which may be used in addition to or instead of features described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.

Claims

1. A method of manufacturing a semiconductor device, including: providing a gate dielectric (4) over a semiconductor body (2); forming a silicon gate (6) over the gate dielectric; depositing a refractory metal layer (8) over the gate (6); depositing a work function layer (12) over the gate (6); annealing to fully react the silicon gate (6) with the refractory metal layer (8) to form a fully suicided gate and to diffuse the material of the work function layer to the boundary of the gate (6) and the gate dielectric (4) to change the work function of the silicon gate (6) with respect to the semiconductor body (2).
2. A method according to claim 1 wherein the method includes: a suiciding annealing step annealing the semiconductor device to suicide the gate (6) by reaction with the refractory metal layer (8) after the step of depositing a refractory metal layer (8) over the gate (6), and a further annealing step to diffuse the material of the work function layer to the boundary of the gate (6) and the gate dielectric (4) to change the work function after depositing the work function metal layer (12).
3. A method according to claim 2 wherein the suiciding annealing step fully converts the gate (6) to suicide.
4. A method according to claim 2 wherein the suiciding annealing step does not fully convert the gate (6) to suicide leaving an unconverted part
(7) of the gate adjacent to the gate dielectric (4) as silicon.
5. A method according to any of claims 2 to 4 further comprising: depositing a planarisation layer (18) before the step of depositing the work function layer (12) leaving the gate exposed; and removing the work function layer (12) by carrying out a polishing step after the further annealing step.
6. A method according to any preceding claim wherein the work function layer (12) is platinum.
7. A method according to any preceding claim wherein the refractory metal layer (8) is of nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium or cobalt or alloys thereof.
8. A semiconductor device, comprising: a semiconductor body (2); a gate dielectric (4) adjacent to the semiconductor body (2); a fully suicided gate (6) adjacent to the gate dielectric (4) for controlling conduction in the semiconductor body (2), the fully suicided gate being of metal suicide; and a work function metal or metal suicide (14,16) at the interface between the suicided gate (6) and the gate dielectric (4), the metal of the work function metal or metal suicide being a different metal to the metal of the fully suicided gate (6).
9. A semiconductor device according to claim 8 wherein the work function metal or metal suicide (14,16) at the interface between the suicided gate and the gate dielectric is platinum suicide.
10. A semiconductor device according to claim 8 or 9, wherein the fully suicided gate (6) is a metal suicide of nickel, hafnium, erbium, platinum, tungsten, titanium, palladium, chromium or cobalt, or alloys thereof.
PCT/IB2005/052096 2004-06-28 2005-06-24 Field effect transistor method and device WO2006003579A1 (en)

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CN103811326A (en) * 2012-11-06 2014-05-21 格罗方德半导体公司 Metal gate structure for midgap semiconductor device and method of making same
CN109371378A (en) * 2018-12-20 2019-02-22 五邑大学 A method of improving transparent conductive oxide film work function

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CN103811326A (en) * 2012-11-06 2014-05-21 格罗方德半导体公司 Metal gate structure for midgap semiconductor device and method of making same
CN109371378A (en) * 2018-12-20 2019-02-22 五邑大学 A method of improving transparent conductive oxide film work function

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