WO2005101501A1 - Housing formed by a metallic layer - Google Patents

Housing formed by a metallic layer Download PDF

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Publication number
WO2005101501A1
WO2005101501A1 PCT/EP2005/051584 EP2005051584W WO2005101501A1 WO 2005101501 A1 WO2005101501 A1 WO 2005101501A1 EP 2005051584 W EP2005051584 W EP 2005051584W WO 2005101501 A1 WO2005101501 A1 WO 2005101501A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
insulating material
component
electrically insulating
Prior art date
Application number
PCT/EP2005/051584
Other languages
German (de)
French (fr)
Inventor
Mark-Matthias Bakran
Eric Baudelot
Ralf-Michael Franke
Norbert Seliger
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2005101501A1 publication Critical patent/WO2005101501A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01032—Germanium [Ge]
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    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01068—Erbium [Er]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01075—Rhenium [Re]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/30107—Inductance
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    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0999—Circuit printed on or in housing, e.g. housing as PCB; Circuit printed on the case of a component; PCB affixed to housing

Definitions

  • modules with plastic housings have been used, which are filled with a silicone-containing gel as a potting compound.
  • the module explodes silicone is burned, polluting the environment.
  • these modules are not gas-tight, i.e. there is an influence of harmful gas and moisture damage.
  • the modules Because of the construction principle described, the dimensions cannot be reduced arbitrarily. This applies especially to the height.
  • the modules also always need a cover to protect bond wires during the manufacturing steps, otherwise there is a risk of short-circuiting by pressing the wires in.
  • a contacting technique for components, in particular power semiconductors, is known from WO 03/030247 A2, in which they are contacted via a laminated film and a conductive layer applied thereon.
  • the object of the invention is to bring about a reduction in volume in the power electronics by minimizing the housing dimensions for power modules. Weaknesses adhering to previous modules resulting from the use of silicone potting compound and lids as well as sensitivity to harmful gases and moisture should also be eliminated.
  • the substrate can have, for example, a metal structure that runs around the circuit structure on the surface of the substrate. It forms a kind
  • the circuit structure advantageously has an insulation layer to which the metal layer is applied. This prevents the metal layer from producing undesired electrical connections.
  • the insulation layer can be applied over a large area, that is, for example, also to the metal structure that surrounds the circuit structure on the substrate.
  • the insulation layer is then opened, for example with the aid of a laser, before the metal layer is applied to the metal structure.
  • the insulation layer is preferably applied using one or more of the following procedures: laminating a film, casting curtains, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, Printing, in particular screen printing, overmolding, dispensing, spin coating.
  • a physical or chemical deposition of metal is preferably carried out.
  • Such physical processes are sputtering and vapor deposition (Physical Vapor Deposition, PVD).
  • Chemical deposition can take place from the gaseous phase (Chemical Vapor Deposition, PVD) and / or liquid phase (Liquid Phase Chemical Vapor Deposition). It is also conceivable that a thin metal partial layer, for example made of titanium / copper, is first applied by one of these methods, on which a thicker metal partial layer, for example made of copper, is then electrodeposited.
  • a component with an electrical contact surface is arranged on the substrate.
  • a layer of electrically insulating material is applied to the substrate and the component.
  • the electrical contact surface of the component remains free when the layer of electrically insulating material is applied and / or is exposed after the layer of electrically insulating material has been applied, in particular by opening a window.
  • a layer of electrically conductive material is applied to the layer of electrically insulating material and the electrical contact surface of the component.
  • the layer of electrically insulating material is therefore a carrier layer for the layer of electrically conductive material.
  • circuit structure is thus produced using very similar process steps to the housing, which considerably rationalizes and simplifies the manufacturing process.
  • Another synergy effect is that both the leads of the component, which are in the circuit structure by the Layer of electrically conductive material are formed, as well as the metal layer belonging to the housing and the insulating layer and the insulation layer are constructed in layer technology, that is to say are very flat. Overall, extremely flat power modules or other circuits can be realized in this way.
  • the layer of electrically insulating material preferably follows the surface contour formed from the substrate and the component, i.e. the layer of electrically insulating material runs on this surface contour in accordance with the surface contour formed from the substrate and the component.
  • the layer of electrically insulating material in its entirety follows the surface contour formed from the substrate and the component, there are two advantages, in particular if a power component is used as the component.
  • a sufficient thickness of the layer of electrically insulating material over the edges of the component facing away from the substrate is ensured, so that breakdown at high voltages or field strengths is prevented.
  • the layer of electrically insulating material is not so thick that it would be problematic to expose and contact contact surfaces on the substrate's conductor tracks.
  • the metal layer and / or the insulation layer arranged below it advantageously follows the surface contour formed by the component and the substrate and the layers lying between the component and the substrate and the metal layer and / or the insulation layer.
  • This surface contour can deviate from the surface contour given by the substrate and the component in particular, because the intermediate layers, ie the layer made of electrically insulating material and the layer made of electrically conductive material, can be structured depending on the application. If the layer of electrically insulating material serves as a carrier layer for the layer of electrically conductive material, this in turn serves as a carrier layer for the insulation layer, which in turn serves as a carrier layer for the metal layer. Each layer is in close, dense contact with its neighboring layers and adheres to them.
  • the thickness of the layer of electrically insulating material and / or the thickness of the insulation layer deviates, in order to follow the surface contour, in its rectilinear region by less than 50% of its thickness over the component in its rectilinear region, in particular by less than 20%.
  • the thicknesses are preferably approximately the same, that is to say deviate from one another by less than 5% or even less than 1%.
  • the percentages relate in particular to the thickness of the layer above the component in its rectilinear area, which accordingly indicates 100%.
  • the rectilinear region is used because the layer in the inner edges of the substrate and the component generally runs thicker and edges of the component facing away from the substrate generally run thinner.
  • the substrate For contacting the component with the substrate, the substrate preferably has an electrical contact surface which remains free when the layer of electrically conductive material is applied or is exposed after the layer of electrically conductive material has been applied and to which the Layer of electrically conductive material is also applied.
  • the contact surface of the component is connected to the contact surface of the substrate via the layer of electrically conductive material.
  • the contact area of the component and the contact area of the substrate are preferably approximately the same size in order to ensure a continuous current flow.
  • the electrical contact surface of the component can be left exposed when the layer of electrically conductive material is applied and / or later exposed.
  • the complete or partial release already during application can be realized particularly advantageously if the layer of electrically insulating material is applied with openings.
  • a layer of electrically insulating material with one or more corresponding openings or windows can be used from the outset, which can be created beforehand, for example, by inexpensive punching out or cutting out. If a window is opened by exposing the contact area with more than 60% of the size of the side and / or area of the component on which the window is opened, in particular more than 80%, the method can be used for power components whose Contact surface has a corresponding size.
  • the size of the window should not be more than 99.9% of the size of the side and / or area of the component on which the window is opened, in particular not more than 99% and further preferably not more than 95%.
  • the window is opened in particular on the largest and / or on the side of the component facing away from the substrate and preferably has an absolute size of more than 50 qmm, in particular more than 70 qmm.
  • Any substrates on an organic or inorganic basis can be used as substrates.
  • Such substrates are, for example, PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
  • the layer of electrically insulating material and the insulation layer are in particular made of plastic. Depending on the further processing, these layers can be photosensitive or non-photosensitive.
  • a substrate with a surface which is equipped with one or more components, in particular power components, on each of which one or more contact surfaces are or are present, the layer of electrically insulating material on this surface under vacuum is applied so that the layer of electrically insulating material closely covers this surface including the components and optionally also the contact surfaces and adheres to this surface including the substrate and the components.
  • the layer of electrically insulating material is designed so that a height difference of up to 100.0 ⁇ m can be overcome.
  • the height difference is caused, among other things, by the topology of the substrate and by the components and interconnects arranged on the substrate.
  • the thickness of the layer of electrically insulating material can be 10 ⁇ m to 500 ⁇ m.
  • a layer of electrically insulating material with a thickness of 25 ⁇ m to 150 ⁇ m is preferably applied.
  • the application is repeated until a certain thickness of the layer of electrically insulating material is reached.
  • partial layers of electrically insulating material of smaller thickness are processed to form a layer of electrically insulating material of higher thickness.
  • These partial layers made of electrically insulating material advantageously consist of a type of plastic material.
  • the partial layers made of electrically insulating material consist of several different plastic materials. The result is a layer made of partial layers of electrically insulating material.
  • a window in the layer of electrically insulating material is opened by laser ablation to expose the electrical contact surface of the component.
  • a wavelength of a laser used for this is between 0.1 ⁇ m and 11 ⁇ m.
  • the power of the laser is between 1 watt and 100 watts.
  • a C02 laser with a wavelength of 9.24 ⁇ m is preferably used.
  • the windows are opened without damaging a chip contact made of aluminum, gold or copper, which may be under a layer of insulating material.
  • a photosensitive layer made of electrically insulating material is used and a window is opened by a photolithographic process to expose the electrical contact surface of the component.
  • the photolithographic process comprises exposing the photosensitive layer of electrically insulating material and developing and thus removing the exposed or unexposed areas of the layer of electrically insulating material.
  • the cleaning step may be carried out, for example, by wet chemistry. In particular, a plasma cleaning process is also conceivable.
  • a layer of electrically conductive material made of several partial layers of different, electrically conductive materials arranged one above the other is used.
  • different metal layers are applied one above the other.
  • the number of sub-layers or metal layers is, in particular, 2 to 5.
  • Such a partial layer consists, for example, of a titanium-tungsten alloy (TiW).
  • TiW titanium-tungsten alloy
  • a partial layer that promotes or improves adhesion is advantageously applied directly to the surface to be contacted.
  • Such a partial layer consists, for example, of titanium.
  • At least one conductor track is produced from the electrically conductive material after the two-dimensional contacting in / or on the layer.
  • the conductor track can be applied to the layer.
  • the layer is structured to produce the conductor track. This means that the conductor track in this layer is generated.
  • the conductor track is used, for example, to make electrical contact with a component.
  • the structuring is usually carried out in a photolithographic process.
  • a photoresist can be applied to the electrically conductive layer, dried and then exposed and developed.
  • a tempering step may follow in order to stabilize the applied photoresist against subsequent treatment processes.
  • photoresist Conventional positive and negative resists (coating materials) can be used as photoresist.
  • the photo lacquer is applied, for example, by a spraying or dipping process.
  • Electro-deposition electrostatic or electrophoretic deposition is also conceivable.
  • another structurable material can also be applied using one or more of the following procedures: curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, qing, dispensing, spin coating, laminating a film.
  • photosensitive foils can also be used, which are laminated on and exposed and developed in a manner comparable to the applied photoresist layer.
  • the following can be used to generate the conductor track.
  • the electrically conductive layer is structured, and in a subsequent sub-step, a further metallization is applied to the conductor track generated.
  • the conductor track is reinforced by the further metallization.
  • copper is electroplated on the conductor track created by structuring with a thickness of 1 ⁇ m to 400 ⁇ m.
  • the photoresist layer or the laminated film or the alternatively used structurable material is removed. solves. This can be done, for example, with an organic solvent, an alkaline developer or the like.
  • Subsequent differential etching removes the flat, metallically conductive layer that is not reinforced with the metallization.
  • the reinforced conductor track is retained.
  • the steps of laminating, exposing, contacting and producing conductor tracks are carried out several times to produce a multilayer device.
  • a layer of electrically insulating material is heat-resistant up to 300 ° C.
  • DCB substrates can be processed in the benefit.
  • the entire chip contact area can be used so that high currents can be derived.
  • the chips can be controlled homogeneously due to the flat contact.
  • the inductance of the contact in a contact area is smaller due to the areal geometry than with thick wire bonding.
  • the contacting leads to high reliability in the case of vibration and mechanical shock loads.
  • modules can be produced and used without bond wires, without potting compound and therefore without a plastic housing.
  • the housing can be made gastight in that the insulation layer, for example in the form of a film, covers all parts of the circuit structure and the insulation layer is subsequently metallized by applying a metal layer.
  • FIG. 1 shows a device with a housing formed with a metal layer
  • FIG. 2 shows the device of Figure 1 in the area of a load connection
  • FIG. 3 shows a cross section through the device according to FIG. 1.
  • a base plate 1, for example made of copper, can be seen in the figures.
  • a substrate 3 is arranged on this base plate 1 via a lower copper metallization 2.
  • This substrate 3 is, for example, a DCB substrate, which has a layer of ceramic material, the lower copper metallization 2 applied to the lower surface of the substrate 3 and one on a side facing away from the lower surface Surface of the substrate 3 has applied layer 4 of copper.
  • the layer 4 on the upper surface of the substrate 3 is removed in some areas down to the upper surface of the substrate 3. Conductor tracks are thus formed on the substrate 3 through the layer 4 of copper.
  • One or more components 9 in the form of semiconductor chips are applied to the surface of the remaining copper layer 4 facing away from the substrate 3, which can be identical and / or different from one another.
  • the component 9, which is preferably a power semiconductor chip, contacts the upper surface of the layer 4 made of copper with a contact surface, not shown, which is present on a lower surface of the component 9 facing the layer 4 of copper.
  • this contact surface is soldered to the layer 4 made of copper.
  • the contact area on the lower surface of the component 9 is the contact area of a collector or drain contact and the contact on the upper surface of the component 9 is an emitter-source contact, the contact area of which is the said contact area is.
  • the entire surface of the substrate 3 equipped with the component 9 is due to the exposed parts of the upper surface of the substrate layer 3, the upper and side surfaces of the layer 4 of copper outside the component 9 and the free surface of the component 9 given itself, which is determined by the upper surface and the lateral surfaces of this component 9.
  • a layer 7 of electrically insulating material is applied under vacuum to the entire surface of the substrate 3 equipped with the component 9, so that the layer 7 made of electrically insulating material closely fits the surface of the substrate 3 equipped with the component 9 with the contact surfaces covered and adheres to this surface.
  • the layer 7 made of electrically insulating material follows that through the exposed parts of the upper surface of the substrate layer 3, the upper surface of the layer 4 made of copper outside the component 9 and through the free surface of the component 9 itself, which through the upper surface and the lateral surface of this component 9 is determined, given surface contour.
  • the layer 7 made of electrically insulating material serves as an insulator and as a carrier of a layer 11 made of electrically conductive material applied to it.
  • Typical thicknesses of the layer 7 made of electrically insulating material are in the range from 25 to 150 ⁇ m, and larger thicknesses can also be achieved from layer sequences of thinner partial layers made of electrically insulating material. Isolation field strengths in the range of a few 10 kV / mm can thus advantageously be realized.
  • Each contact surface to be contacted on the surface of the substrate 3 including the component 9 is exposed by opening respective windows in the layer 7 made of electrically insulating material.
  • a contact surface to be contacted is not only a contact surface on the component 9, but also any region of the upper surface exposed by opening a window in the layer 7 made of electrically insulating material.
  • layer 4 is made of copper or another metal.
  • the size of the window that is open for contacting the contact area of the component is more than 60% of the size of the component, in particular more than 80%.
  • the windows in the layer 7 made of electrically insulating material are preferably opened by laser ablation.
  • the contact surfaces of the substrate and the component exposed by the layer 7 made of electrically insulating material are in surface contact with a layer 11 made of electrically conductive material, preferably metal.
  • the layer 11 made of electrically conductive material can be applied over the entire surface both to each contact surface and to the upper surface of the layer 7 made of electrically insulating material facing away from the surface of the substrate 3, and can then be structured, for example by photolithography, in such a way that each contact surface remains in contact with the surface and Laugh over the contact and the layer 7 made of electrically insulating material extending conductor tracks are given.
  • the result is a device with a substrate 3 with a component 9, electrical contact surfaces being arranged on the surface formed by the substrate 3 and the component 9, in which an insulator in the form of a layer 7 of electrically insulating material is applied to the surface , which lies close to the surface and adheres to the surface, and in which the layer 7 made of electrically insulating material has windows at the contact surfaces, in which these contact surfaces are free of the layer 7 made of electrically insulating material and with a layer 11 electrically conductive material are contacted.
  • a circuit structure is thus arranged on the substrate 3, which contains the component 9, the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material.
  • the circuit structure 7, 9, 10, 11 furthermore has an insulation layer 10 in the form of a film laminated onto the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material.
  • a metal structure 6 in the form of a closed ring made of copper is present at the edges and transitions to connections below the insulation layer 10.
  • the metal structure 6 may have been part of the layer 4 made of copper and may have been produced from this by etching away areas that are not required.
  • the insulation layer 10 is opened by lasering exactly above the metal structure 6. After opening, a further metallization process takes place, which covers the insulation layer 10 with a gas-tight metal layer 8, which also ensures a gas-tight seal to the metal structure 6.
  • the circuit structure with the component 9, the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material on the substrate 3 is hermetically sealed.
  • layer 7 made of electrically insulating material is opened in such a way that a sufficient insulation distance between the connection formed by layer 4 made of electrically conductive material and metal structure 6 is ensured.

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Abstract

A metallic layer is applied to a circuit structure on a substrate and, together with the substrate, forms a housing for the circuit structure.

Description

Beschreibungdescription
Mit einer Metallschicht gebildetes GehäuseHousing formed with a metal layer
Bisher werden Module mit Kunststoffgehäusen eingesetzt, welche mit einem silikonhaltigen Gel als Vergussmasse gefüllt sind. Dabei ergibt sich das Problem, dass das Silikon, da es als Isolation dient, vollständig frei von jeglichen Lufteinschlüssen sein muss. Der Prozessschritt in Modulfertigung ist daher sehr empfindlich. Außerdem wird bei einer Explosion des Moduls Silikon verbrannt und verschmutzt damit die Umgebung. Darüber hinaus sind diese Module nicht gasdicht, d.h., es kommt zu Schadgaseinfluss und Feuchtigkeitsschäden.So far, modules with plastic housings have been used, which are filled with a silicone-containing gel as a potting compound. The problem arises that the silicone, since it serves as insulation, must be completely free of any air pockets. The process step in module production is therefore very sensitive. In addition, if the module explodes, silicone is burned, polluting the environment. In addition, these modules are not gas-tight, i.e. there is an influence of harmful gas and moisture damage.
Wegen des beschriebenen Aufbauprinzips können die Abmessungen nicht beliebig reduziert werden. Dies gilt speziell für die Höhe. Auch brauchen die Module immer einen Deckel, um Bonddrähte bei den Fertigungsschritten zu schützen, sonst besteht Kurzschlussgefahr durch Eindrücken der Drähte.Because of the construction principle described, the dimensions cannot be reduced arbitrarily. This applies especially to the height. The modules also always need a cover to protect bond wires during the manufacturing steps, otherwise there is a risk of short-circuiting by pressing the wires in.
Aus der WO 03/030247 A2 ist eine Kontaktierungstechnik für Bauelemente, insbesondere Leistungshalbleiter, bekannt, bei der diese über eine auflaminierte Folie und eine darauf aufgebrachte leitende Schicht kontaktiert werden.A contacting technique for components, in particular power semiconductors, is known from WO 03/030247 A2, in which they are contacted via a laminated film and a conductive layer applied thereon.
Davon ausgehend liegt der Erfindung die Aufgabe zugrunde, eine Volumenreduktion in der Leistungselektronik durch Minimierung der Gehäuseabmessungen für Leistungsmodule herbeizuführen. Dabei sollen auch bisherigen Modulen anhaftende Schwä- chen beseitigt werden, die sich aus dem Einsatz von Silikon- vergussmasse und Deckeln sowie Schadgas- und Feuchtigkeitsempfindlichkeit ergeben.Based on this, the object of the invention is to bring about a reduction in volume in the power electronics by minimizing the housing dimensions for power modules. Weaknesses adhering to previous modules resulting from the use of silicone potting compound and lids as well as sensitivity to harmful gases and moisture should also be eliminated.
Diese Aufgabe wird durch die in den unabhängigen Ansprüchen angegebenen Erfindungen gelöst. Vorteilhafte Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. Dementsprechend wird in einem Verfahren zum Herstellen eines Gehäuses für eine auf einen Substrat angeordnete Schaltungsstruktur auf die Schaltungsstruktur eine Metallschicht so aufgebracht, dass sie zusammen mit dem Substrat das Gehäuse für die Schaltungsstruktur bildet.This object is achieved by the inventions specified in the independent claims. Advantageous configurations result from the dependent claims. Accordingly, in a method for producing a housing for a circuit structure arranged on a substrate, a metal layer is applied to the circuit structure such that it forms the housing for the circuit structure together with the substrate.
Durch das Verwenden einer Metallschicht, die die Schaltungsstruktur an allen Seiten umgibt, mit denen sie nicht am Substrat angeordnet ist, ergibt sich ein extrem flacher Aufbau des Gehäuses. Außerdem kann dieses aufgrund der Gasdichtheit der Metallschicht sehr einfach gasdicht gestaltet werden.The use of a metal layer which surrounds the circuit structure on all sides with which it is not arranged on the substrate results in an extremely flat structure of the housing. In addition, due to the gas tightness of the metal layer, this can be made gas-tight very easily.
Dazu kann das Substrat beispielsweise eine Metallstruktur aufweisen, die auf der Oberfläche des Substrats um die Schal- tungsstruktur herum verläuft. Sie bildet dadurch eine ArtFor this purpose, the substrate can have, for example, a metal structure that runs around the circuit structure on the surface of the substrate. It forms a kind
Ring, der die Schaltungsstruktur umgibt . Wird nun die Metallschicht mit direktem Kontakt an der Metallstruktur angeordnet, so ergibt sich ein gasdichter Übergang von der Metall- schicht zum Substrat und damit ein insgesamt gasdichtes Ge- häuse.Ring that surrounds the circuit structure. If the metal layer is now arranged with direct contact on the metal structure, there is a gas-tight transition from the metal layer to the substrate and thus an overall gas-tight housing.
Vorteilhaft weist die Schaltungsstruktur eine Isolationsschicht auf, auf die die Metallschicht aufgebracht wird. So wird verhindert, dass die Metallschicht ungewünschte elektri- sehe Verbindungen erzeugt.The circuit structure advantageously has an insulation layer to which the metal layer is applied. This prevents the metal layer from producing undesired electrical connections.
Die Isolationsschicht kann der Einfachheit halber großflächig, also beispielsweise auch auf die Metallstruktur aufgebracht werden, die die Schaltungsstruktur auf dem Substrat umgibt. Dann wird die Isolationsschicht vor Aufbringen der Metallschicht an der Metallstruktur beispielsweise mit Hilfe eines Lasers geöffnet.For the sake of simplicity, the insulation layer can be applied over a large area, that is, for example, also to the metal structure that surrounds the circuit structure on the substrate. The insulation layer is then opened, for example with the aid of a laser, before the metal layer is applied to the metal structure.
Die Isolationsschicht ist vorzugsweise mit einer oder mehre- ren der folgenden Vorgehensweisen aufgebracht: Auflaminieren einer Folie, Vorhanggießen, Tauchen, insbesondere einseitiges Tauchen, Sprühen, insbesondere elektrostatisches Sprühen, Drucken, insbesondere Siebdrucken, Overmolden, Dispensen, Spincoaten.The insulation layer is preferably applied using one or more of the following procedures: laminating a film, casting curtains, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, Printing, in particular screen printing, overmolding, dispensing, spin coating.
Zum Aufbringen der Metallschicht wird vorzugsweise ein physi- kalisches oder chemisches Abscheiden von Metall durchgeführt. Derartige physikalische Verfahren sind sputtern und bedampfen (Physical Vapor Deposition, PVD) . Das chemische Abscheiden kann aus gasförmiger Phase (Chemical Vapor Deposition, PVD) und/oder flüssiger Phase (Liquid Phase Chemical Vapor Deposi- tion) erfolgen. Denkbar ist auch, dass zunächst durch eines dieser Verfahren eine dünne Metallteilschicht beispielsweise aus Titan/Kupfer aufgetragen wird, auf der dann eine dickere Metallteilschicht beispielsweise aus Kupfer galvanisch abgeschieden wird.To apply the metal layer, a physical or chemical deposition of metal is preferably carried out. Such physical processes are sputtering and vapor deposition (Physical Vapor Deposition, PVD). Chemical deposition can take place from the gaseous phase (Chemical Vapor Deposition, PVD) and / or liquid phase (Liquid Phase Chemical Vapor Deposition). It is also conceivable that a thin metal partial layer, for example made of titanium / copper, is first applied by one of these methods, on which a thicker metal partial layer, for example made of copper, is then electrodeposited.
Ganz besondere Vorteile und Synergieeffekte ergeben sich, wenn die Schaltungsstruktur in einer ganz bestimmten Art und Weise hergestellt wird. Dazu ist auf dem Substrat ein Bauelement mit einer elektrischen Kontaktfläche angeordnet. Auf dem Substrat und dem Bauelement wird eine Schicht aus elektrisch isolierendem Material aufgebracht. Die elektrische Kontaktfläche des Bauelementes bleibt beim Aufbringen der Schicht aus elektrisch isolierendem Material frei und/oder wird nach dem Aufbringen der Schicht aus elektrisch isolierendem Mate- rial freigelegt, insbesondere durch Öffnen eines Fensters.Very special advantages and synergy effects result if the circuit structure is manufactured in a very specific way. For this purpose, a component with an electrical contact surface is arranged on the substrate. A layer of electrically insulating material is applied to the substrate and the component. The electrical contact surface of the component remains free when the layer of electrically insulating material is applied and / or is exposed after the layer of electrically insulating material has been applied, in particular by opening a window.
Weiterhin wird eine Schicht aus elektrisch leitendem Material auf der Schicht aus elektrisch isolierendem Material und der elektrischen Kontaktfläche des Bauelements aufgebracht. Die Schicht aus elektrisch isolierendem Material ist also eine Trägerschicht für die Schicht aus elektrisch leitendem Material.Furthermore, a layer of electrically conductive material is applied to the layer of electrically insulating material and the electrical contact surface of the component. The layer of electrically insulating material is therefore a carrier layer for the layer of electrically conductive material.
Die Schaltungsstruktur wird somit mit ganz ähnlichen Prozessschritten hergestellt wie das Gehäuse, was den Herstellungs- Vorgang erheblich rationalisiert und vereinfacht. Ein weiterer Synergieeffekt besteht darin, dass sowohl die Zuleitungen des Bauelements, die in der Schaltungsstruktur durch die Schicht aus elektrisch leitendem Material gebildet werden, als auch die zum Gehäuse gehörende Metallschicht sowie die isolierende Schicht und die Isolationsschicht in Schichttechnologie aufgebaut sind, also sehr flach sind. Insgesamt kön- nen so außerordentlich flache Leistungsmodule oder andere Schaltungen realisiert werden.The circuit structure is thus produced using very similar process steps to the housing, which considerably rationalizes and simplifies the manufacturing process. Another synergy effect is that both the leads of the component, which are in the circuit structure by the Layer of electrically conductive material are formed, as well as the metal layer belonging to the housing and the insulating layer and the insulation layer are constructed in layer technology, that is to say are very flat. Overall, extremely flat power modules or other circuits can be realized in this way.
Da das Bauelement auf dem Substrat angeordnet ist, bilden das Substrat und das Bauelement eine Oberflächenkontur. Vorzugs- weise folgt die Schicht aus elektrisch isolierendem Material der aus dem Substrat und dem Bauelement gebildeten Oberflächenkontur, d.h., dass die Schicht aus elektrisch isolierendem Material entsprechend der aus Substrat und Bauelement gebildeten Oberflächenkontur auf dieser Oberflächenkontur ver- läuft.Since the component is arranged on the substrate, the substrate and the component form a surface contour. The layer of electrically insulating material preferably follows the surface contour formed from the substrate and the component, i.e. the layer of electrically insulating material runs on this surface contour in accordance with the surface contour formed from the substrate and the component.
Dadurch dass die Schicht aus elektrisch isolierendem Material in ihrer Gesamtheit der aus Substrat und Bauelement gebildeten Oberflächenkontur folgt, ergeben sich, insbesondere wenn ein Leistungsbauelement als Bauelement verwendet wird, gleich zwei Vorteile. Zum einen ist eine noch ausreichende Dicke der Schicht aus elektrisch isolierendem Material über den dem Substrat abgewandten Kanten des Bauelements gewährleistet, so dass ein Durchschlag bei hohen Spannungen bzw. Feldstärken verhindert wird. Zum anderen ist die Schicht aus elektrisch isolierendem Material neben dem in der Regel sehr hohen Leistungsbauelement auf dem Substrat nicht so dick, dass ein Freilegen und Kontaktieren von Kontaktflächen auf Leiterbahnen des Substrats problematisch wäre.Because the layer of electrically insulating material in its entirety follows the surface contour formed from the substrate and the component, there are two advantages, in particular if a power component is used as the component. On the one hand, a sufficient thickness of the layer of electrically insulating material over the edges of the component facing away from the substrate is ensured, so that breakdown at high voltages or field strengths is prevented. On the other hand, in addition to the generally very high power component on the substrate, the layer of electrically insulating material is not so thick that it would be problematic to expose and contact contact surfaces on the substrate's conductor tracks.
Ebenso folgt vorteilhaft die Metallschicht und/oder die unter ihr angeordnete Isolationsschicht der aus dem Bauelement und dem Substrat und den zwischen dem Bauelement und dem Substrat und der Metallschicht und/der Isolationsschicht liegenden Schichten gebildeten Oberflächenkontur. Diese Oberflächenkontur kann von der durch das Substrat und das Bauelement vorgegebenen Oberflächenkontur insbesondere deshalb abweichen, weil die zwischenliegenden Schichten, also die Schicht aus elektrisch isolierendem Material und die Schicht aus elektrisch leitendem Material je nach Anwendungszweck strukturiert sein können. Wenn die Schicht aus elektrisch isolierendem Ma- terial als Trägerschicht für die Schicht aus elektrisch leitendem Material dient, so dient diese wiederum als Trägerschicht für die Isolationsschicht, die ihrerseits als Trägerschicht für die Metallschicht dient. Dabei ist jede Schicht in engem, dichtem Kontakt zu ihren Nachbarschichten und haf- tet an diesen.Likewise, the metal layer and / or the insulation layer arranged below it advantageously follows the surface contour formed by the component and the substrate and the layers lying between the component and the substrate and the metal layer and / or the insulation layer. This surface contour can deviate from the surface contour given by the substrate and the component in particular, because the intermediate layers, ie the layer made of electrically insulating material and the layer made of electrically conductive material, can be structured depending on the application. If the layer of electrically insulating material serves as a carrier layer for the layer of electrically conductive material, this in turn serves as a carrier layer for the insulation layer, which in turn serves as a carrier layer for the metal layer. Each layer is in close, dense contact with its neighboring layers and adheres to them.
Es liegt natürlich auch im Rahmen der Erfindung bei einem Substrat, auf dem mehrere Bauelemente mit Kontaktflächen angeordnet sind, und/oder bei Bauelementen mit mehreren Kon- taktflächen entsprechend vorzugehen.It is of course also within the scope of the invention for a substrate on which a plurality of components with contact surfaces are arranged and / or for components with a plurality of contact surfaces to be carried out accordingly.
Die Dicke der Schicht aus elektrisch isolierendem Material und/oder die Dicke der Isolationsschicht weicht, um der Oberflächenkontur zu folgen, in ihrem geradlinig verlaufenden Be- reich um weniger als 50 % von ihrer Dicke über den Bauelement in ihrem dort geradlinig verlaufenden Bereich ab, insbesondere um weniger als 20 %. Vorzugsweise sind die Dicken in etwa gleich, weichen also um weniger als 5 % oder sogar weniger als 1 % voneinander ab. Die Prozentangaben beziehen sich da- bei insbesondere auf die Dicke der Schicht über dem Bauelement in deren geradlinig verlaufenden Bereich, die dementsprechend 100 % angibt. Auf den geradlinig verlaufenden Bereich wird abgestellt, da die Schicht in Innenkanten von Substrat und Bauelement in der Regel dicker, über dem Substrat abgewandten Kanten des Bauelements in der Regel dünner verläuft .The thickness of the layer of electrically insulating material and / or the thickness of the insulation layer deviates, in order to follow the surface contour, in its rectilinear region by less than 50% of its thickness over the component in its rectilinear region, in particular by less than 20%. The thicknesses are preferably approximately the same, that is to say deviate from one another by less than 5% or even less than 1%. The percentages relate in particular to the thickness of the layer above the component in its rectilinear area, which accordingly indicates 100%. The rectilinear region is used because the layer in the inner edges of the substrate and the component generally runs thicker and edges of the component facing away from the substrate generally run thinner.
Zur Kontaktierung des Bauelements mit dem Substrat weist das Substrat vorzugsweise eine elektrische Kontaktfläche auf, die beim Aufbringen der Schicht aus elektrisch leitendem Material frei bleibt oder nach dem Aufbringen der Schicht aus elektrisch leitendem Material freigelegt wird und auf die die Schicht aus elektrisch leitendem Material ebenfalls aufgebracht wird. So wird die Kontaktfläche des Bauelements über die Schicht aus elektrisch leitendem Material mit der Kontaktfläche des Substrats verbunden.For contacting the component with the substrate, the substrate preferably has an electrical contact surface which remains free when the layer of electrically conductive material is applied or is exposed after the layer of electrically conductive material has been applied and to which the Layer of electrically conductive material is also applied. The contact surface of the component is connected to the contact surface of the substrate via the layer of electrically conductive material.
Die Kontaktfläche des Bauelements und die Kontaktfläche des Substrats sind vorzugsweise in etwa gleich groß, um einen durchgängigen Stromfluss zu gewährleisten.The contact area of the component and the contact area of the substrate are preferably approximately the same size in order to ensure a continuous current flow.
Die elektrische Kontaktfläche des Bauelements kann beim Aufbringen der Schicht aus elektrisch leitendem Material freigelassen und/oder später freigelegt werden. Das vollständige oder partielle Freilassen schon beim Aufbringen lässt sich besonders vorteilhaft verwirklichen, wenn die Schicht aus e- lektrisch isolierendem Material mit Öffnungen aufgebracht wird. Dann lässt sich nämlich von vorneherein eine Schicht aus elektrisch isolierendem Material mit einer oder mehreren entsprechenden Öffnungen bzw. Fenstern verwenden, die sich beispielsweise zuvor durch kostengünstiges Ausstanzen oder Ausschneiden schaffen lassen. ird durch das Freilegen der Kontaktfläche ein Fenster mit mehr als 60 % der Größe der Seite und/oder Fläche des Bauelementes geöffnet, an der das Fenster geöffnet wird, insbeson- dere mehr als 80 %, so kann das Verfahren für Leistungsbauelemente verwendet werden, deren Kontaktfläche eine entsprechende Größe aufweist. Um eine saubere Kantenverarbeitung zu gewährleisten, sollte die Größe des Fensters aber andererseits nicht mehr als 99, 9 % der Größe der Seite und/oder Flä- ehe des Bauelementes betragen, an der das Fenster geöffnet wird, insbesondere nicht mehr als 99 % und weiter bevorzugt nicht mehr als 95 %. Das Fenster wird insbesondere an der größten und/oder an der vom Substrat abgewandten Seite des Bauelementes geöffnet und hat vorzugsweise eine absolute Grö- ße von mehr als 50 qmm, insbesondere mehr als 70 qmm. Als Substrate kommen beliebige Schaltungsträger auf organischer oder anorganischer Basis in Frage. Solche Substrate sind beispielsweise PCB (Printed Circuit Board)-, DCB-, IM (Insulated Metal)-, HTCC (High Temperature Cofired Ceramics)- und LTCC (Low Temperature Cofired Ceramics) -Substrate.The electrical contact surface of the component can be left exposed when the layer of electrically conductive material is applied and / or later exposed. The complete or partial release already during application can be realized particularly advantageously if the layer of electrically insulating material is applied with openings. Then a layer of electrically insulating material with one or more corresponding openings or windows can be used from the outset, which can be created beforehand, for example, by inexpensive punching out or cutting out. If a window is opened by exposing the contact area with more than 60% of the size of the side and / or area of the component on which the window is opened, in particular more than 80%, the method can be used for power components whose Contact surface has a corresponding size. On the other hand, to ensure clean edge processing, the size of the window should not be more than 99.9% of the size of the side and / or area of the component on which the window is opened, in particular not more than 99% and further preferably not more than 95%. The window is opened in particular on the largest and / or on the side of the component facing away from the substrate and preferably has an absolute size of more than 50 qmm, in particular more than 70 qmm. Any substrates on an organic or inorganic basis can be used as substrates. Such substrates are, for example, PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
Die Schicht aus elektrisch isolierendem Material und die Isolationsschicht sind insbesondere aus Kunststoff. Je nach Weiterverarbeitung können diese Schichten fotoempfindlich oder nicht fotoempfindlich sein.The layer of electrically insulating material and the insulation layer are in particular made of plastic. Depending on the further processing, these layers can be photosensitive or non-photosensitive.
Sie werden vorzugsweise mit einer der oder mehreren der folgenden Vorgehensweise aufgebracht: Auflaminieren einer Folie, Vorhanggießen, Tauchen, insbesondere einseitiges Tauchen, Sprühen, insbesondere elektrostatisches Sprühen, Drucken, insbesondere Siebdrucken, Overmolden, Dispensen, Spincoaten.They are preferably applied using one or more of the following procedures: lamination of a film, curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating.
Für das Aufbringen der Schicht aus elektrisch leitendem Material gilt das zum Aufbringen der Metallschicht geschriebene.What is written for the application of the metal layer applies to the application of the layer of electrically conductive material.
Vorzugsweise wird ein Substrat mit einer Oberfläche verwendet, die mit einem oder mehreren Bauelementen, insbesondere Leistungsbauelemente bestückt ist, auf deren jedem je ein o- der mehrere zu kontaktierende Kontaktflächen vorhanden ist oder sind, wobei die Schicht aus elektrisch isolierendem Material auf dieser Oberfläche unter Vakuum aufgebracht wird, so dass die Schicht aus elektrisch isolierendem Material diese Oberfläche einschließlich der Bauelemente und gegebenenfalls auch der Kontaktflächen eng anliegend bedeckt und auf dieser Oberfläche einschließlich des Substrats und der Bauelemente haftet.Preferably, a substrate with a surface is used which is equipped with one or more components, in particular power components, on each of which one or more contact surfaces are or are present, the layer of electrically insulating material on this surface under vacuum is applied so that the layer of electrically insulating material closely covers this surface including the components and optionally also the contact surfaces and adheres to this surface including the substrate and the components.
Die Schicht aus elektrisch isolierendem Material ist dabei so gestaltet, dass ein Höhenunterschied von bis zu 100.0 μm über- wunden werden kann. Der Höhenunterschied ist unter anderem durch die Topologie des Substrats und durch die auf dem Substrat angeordneten Bauelemente und Leiterbahnen verursacht. Die Dicke der Schicht aus elektrisch isolierendem Material kann 10 μm bis 500 μm betragen. Vorzugsweise wird bei dem Verfahren eine Schicht aus elektrisch isolierendem Material mit einer Dicke von 25 μm bis 150 μm aufgebracht.The layer of electrically insulating material is designed so that a height difference of up to 100.0 μm can be overcome. The height difference is caused, among other things, by the topology of the substrate and by the components and interconnects arranged on the substrate. The thickness of the layer of electrically insulating material can be 10 μm to 500 μm. In the method, a layer of electrically insulating material with a thickness of 25 μm to 150 μm is preferably applied.
In einer weiteren Ausgestaltung wird das Aufbringen so oft wiederholt, bis eine bestimmte Dicke der Schicht aus elektrisch isolierendem Material erreicht ist. Beispielsweise werden Teilschichten aus elektrisch isolierendem Material gerin- gerer Dicke zu einer Schicht aus elektrisch isolierendem Material höherer Dicke bearbeitet. Diese Teilschichten aus e- lektrisch isolierendem Material bestehen vorteilhaft aus einer Art Kunststoffmaterial. Denkbar ist aber auch, dass die Teilschichten aus elektrisch isolierendem Material aus mehre- ren unterschiedlichen Kunststoffmaterialien bestehen. Es resultiert eine aus Teilschichten aufgebaute Schicht aus elektrisch isolierendem Material.In a further embodiment, the application is repeated until a certain thickness of the layer of electrically insulating material is reached. For example, partial layers of electrically insulating material of smaller thickness are processed to form a layer of electrically insulating material of higher thickness. These partial layers made of electrically insulating material advantageously consist of a type of plastic material. However, it is also conceivable that the partial layers made of electrically insulating material consist of several different plastic materials. The result is a layer made of partial layers of electrically insulating material.
In einer besonderen Ausgestaltung wird zum Freilegen der elektrischen Kontaktfläche des Bauelements ein Fenster in der Schicht aus elektrisch isolierendem Material durch Laserabla- tion geöffnet . Eine Wellenlänge eines dazu verwendeten Lasers beträgt zwischen 0,1 μm und 11 μm. Die Leistung des Lasers beträgt zwischen 1 Watt und 100 Watt. Vorzugsweise wird ein C02-Laser mit einer Wellenlänge von 9,24 μm verwendet. DasIn a special embodiment, a window in the layer of electrically insulating material is opened by laser ablation to expose the electrical contact surface of the component. A wavelength of a laser used for this is between 0.1 μm and 11 μm. The power of the laser is between 1 watt and 100 watts. A C02 laser with a wavelength of 9.24 μm is preferably used. The
Öffnen der Fenster erfolgt dabei ohne eine Beschädigung eines eventuell unter Schicht aus isolierendem Material liegenden Chipkontakts aus Aluminium, Gold oder Kupfer.The windows are opened without damaging a chip contact made of aluminum, gold or copper, which may be under a layer of insulating material.
In einer weiteren Ausgestaltung wird eine fotoempfindliche Schicht aus elektrisch isolierendem Material verwendet und zum Freilegen der elektrischen Kontaktfläche des Bauelements ein Fenster durch einen fotolitergrafischen Prozess geöffnet. Der fotolitergrafische Prozess umfasst ein Belichten der fo- toempfindlichen Schicht aus elektrisch isolierendem Material und ein Entwickeln und damit Entfernen der belichteten oder nicht-belichteten Stellen der Schicht aus elektrisch isolierendem Material.In a further embodiment, a photosensitive layer made of electrically insulating material is used and a window is opened by a photolithographic process to expose the electrical contact surface of the component. The photolithographic process comprises exposing the photosensitive layer of electrically insulating material and developing and thus removing the exposed or unexposed areas of the layer of electrically insulating material.
Nach dem Öffnen der Fenster erfolgt gegebenenfalls ein Reini- gungsschritt, bei dem Reste der Schicht aus elektrisch isolierendem Material entfernt werden. Der Reinigungsschritt erfolgt beispielsweise nasschemisch. Denkbar ist insbesondere auch ein Plasmareinigungsverfahren.After opening the windows, there may be a cleaning step in which remnants of the layer of electrically insulating material are removed. The cleaning step is carried out, for example, by wet chemistry. In particular, a plasma cleaning process is also conceivable.
Das zur der Schicht aus elektrisch isolierendem Material Geschriebene findet analog auch für die Isolationsschicht Anwendung.What is written about the layer of electrically insulating material is also used analogously for the insulation layer.
In einer weiteren Ausgestaltung wird eine Schicht aus elekt- risch leitendem Material aus mehreren übereinander angeordneten Teilschichten aus unterschiedlichen, elektrisch leitenden Materialien verwendet. Es werden beispielsweise verschiedene Metalllagen übereinander aufgetragen. Die Anzahl der Teilschichten bzw. Metalllagen beträgt insbesondere 2 bis 5. Durch die aus mehreren Teilschichten aufgebaute Schicht aus elektrisch leitendem Material kann beispielsweise eine als. Diffusionsbarriere fungierende Teilschicht integriert sein. Eine derartige Teilschicht besteht beispielsweise aus einer Titan-Wolfram-Legierung (TiW) . Vorteilhafter Weise wird bei einem mehrschichtigen Aufbau direkt auf der zu kontaktierenden Oberfläche eine die Haftung vermittelnde oder verbessernde Teilschicht aufgebracht. Eine derartige Teilschicht besteht beispielsweise aus Titan.In a further embodiment, a layer of electrically conductive material made of several partial layers of different, electrically conductive materials arranged one above the other is used. For example, different metal layers are applied one above the other. The number of sub-layers or metal layers is, in particular, 2 to 5. Due to the layer made of several sub-layers made of electrically conductive material, for example, an as. Diffusion barrier functioning sub-layer can be integrated. Such a partial layer consists, for example, of a titanium-tungsten alloy (TiW). In the case of a multi-layer structure, a partial layer that promotes or improves adhesion is advantageously applied directly to the surface to be contacted. Such a partial layer consists, for example, of titanium.
Entsprechend kann für die Metallschicht verfahren werden.The same can be done for the metal layer.
In einer besonderen Ausgestaltung wird nach dem flächigen Kontaktieren in/oder auf der Schicht aus dem elektrisch leitenden Material mindestens eine Leiterbahn erzeugt. Die Lei- terbahn kann auf der Schicht aufgetragen werden. Insbesondere wird zum Erzeugen der Leiterbahn ein Strukturieren der Schicht durchgeführt. Dies bedeutet, dass die Leiterbahn in dieser Schicht erzeugt wird. Die Leiterbahn dient beispielsweise der elektrischen Kontaktierung eines Bauelements.In a special embodiment, at least one conductor track is produced from the electrically conductive material after the two-dimensional contacting in / or on the layer. The conductor track can be applied to the layer. In particular, the layer is structured to produce the conductor track. This means that the conductor track in this layer is generated. The conductor track is used, for example, to make electrical contact with a component.
Das Strukturieren erfolgt üblicherweise in einem fotolitergrafischen Prozess. Dazu kann an der elektrisch leitenden Schicht ein Fotolack aufgetragen, getrocknet und anschließend belichtet und entwickelt werden. Unter Umständen folgt ein Temperschritt, um den aufgetragenen Fotolack gegenüber nachfolgenden Behandlungsprozessen zu stabilisieren.The structuring is usually carried out in a photolithographic process. For this purpose, a photoresist can be applied to the electrically conductive layer, dried and then exposed and developed. A tempering step may follow in order to stabilize the applied photoresist against subsequent treatment processes.
Als Fotolack kommen herkömmliche positive und negative Re- sists (Beschichtungsmaterialien) in Frage. Das Auftragen des Fotolacks erfolgt beispielsweise durch einen Sprüh- oder Tauchprozess. Electro-Deposition (elektrostatisches oder elektrophoretisches Abscheiden) ist ebenfalls denkbar.Conventional positive and negative resists (coating materials) can be used as photoresist. The photo lacquer is applied, for example, by a spraying or dipping process. Electro-deposition (electrostatic or electrophoretic deposition) is also conceivable.
Statt eines Fotolacks kann auch ein anderes strukturierbares Material mit einer oder mehreren der folgenden Vorgehensweise aufgebracht werden: Vorhanggießen, Tauchen, insbesondere ein- seitiges Tauchen, Sprühen, insbesondere elektrostatischesSprühen, Drucken, insbesondere Siebdrucken, Qvermolden, Dispensen, Spincoaten, Auflaminieren einer Folie.Instead of a photoresist, another structurable material can also be applied using one or more of the following procedures: curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, qing, dispensing, spin coating, laminating a film.
Zum Strukturieren können auch fotoempfindliche Folien einge- setzt werden, die auflaminiert und vergleichbar mit der aufgetragenen Fotolackschicht belichtet und entwickelt werden.For structuring, photosensitive foils can also be used, which are laminated on and exposed and developed in a manner comparable to the applied photoresist layer.
Zum Erzeugen der Leiterbahn kann beispielsweise wie folgt vorgegangen werden. In einem ersten Teilschritt wird die elektrisch leitende Schicht strukturiert und in einem darauf folgenden Teilschritt wird auf die erzeugte Leiterbahn eine weitere Metallisierung aufgebracht. Durch die weitere Metallisierung wird die Leiterbahn verstärkt. Beispielsweise wird auf der durch Strukturieren erzeugten Leiterbahn Kupfer gal- vanisch mit einer Dicke von 1 μm bis 400 μm abgeschieden. Danach wird die Fotolackschicht bzw. die auflaminierte Folie oder das alternativ verwendete strukturierbare Material abge- löst. Dies gelingt beispielsweise mit einem organischen Lösungsmittel, einem alkalischen Entwickler oder dergleichen. Durch nachfolgendes Differenzätzen wird die flächige, nicht mit der Metallisierung verstärkte, metallisch leitende Schicht wieder entfernt. Die verstärkte Leiterbahn bleibt erhalten. In einer besonderen Ausgestaltung werden zum Herstellen einer mehrlagigen Vorrichtung die Schritte Auflaminieren, Freilegen, Kontaktieren und Erzeugen von Leiterbahnen mehrmals durchgeführt.For example, the following can be used to generate the conductor track. In a first sub-step, the electrically conductive layer is structured, and in a subsequent sub-step, a further metallization is applied to the conductor track generated. The conductor track is reinforced by the further metallization. For example, copper is electroplated on the conductor track created by structuring with a thickness of 1 μm to 400 μm. Then the photoresist layer or the laminated film or the alternatively used structurable material is removed. solves. This can be done, for example, with an organic solvent, an alkaline developer or the like. Subsequent differential etching removes the flat, metallically conductive layer that is not reinforced with the metallization. The reinforced conductor track is retained. In a special embodiment, the steps of laminating, exposing, contacting and producing conductor tracks are carried out several times to produce a multilayer device.
Durch das Aufbringen der Schicht aus elektrisch isolierendem Material ergeben sich folgende Vorteile:Applying the layer of electrically insulating material has the following advantages:
- Anwendung bei hohen Temperaturen. Eine Schicht aus elektrisch isolierendem Material ist bei geeigneter Materialwahl hitzebeständig bis 300°C.- Use at high temperatures. With a suitable choice of material, a layer of electrically insulating material is heat-resistant up to 300 ° C.
- Geringere Prozesskosten.- Lower process costs.
- Es sind hohe Isolationsfeldstärken durch Verwendung dicker Isolationslagen möglich.- High insulation field strengths are possible by using thick insulation layers.
- Hoher Durchsatz, z.B. können DCB-Substrate im Nutzen pro- zessiert werden.- high throughput, e.g. DCB substrates can be processed in the benefit.
- Homogene Isolationseigenschaften, da Lufteinschlüsse durch die Verarbeitung der Schicht aus elektrisch isolierendem Material im Vakuum verhindert werden.- Homogeneous insulation properties, since air pockets are prevented by processing the layer of electrically insulating material in a vacuum.
- Die gesamte Chipkontaktfläche kann genützt werden, so dass hohe Ströme abgeleitet werden können.- The entire chip contact area can be used so that high currents can be derived.
- Durch die flächige Kontaktierung können die Chips homogen angesteuert werden.- The chips can be controlled homogeneously due to the flat contact.
- Die Induktivität des Kontaktes bei einer Kontaktfläche ist durch die flächenhafte Geometrie kleiner als beim Dickdrahtbonden.- The inductance of the contact in a contact area is smaller due to the areal geometry than with thick wire bonding.
- Die Kontaktierung führt zu hoher Zuverlässigkeit bei Vibra- tions- und mechanischer Schockbelastung.- The contacting leads to high reliability in the case of vibration and mechanical shock loads.
- Höhere Lastwechselfestigkeit im Vergleich zu kongurierenden Methoden wegen geringerer thermomechanischer Spannungen. - Es sind mehrere Verdrahtungsebenen zugänglich.- Higher fatigue strength compared to conguring methods due to lower thermomechanical stresses. - Several wiring levels are accessible.
- Die beschriebene, planare Verbindungstechnik beansprucht eine geringe Bauhöhe. Es resultiert ein kompakter Aufbau. - Bei mehrlagigen Verbindungsebenen sind großflächige Metallisierungslagen zur Abschirmung realisierbar. Dies wirkt sich insbesondere auf das EMV (elektromagnetische Verträglichkeit) -Verhalten der Schaltung (Störemission, Störfes- tigkeit) sehr positiv aus.- The described, planar connection technology requires a low overall height. The result is a compact structure. - With multi-layer connection levels, large-area metallization layers can be implemented for shielding. This has a particularly positive effect on the EMC (electromagnetic compatibility) behavior of the circuit (interference emissions, immunity to interference).
In Verbindung mit der beschriebenen Gehäusetechnologie können Module ohne Bonddrähte, ohne Vergussmasse und dadurch ohne Kunststoffgehäuse hergestellt und eingesetzt werden. Das Ge- häuse kann dadurch gasdicht gemacht werden, dass die beispielsweise in Form einer Folie realisierte Isolationsschicht alle Teile der Schaltungsstruktur abdeckt und die Isolationsschicht anschließend metallisiert wird, indem eine Metallschicht aufgebracht wird.In conjunction with the housing technology described, modules can be produced and used without bond wires, without potting compound and therefore without a plastic housing. The housing can be made gastight in that the insulation layer, for example in the form of a film, covers all parts of the circuit structure and the insulation layer is subsequently metallized by applying a metal layer.
Bevorzugte und vorteilhafte Ausgestaltung der Vorrichtung ergeben sich aus dem bevorzugten Ausgestaltungen des Verfahrens und umgekehrt .Preferred and advantageous configurations of the device result from the preferred configurations of the method and vice versa.
Weitere Merkmale und Vorteile der Erfindung lassen sich der Beschreibung eines Ausführungsbeispiels anhand der Zeichnung entnehmen. Dabei zeigt:Further features and advantages of the invention can be found in the description of an exemplary embodiment with reference to the drawing. It shows:
Figur 1 eine Vorrichtung mit einem mit einer Metallschicht gebildeten Gehäuse;1 shows a device with a housing formed with a metal layer;
Figur 2 die Vorrichtung nach Figur 1 im Bereich eines Lastanschlusses; Figur 3 einen Querschnitt durch die Vorrichtung nach Figur 1.Figure 2 shows the device of Figure 1 in the area of a load connection; FIG. 3 shows a cross section through the device according to FIG. 1.
In den Figuren erkennt man eine Bodenplatte 1 beispielsweise aus Kupfer. Auf dieser Bodenplatte 1 ist über eine untere Kupfer-Metallisierung 2 ein Substrat 3 angeordnet. Dieses Substrat 3 ist beispielsweise ein DCB-Substrat, das eine Schicht aus Keramikmaterial, die auf die untere Oberfläche des Substrats 3 aufgebrachte untere Kupfermetallisierung 2 und eine auf eine von der unteren Oberfläche abgekehrten Oberfläche des Substrats 3 aufgebrachte Schicht 4 aus Kupfer aufweist. Die Schicht 4 auf der oberen Oberfläche des Substrats 3 ist bereichsweise bis auf die obere Oberfläche des Substrats 3 herab entfernt. Durch die Schicht 4 aus Kupfer werden so Leiterbahnen auf dem Substrat 3 gebildet.A base plate 1, for example made of copper, can be seen in the figures. A substrate 3 is arranged on this base plate 1 via a lower copper metallization 2. This substrate 3 is, for example, a DCB substrate, which has a layer of ceramic material, the lower copper metallization 2 applied to the lower surface of the substrate 3 and one on a side facing away from the lower surface Surface of the substrate 3 has applied layer 4 of copper. The layer 4 on the upper surface of the substrate 3 is removed in some areas down to the upper surface of the substrate 3. Conductor tracks are thus formed on the substrate 3 through the layer 4 of copper.
Auf die von dem Substrat 3 abgekehrte Oberfläche der verbliebenen Schicht 4 aus Kupfer sind ein oder mehrere Bauelemente 9 in Form von Halbleiterchips aufgebracht, die zueinander gleich und/oder voneinander verschieden sein können.One or more components 9 in the form of semiconductor chips are applied to the surface of the remaining copper layer 4 facing away from the substrate 3, which can be identical and / or different from one another.
Das Bauelement 9, das vorzugsweise ein Leistungshalbleiterchip ist, kontaktiert mit einer nicht dargestellten Kontaktfläche, die auf einer der Schicht 4 aus Kupfer zugekehrten unteren Oberfläche des Bauelements 9 vorhanden ist, flächig die obere Oberfläche der Schicht 4 aus Kupfer. Beispielsweise ist diese Kontaktfläche mit der Schicht 4 aus Kupfer verlötet.The component 9, which is preferably a power semiconductor chip, contacts the upper surface of the layer 4 made of copper with a contact surface, not shown, which is present on a lower surface of the component 9 facing the layer 4 of copper. For example, this contact surface is soldered to the layer 4 made of copper.
Auf der von der Schicht 4 aus Kupfer und der der unterenOn that of layer 4 of copper and that of the lower one
Oberfläche abgekehrten oberen Oberfläche des Bauelements 9 ist ein Kontakt mit einer vom Bauelement 9 abgekehrten Kontaktfläche vorhanden.Surface facing away from the upper surface of the component 9 is in contact with a contact surface facing away from the component 9.
Ist beispielsweise das Bauelement 9 ein Transistor, ist die Kontaktfläche auf der unteren Oberfläche des Bauelements 9 die Kontaktfläche eines Kollektor- bzw. Drain-Kontaktes und der Kontakt auf der oberen Oberfläche des Bauelements 9 ein Emitter-Source-Kontakt, dessen Kontaktfläche die genannte Kontaktfläche ist.For example, if the component 9 is a transistor, the contact area on the lower surface of the component 9 is the contact area of a collector or drain contact and the contact on the upper surface of the component 9 is an emitter-source contact, the contact area of which is the said contact area is.
Die gesamte Oberfläche des mit dem Bauelement 9 bestückten Substrats 3 ist durch die freiliegenden Teile der oberen Oberfläche der Substratschicht 3, die obere und seitlichen Oberflächen der Schicht 4 aus Kupfer außerhalb des Bauelements 9 und durch die freie Oberfläche des Bauelements 9 selbst gegeben, die durch dessen obere Oberfläche und die seitlichen Oberflächen dieses Bauelements 9 bestimmt ist.The entire surface of the substrate 3 equipped with the component 9 is due to the exposed parts of the upper surface of the substrate layer 3, the upper and side surfaces of the layer 4 of copper outside the component 9 and the free surface of the component 9 given itself, which is determined by the upper surface and the lateral surfaces of this component 9.
Auf die gesamte Oberfläche des mit dem Bauelement 9 bestück- ten Substrats 3 ist eine Schicht 7 aus elektrisch isolierendem Material unter Vakuum aufgebracht, so dass die Schicht 7 aus elektrisch isolierendem Material die Oberfläche des mit dem Bauelement 9 bestückten Substrats 3 mit den Kontaktflächen eng anliegend bedeckt und auf dieser Oberfläche haftet. Die Schicht 7 aus elektrisch isolierendem Material folgt dabei der durch die freiliegenden Teile der oberen Oberfläche der Substratschicht 3, der oberen Oberfläche der Schicht 4 aus Kupfer außerhalb des Bauelements 9 und durch die freie Oberfläche des Bauelements 9 selbst, die durch die obere 0- berfläche und die seitliche Oberfläche dieses Bauelements9 bestimmt ist, gegebenen Oberflächenkontur.A layer 7 of electrically insulating material is applied under vacuum to the entire surface of the substrate 3 equipped with the component 9, so that the layer 7 made of electrically insulating material closely fits the surface of the substrate 3 equipped with the component 9 with the contact surfaces covered and adheres to this surface. The layer 7 made of electrically insulating material follows that through the exposed parts of the upper surface of the substrate layer 3, the upper surface of the layer 4 made of copper outside the component 9 and through the free surface of the component 9 itself, which through the upper surface and the lateral surface of this component 9 is determined, given surface contour.
Die Schicht 7 aus elektrisch isolierendem Material dient als Isolator und als Träger einer auf ihr aufgebrachten Schicht 11 aus elektrisch leitendem Material.The layer 7 made of electrically insulating material serves as an insulator and as a carrier of a layer 11 made of electrically conductive material applied to it.
Typische Dicken der Schicht 7 aus elektrisch isolierendem Material liegen im Bereich von 25 bis 150 μm, wobei größere Dicken auch aus Schichtfolgen von dünneren Teilschichten aus elektrisch isolierendem Material erreicht werden können. Damit lassen sich vorteilhafter Weise Isolationsfeldstärken im Bereich von einigen 10 kV/mm realisieren.Typical thicknesses of the layer 7 made of electrically insulating material are in the range from 25 to 150 μm, and larger thicknesses can also be achieved from layer sequences of thinner partial layers made of electrically insulating material. Isolation field strengths in the range of a few 10 kV / mm can thus advantageously be realized.
Jede zu kontaktierende Kontaktfläche auf der Oberfläche des Substrats 3 einschließlich des Bauelements 9 ist durch Öffnen jeweiliger Fenster in der Schicht 7 aus elektrisch isolierendem Material freigelegt .Each contact surface to be contacted on the surface of the substrate 3 including the component 9 is exposed by opening respective windows in the layer 7 made of electrically insulating material.
Eine zu kontaktierende Kontaktfläche ist nicht nur eine Kon- taktfläche auf dem Bauelement 9, sondern kann auch jeder durch Öffnen eines Fensters in der Schicht 7 aus elektrisch isolierendem Material freigelegte Bereich der oberen Oberflä- ehe der Schicht 4 aus Kupfer oder einem sonstigen Metall sein.A contact surface to be contacted is not only a contact surface on the component 9, but also any region of the upper surface exposed by opening a window in the layer 7 made of electrically insulating material. Before layer 4 is made of copper or another metal.
Die Größe des Fensters, das zum Kontaktieren der Kontaktflä- ehe des Bauelementsgeöffnet ist, beträgt mehr als 60 % der Größe des Bauelements, insbesondere mehr als 80 %.The size of the window that is open for contacting the contact area of the component is more than 60% of the size of the component, in particular more than 80%.
Das Öffnen der Fenster in der Schicht 7 aus elektrisch isolierendem Material ist vorzugsweise durch Laserablation vor- genommen.The windows in the layer 7 made of electrically insulating material are preferably opened by laser ablation.
Die von der Schicht 7 aus elektrisch isolierendem Material freigelegten Kontaktflächen des Substrats und des Bauelements sind mit einer Schicht 11 aus elektrisch leitendem Material, vorzugsweise Metall, flächig kontaktiert.The contact surfaces of the substrate and the component exposed by the layer 7 made of electrically insulating material are in surface contact with a layer 11 made of electrically conductive material, preferably metal.
Beispielsweise kann die Schicht 11 aus elektrisch leitendem Material ganzflächig sowohl auf jede Kontaktfläche als auch auf die von der Oberfläche des Substrats 3 abgekehrte obere Oberfläche der Schicht 7 aus elektrisch isolierendem Material aufgebracht und danach beispielsweise fotolitergrafisch so strukturiert sein, dass jede Kontaktfläche flächig kontaktiert bleibt und über die Kontakt lächen und die Schicht 7 aus elektrisch isolierendem Material verlaufende Leiterbahnen gegeben sind.For example, the layer 11 made of electrically conductive material can be applied over the entire surface both to each contact surface and to the upper surface of the layer 7 made of electrically insulating material facing away from the surface of the substrate 3, and can then be structured, for example by photolithography, in such a way that each contact surface remains in contact with the surface and Laugh over the contact and the layer 7 made of electrically insulating material extending conductor tracks are given.
Vorzugsweise wurden dazu folgende Prozessschritte (semiadditiver Aufbau) durchgeführt:The following process steps (semi-additive construction) were preferably carried out:
- Sputtern einer Ti-Haftschicht von ca. 100 nm Dicke und ei- ner KupferleitSchicht von ca. 200 nm Dicke.- Sputtering a Ti adhesive layer of approx. 100 nm thickness and a copper conductive layer of approx. 200 nm thickness.
- Fotolitergrafie unter Verwendung dicker Lackschichten oder von Fotofolien.- Photolithography using thick layers of lacquer or photo foils.
- Galvanische Verstärkung der freientwickelten Bereiche mit einer Schicht aus elektrisch leitendem Material. Hier sind Schichtdicken bis zu 500 μm möglich.- Galvanic reinforcement of the freely developed areas with a layer of electrically conductive material. Layer thicknesses of up to 500 μm are possible here.
- LackentSchichtung und Differenzsetzen von Kupfer und Titan. Es ergibt sich eine Vorrichtung mit einem Substrat 3 mit einem Bauelement 9, wobei auf der von dem Substrat 3 und dem Bauelement 9 gebildeten Oberfläche elektrische Kontaktflächen angeordnet sind, bei der auf der Oberfläche ein Isolator in Form einer Schicht 7 aus elektrisch isolierendem Material aufgebracht ist, die eng an der Oberfläche anliegt und an der Oberfläche haftet, und bei der die Schicht 7 aus elektrisch isolierendem Material bei den Kontaktflächen jeweils Fenster aufweist, in welchen diese Kontaktflächen frei von der Schicht 7 aus elektrisch isolierendem Material und flächig mit einer Schicht 11 aus elektrisch leitendem Material kontaktiert sind. Auf dem Substrat 3 ist damit eine Schaltungsstruktur angeordnet, die das Bauelement 9, die Schicht 7 aus elektrisch isolierendem Material und die Schicht 11 aus e- lektrisch leitendem Material enthält.- Paint decoating and differential setting of copper and titanium. The result is a device with a substrate 3 with a component 9, electrical contact surfaces being arranged on the surface formed by the substrate 3 and the component 9, in which an insulator in the form of a layer 7 of electrically insulating material is applied to the surface , which lies close to the surface and adheres to the surface, and in which the layer 7 made of electrically insulating material has windows at the contact surfaces, in which these contact surfaces are free of the layer 7 made of electrically insulating material and with a layer 11 electrically conductive material are contacted. A circuit structure is thus arranged on the substrate 3, which contains the component 9, the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material.
Die Schaltungsstruktur 7, 9, 10, 11 weist weiterhin eine Isolationsschicht 10 in Form einer auf die Schicht 7 aus elektrisch isolierendem Material und die Schicht 11 aus elektrisch leitendem Material auflaminierte Folie auf. An den Rändern und Übergängen zu Anschlüssen unterhalb der Isolationsschicht 10 ist eine Metallstruktur 6 in Form eines geschlossenen Rings aus Kupfer vorhanden. Die Metallstruktur 6 kann Teil der Schicht 4 aus Kupfer gewesen und aus dieser durch Wegät- zen nicht benötigter Bereiche erzeugt worden sein.The circuit structure 7, 9, 10, 11 furthermore has an insulation layer 10 in the form of a film laminated onto the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material. A metal structure 6 in the form of a closed ring made of copper is present at the edges and transitions to connections below the insulation layer 10. The metal structure 6 may have been part of the layer 4 made of copper and may have been produced from this by etching away areas that are not required.
Genau über der Metallstruktur 6 ist die Isolationsschicht 10 durch Lasern geöffnet . Nach dem Öffnen erfolgt ein weiterer Metallisierungsprozess, der die Isolationsschicht 10 mit ei- ner gasdichten Metallschicht 8 bedeckt, die außerdem einen gasdichten Abschluss zu der Metallstruktur 6 sicherstellt. Somit wird die Schaltungsstruktur mit dem Bauelement 9, der Schicht 7 aus elektrisch isolierendem Material und der Schicht 11 aus elektrisch leitendem Material auf dem Substrat 3 hermetisch abgedichtet. Wie in Figur 2 dargestellt, ist im Bereich von Öffnungen für Lastanschlüsse 5 bzw. Signalkontakte die Schicht 7 aus elektrisch isolierendem Material derart geöffnet, dass ein ausreichender Isolationsabstand zwischen den durch die Schicht 4 aus elektrisch leitendem Material gebildeten Anschluss und der Metallstruktur 6 sichergestellt ist. The insulation layer 10 is opened by lasering exactly above the metal structure 6. After opening, a further metallization process takes place, which covers the insulation layer 10 with a gas-tight metal layer 8, which also ensures a gas-tight seal to the metal structure 6. Thus, the circuit structure with the component 9, the layer 7 made of electrically insulating material and the layer 11 made of electrically conductive material on the substrate 3 is hermetically sealed. As shown in FIG. 2, in the area of openings for load connections 5 or signal contacts, layer 7 made of electrically insulating material is opened in such a way that a sufficient insulation distance between the connection formed by layer 4 made of electrically conductive material and metal structure 6 is ensured.

Claims

Patentansprüche claims
1. Verfahren zum Herstellen eines Gehäuses für eine auf einem Substrat (3) angeordnete Schaltungsstruktur (7, 9, 10, 11), bei dem auf die Schaltungsstruktur (7, 9, 10, 11) eine Metallschicht (8) aufgebracht wird, die zusammen mit dem Substrat (3) das Gehäuse für die Schaltungsstruktur (7, 9, 10, 11) bildet.1. A method for producing a housing for a circuit structure (7, 9, 10, 11) arranged on a substrate (3), in which a metal layer (8) is applied to the circuit structure (7, 9, 10, 11) together with the substrate (3) forms the housing for the circuit structure (7, 9, 10, 11).
2. Verfahren nach Anspruch 1, bei dem das Substrat (2, 3, 4) eine Metallstruktur (6) aufweist, die die Schaltungsstruktur (7, 9, 10, 11) auf den Substrat (3) umgibt und an der die Metallschicht 8) angeordnet wird.2. The method according to claim 1, wherein the substrate (2, 3, 4) has a metal structure (6) which surrounds the circuit structure (7, 9, 10, 11) on the substrate (3) and on which the metal layer 8 ) is arranged.
3. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die Schaltungsstruktur (7, 9, 10, 11) eine Isolationsschicht (10) aufweist, auf die die Metallschicht (8) aufgebracht wird.3. The method according to any one of the preceding claims, wherein the circuit structure (7, 9, 10, 11) has an insulation layer (10) to which the metal layer (8) is applied.
4. Verfahren nach den Ansprüchen 2 und 3, bei dem die Isolationsschicht (10) die Metallstruktur (6) bedeckt und die Isolationsschicht (10) vor Aufbringen der Metallschicht (8) an der Metallstruktur (6) geöffnet wird.4. The method according to claims 2 and 3, wherein the insulation layer (10) covers the metal structure (6) and the insulation layer (10) before application of the metal layer (8) to the metal structure (6) is opened.
5. Verfahren nach einem der Ansprüche 3 oder 4, bei dem die Isolationsschicht (10) durch eine Folie gebildet wird.5. The method according to any one of claims 3 or 4, wherein the insulation layer (10) is formed by a film.
6. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die Metallschicht durch Sputtern, außenstromlos und/oder galvanisch aufgebracht und/oder verstärkt wird. 6. The method according to any one of the preceding claims, in which the metal layer is applied and / or reinforced by sputtering, without external current and / or galvanically.
7. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die Schaltungsstruktur (7, 9, 10, 11) mit einem auf dem Substrat (3) angeordneten Bauelement (9) mit einer elektrischen Kontaktfläche hergestellt wird, indem - eine Schicht (7) aus elektrisch isolierendem Material auf dem Substrat (3) und dem Bauelement (9) aufgebracht wird,7. The method according to any one of the preceding claims, wherein the circuit structure (7, 9, 10, 11) with a component (9) arranged on the substrate (3) with an electrical contact surface is produced by - a layer (7) electrically insulating material is applied to the substrate (3) and the component (9),
- die elektrische Kontaktfläche des Bauelements zumindest teilweise beim Aufbringen der Schicht (7) aus elektrisch isolierendem Material frei bleibt und/oder nach dem Auf- bringen der Schicht (7) aus elektrisch isolierendem Material freigelegt wird,the electrical contact surface of the component remains at least partially free when the layer (7) made of electrically insulating material is applied and / or is exposed after the layer (7) made of electrically insulating material is applied,
- eine Schicht (11) aus elektrisch leitendem Material auf der Schicht (7) aus elektrisch isolierendem Material und der elektrischen Kontaktfläche des Bauelements aufgebracht wird.- A layer (11) made of electrically conductive material is applied to the layer (7) made of electrically insulating material and the electrical contact surface of the component.
8. Verfahren nach Anspruch 7, bei dem das Substrat (3) und das Bauelement (9) eine Oberflächenkontur bilden und die Schicht (7) aus elektrisch isolie- rendem Material in ihrer Gesamtheit der Oberflächenkontur folgt.8. The method according to claim 7, wherein the substrate (3) and the component (9) form a surface contour and the layer (7) made of electrically insulating material follows the surface contour in its entirety.
9. Verfahren nach einem der Ansprüche 7 oder 8, bei dem die Dicke der Schicht (7) aus elektrisch isolierendem Material über dem Substrat (3) in ihrem geradlinig verlaufenden Bereich um weniger als 50 % von der Dicke der Schicht (7) aus elektrisch isolierendem Material über dem Bauelement (9) in ihren geradlinig verlaufenden Bereich abweicht, insbesondere um weniger als 20 %.9. The method according to any one of claims 7 or 8, wherein the thickness of the layer (7) of electrically insulating material over the substrate (3) in its rectilinear region by less than 50% of the thickness of the layer (7) of electrical insulating material deviates over the component (9) in its rectilinear area, in particular by less than 20%.
10. Verfahren nach einem der Ansprüche 7 bis 9, bei dem das Substrat (3) eine elektrische Kontaktfläche aufweist, die e- lektrische Kontaktfläche des Substrats zumindest teilweise beim Aufbringen der Schicht (7) aus elektrisch isolierendem Material frei bleibt und/oder nach dem Aufbringen der Schicht (7) aus elektrisch isolierendem Material freigelegt wird und die Schicht (11) aus elektrisch leitendem Material auch auf der elektrischen Kontaktfläche des Substrats aufgebracht wird.10. The method according to any one of claims 7 to 9, wherein the substrate (3) has an electrical contact surface, the electrical contact surface of the substrate remains at least partially free when applying the layer (7) made of electrically insulating material and / or after Application of the layer (7) made of electrically insulating material is exposed and the layer (11) made of electrically conductive material the electrical contact surface of the substrate is applied.
11. Verfahren nach einem der Ansprüche 7 bis 10, bei dem das Bauelement (9) ein Leistungselektronikbauelement ist, insbesondere bei einem Leistungshalbleiter.11. The method according to any one of claims 7 to 10, in which the component (9) is a power electronics component, in particular in the case of a power semiconductor.
12. Verfahren nach einem der Ansprüche 7 bis 11, bei dem das Bauelement (9) in Richtung der Flächennormalen des Substrats (3) mindestens 70 μm dick ist, insbesondere mindestens 100 μm.12. The method according to any one of claims 7 to 11, wherein the component (9) in the direction of the surface normal of the substrate (3) is at least 70 microns thick, in particular at least 100 microns.
13. Vorrichtung mit einem Gehäuse (2, 3, 4, 8) für eine auf einen Substrat (3) angeordnete Schaltungsstruktur (7, 9, 10, 11), dadurch gekennzeichnet, dass auf die Schaltungsstruktur (7, 9, 10, 11) eine Metallschicht (8) aufgebracht ist, die zusammen mit dem Substrat (3) das Gehäuse (2, 3, 4, 8) für die Schaltungsstruktur (7, 9, 10, 11) bildet. 13. Device with a housing (2, 3, 4, 8) for a circuit structure (7, 9, 10, 11) arranged on a substrate (3), characterized in that on the circuit structure (7, 9, 10, 11 ) a metal layer (8) is applied, which together with the substrate (3) forms the housing (2, 3, 4, 8) for the circuit structure (7, 9, 10, 11).
PCT/EP2005/051584 2004-04-19 2005-04-11 Housing formed by a metallic layer WO2005101501A1 (en)

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DE102004019444 2004-04-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008092635A1 (en) * 2007-02-02 2008-08-07 Dsm Ip Assets B.V. Heat transport assembly

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359496A (en) * 1989-12-21 1994-10-25 General Electric Company Hermetic high density interconnected electronic system
US6492194B1 (en) * 1999-10-15 2002-12-10 Thomson-Csf Method for the packaging of electronic components
WO2003030247A2 (en) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359496A (en) * 1989-12-21 1994-10-25 General Electric Company Hermetic high density interconnected electronic system
US6492194B1 (en) * 1999-10-15 2002-12-10 Thomson-Csf Method for the packaging of electronic components
WO2003030247A2 (en) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008092635A1 (en) * 2007-02-02 2008-08-07 Dsm Ip Assets B.V. Heat transport assembly
US8189335B2 (en) 2007-02-02 2012-05-29 Dsm Ip Assets B.V. Heat transport assembly

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