WO2005004378A1

WO2005004378A1 - An intelligent universal calibration logic in embedded high speed transceiver (serdes) applications

Info

Publication number: WO2005004378A1
Application number: PCT/US2004/009425
Authority: WO
Inventors: Taylor Fengcheng Lin; Mao Xu
Original assignee: Qq Technology, Inc.
Priority date: 2003-06-22
Filing date: 2004-03-25
Publication date: 2005-01-13

Abstract

The present invention discloses a bundled transceiver link recovery process and algorithm and calibration control logic that can be universally implemented in any different types of embedded chipset designs and application for high-speed data communication systems. The calibration logic is capable of performing the calibrations during different stages of system operations. Specifically, the calibration logic of this invention is provided to satisfy the power-on-self calibration (105) requirements. The calibration logic is further provided to perform bundled SERDES (150) alignments, to correct the +/-100ppm frequency difference and to start the calibration process automatically upon detection an error (140). The calibration operations can be universally implemented in different embedded chipset configuration suitable for different data rates and different switch fabric-SERDES arrangements to assure reliable and accurate data transmissions are achieved.

Description

AN INTELLIGENT UNIVERSAL CALIBRATION LOGIC IN EMBEDDED HIGH SPEED TRANSCEIVER (SERDES) APPLICATIONS

This application claims priority to a pending U.S. Provisional Patent application entitled "AN INTELLIGENT UNIVERSAL CALIBRATION LOGIC IN EMBEDDED HIGH SPEED TRANSCEIVER (SERDES) APPLICATIONS", filed June 21, 2003 by Lin et al and accorded a Serial No. 60/480,188, the benefit of its filing date being hereby claimed under Title 35 of the United States Code.

BACKGROUND OF THE INVENTION

1. Field of the Invention This invention relates generally to communication networks. More particularly, this invention is related to embedded transceivers used in a switch fabric chip or network processor chipset that includes intelligent universal calibration logic.

2. Description of the Prior Art

Conventional system configurations for a high-speed transceiver (SERDER) are still faced with several technical limitations. One of the difficulties is the calibration for data transmitted over several bundled transceivers connected to a common port in a switching fabric. As the embedded transceivers are used in switch-fabric chip or network processor chipset, the system design complexity is significantly reduced. However, in order to create higher data bandwidth, several transceivers have to be bundled together to form a single logic port, for example, in order to achieve a 12.5 Gbps data rate to satisfy the OC-192 port requirement, four transceivers each with a data rate of 3.125 Gbps have to be used to provide a data rate 10 Gbps after 20% over head in 8B/10B Decoder /Encoder. Fig. 1 shows a switching fabric chipset, e.g., QQ80802, that includes switching card with 16-SERDES pairs interfaced with each Queue Manage Chip on the line-card. As shown in Fig. 1, two SERDERS are bundled to a logic port for providing a data rate of 5 Gbps or 6.25 Gbps applications wherein each transceiver has 2.5 Gbps or 3.125 Gbps bandwidth. Because of the configuration and operation characteristics of the transceivers, the clock signals recovered in the receiver side in each SERDES has different clock phase than the clock phase recovered in other SERDES. Therefore a link alignment is necessary between the bundled SERDERS to align the clock phases between the linked SERDERS such that the bundled data after deserialization of SERDERS can be read-out using local clock. A calibration process is therefore required to operate between the two connected bundled transceivers to construct a logic port in each direction of the switch fabric chipset application as that shown in Fig. 1. The calibration logic is designed to achieve such alignment process among multi-channel SERDES. Furthermore, there is a frequency difference between a Queue manager chip on the line card and the switching fabric on the switch card. The calibration logic is also required to compensate the frequency difference between Queue Manager chip on the line card and Switch Fabric chip on the switch card. In practical implementation, a +/- 100 ppm frequency difference is allowed between those two cards, the calibration logic is required to monitor the frequency difference in order to correct the frequency differences. Furthermore, in a Switch Fabric chip shown in Fig. 1, the data rate on each SERDES is 2.5Gbps, which gives 5 Gbps total for 2 bundled channels. Since the clock phase is different and data on each SERDES will be skewed. The calibration logic must also realign them to make sure all the data on two channels arrive at the same clock phase. In case there is an error during data transmission or receiving on either side, this transceiver pair has to be re-calibrated in order to guarantee next received or transmitted data are not lost. Therefore, as a result of implementing the bundled transceiver configuration because of the requirement of high data rate transmissions much more complicate functions are now required for a calibration logic.

In the meantime, the demand for a universal and intelligent calibration logic module is ever increased because of the rapid increase of high speed data transmissions, especially after the widespread use of the Internet as a worldwide communication network for transmitting data and multimedia data. Particularly, in data communication or switch fabric applications, a high-speed transceiver has been a core link technology to carry out the whole system architecture. In order to provide a reliable communication system, it is imperative to avoid a link failure and also to recovery quickly in case of a broken link caused by an error. The link error could happen for any kind transceiver because of the operating condition variations, such as, unpredictable temperature, power system, radiation and human mistakes, etc. To assure the reliable and accurate data transmission, it is necessary to build a recovery protocol in the design that insures the data traffic from both sides transferred correctly. However, as described above, the bundle transceiver configuration significantly increase the complexity and functions that must be carried out by the calibration logic. Conventional system configurations and communication data processors are not able to provide effective solutions to resolve these technical difficulties.

For the above reasons, there are ever increasing demands for an improved system configuration and method of a calibration logic that is operable with bundled transceiver systems to assure highly reliable and accurate data transmissions can be achieved such that the above- mentioned difficulties and limitations may be resolved. SUMMARY OF THE PRESENT INVENTION

It is therefore the object of the present invention to advance the art by providing a new and improved bundled transceiver link recovery process and algorithm and calibration control logic that can be universally implemented in any different types of embedded chipset designs and application for high speed data communication systems.

A major object of the present invention is to provide a calibration logic that is capable of performing the calibrations during different stages of system operations. Specifically, the calibration logic of this invention is provided to satisfy the power-on self-calibration requirements. The calibration logic is further provided to perform bundled SERDES alignments, to correct the +/- lOOppm frequency difference and to start the calibration process automatically upon detection an error. It is further an object that the calibration operations as disclosed in this invention can be universally implemented in different embedded chipset configuration suitable for different data rates and different switch fabric-SERDES arrangements to assure reliable and accurate data transmissions are achieved.

Briefly, the present invention discloses in a preferred embodiment at least two transceivers configured as bundled transceivers to a common communication port wherein each of these bundled transceivers includes a calibration logic for calibrating data transmissions during a power startup and a normal operation condition. In a preferred embodiment, the calibration logic further sends out a training pattern to carry out the calibration. In a preferred embodiment, the calibration logic further carries out a link alignment between the bundled transceivers, In another preferred embodiment, the calibration logic further compensates a frequency difference between the transceivers and a switch fabric connected to the bundled transceivers via the common communication port.

In a preferred embodiment, this invention further discloses a method for configured at least two bundled transceivers connected to a common communication port. The method includes a step of calibration data transmissions for the bundled transceivers during a power startup and a normal operation. In a preferred embodiment, the method further includes a step of sending out a training pattern to carry out the calibration. In another preferred embodiment, the method further includes a step of performing a link alignment between the bundled transceivers. In another preferred embodiment, the method further includes a step of compensating a frequency difference between the transceivers and a switch fabric connected to the bundled transceivers via the common communication port. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a diagram for illustrating the embedded bundled highspeed transceivers connected to a switch fabric.

Fig.2 shows the data exchange between two bundled transceivers and the operation of the calibration logic implemented in this invention.

Fig. 3 is a functional block diagram of a transmitter implemented with the calibration logic of this invention.

Fig. 4 is a functional block diagram of a receiver implemented with the calibration logic of this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to Fig. 2 for a functional block diagram of two bundled transceivers, i.e., transceiver A and transceiver B, each having a transmitter port TX and a receiver port RX. Each of these bundled transceivers is implemented with a calibration-logic of this invention.

Since the clock phase between these two transceivers are different while the data on each transceiver will be skewed. The calibration logic of this invention as shown is implemented to realign the data to make sure all the data on two channels arrive at the same clock phase. When there is an error during data transmission or receiving on either side, the calibration logic on each transceiver starts the calibration function to recalibrate the clocks of the data in order guarantee the next received or transmitted data would not be lost. During the system initialization, such as power on or hardware- reset process, the calibration logic modules in the transceiver A and Transceiver B automatically start the calibration process. The calibration modules of this invention make use of the phase lock data generated by the internal Phase Lock Loop (PLL). Either one of the calibration logic modules of transceivers A or B can start calibrating process when its own PLL has been locked and a training sequence is sent to opposite side, such that transceiver A will send training pattern to transceiver B, or vice versa. Then the two channels can be aligned and frequency difference can be compensated.

The calibration logic of this invention initiates the power-on calibration by a condition check to determine whether a local phase lock loop (PLL) has been locked. After a determination that this condition is satisfied, the calibration logic further checks whether there is a stable clock in operation. When the stable clock is in operation, then the calibration logic issues calibration enable signal to start calibration. In the normal operation, the calibration enable signal is issued by detecting the link error, then calibration process can start based on the communication protocol.

During the normal operation, calibration may happen when either transceiver A or B finds the data error by checking link protocol, such as ECC,CRC, 8B/10B, disparity and Parity error etc., and requires it to be calibrated. Either of these transceivers can initiate a calibration processes by sending out a signal according to a specific calibration link protocol. As shown in Fig. 2, options are also provided for a force calibration through an external command as that required by a system condition or a system user's discretion.

In order to further enhance the calibration operations, a training pattern is generated during calibration process and sent out in opposite direction from the calibration logic. In a preferred embodiment of this invention, there are four consecutive "K28.5 D21.5 K28.5 D21.5" data sequence on each link. The reasons for using these special training patterns are:

• This pattern includes a bit stream representing a COMMA character ("1111100") for byte alignment at the receiver side. Bit alignment is necessary since the data bit order is often distorted in a process of clock recovery in the high-speed transceivers.

• This pattern guarantees an alternative running disparity at receiver side. Since K28.5 has two polarity disparities and D21.5 is neutral disparity, therefore "K28.5 D21.5 K28.5 D21.5" will have a unique positive COMMA ("1111100") pattern, which can be detected by COMMA detection logic. This prevents a detection of COMMA bit- streams of both polarities thus simplifies the logic design.

• Sending four consecutive those patterns increase the probability of finding the training sequence.

• This pattern is useful for as a head reference when received and detected by a linked transceiver. A transceiver initiates an alignment process upon receiving and detecting this head reference.

• This pattern is useful in a process of compensating the frequency difference by either delete a "K28.5 D21.5" or insert a "K28.5 D21.5" in elastic buffer operation

Figure 3 shows detailed transmitter design block diagram. During power-up or force calibration is enabled via an enable signal 105, the training pattern is enabled and send out through a MUX select 110. The 8- bit pattern will outputted from a first-in-first-out buffer 120 to pass through an 8B/10B encoder 130, a de-skew FIFO 140 and an analog module (not shown) to be serialized to the high-speed port 150. Figure 4 shows the block diagram at receiver side. The high-speed data 210 is received and de-serialized by a SERDES 220 and is transferred into 10-bit parallel data 225. The data goes to "COMMA DET" module 230 for byte alignment by detecting positive COMMA character. Then the data are evaluated to see if there is coding error 235 or running disparity error 240. If there is no error found after 8B/10B decoder 250, the data will be shipped through a first-in-first-out (FIFO) 255 into Elastic Buffer 260 to carry out an alignment. Since the training pattern starts with K28.5, the 8B/10B will detects this special character that would not be in the normal 8-bit data table and the information is applied on each channel to align the two channel data. The alignment implementation is completed in Elastic

Buffer. When a K28.5 D21.5 K28.5 D21.5 sequence has been detected on each link, the Elastic Buffer pointer values are compared and to determine the difference between those two links. Then, the difference is applied to adjust the read pointer to read out the head in two links at the same time by the same clock.

The frequency compensation logic is also implemented for handling the situation that the output clock in the receive path is not chosen to be the recovered clock of that channel. The frequency variation between the two clocks may cause the Elastic Buffer overflow or underflow if no compensation circuit is performed. The concept of designed logic is explained in the following. ^■

Refer to the Figure 4. If read clock speed (CLK) is faster than write clock (RBC) speed in Elastic Buffer, eventually, the FIFO will be empty and FIFO status will be wrong. Before this status happens, the difference of the read pointer and the write pointer is detected. Once the difference is greater than a threshold, a special character, such as " K28.5 D21.5" is inserted after detecting "K28.5 D21.5". By doing this, FIFO will never have underflow status.

When FIFO read speed (CLK) is slower than FIFO write speed (RBC), a FIFO full or FIFO overflow will happen eventually. To avoid this, the difference between read pointer and write pointer is compared. When its difference is greater than a threshold, the logic will delete a head character "K28.5 D21.5" after detecting it. Thus, FIFO will never have overflow status and frequency compensation has completed.

A gray code has been used in comparing the difference between read pointer and write pointer to avoid multi-clock domain uncertain issue. It should be noted that this frequency compensation action (insert one word or skip one word) are only carried out on the certain order set (K28.5 D21.5), which was inserted on the transmit side for this purpose) to ensure that no useful characters are deleted or inserted.

Therefore, the calibration logic as implemented in the transceivers and described above is provided to satisfy the power-on self-calibration requirement. The calibration logic is further provided to manage the bundled SERDES alignment, to correct the +/- lOOppm frequency difference, and to start calibration process automatically through error check.

According to above descriptions and Figs. 1 to 4, the present invention discloses a network communication system that includes at least two bundled transceivers connected to a communication port wherein each of the bundled transceivers includes a calibration logic for aligning a clock-phase of data transmitted in the two bundled transceivers. In a preferred embodiment, the calibration logic starts a calibration during a power startup. In a preferred embodiment, the calibration logic further starts a calibration when a data transmission error occurs in one of the two bundled transceivers. In a preferred embodiment, the calibration logic starts a calibration when a phase lock data generated from a phase lock loop indicating a phase is locked. In a preferred embodiment, the calibration logic starts a calibration when a clock signal indicating a clock operation is stabilized. In a preferred embodiment, the calibration logic further sends out a training pattern for calibrating the data. In a preferred embodiment, the calibration logic further compensates a frequency difference between the transceivers and a switch fabric connected to the bundled transceivers via the common communication port. In a preferred embodiment, the calibration logic further sends out a training pattern containing a set of bits representing a comma character for calibrating the data. In a preferred embodiment, the calibration logic further sends out a training pattern containing a set of bits representing two polarity disparities and a neutral disparity. In a preferred embodiment, the calibration logic further sends out a training pattern containing consecutive sets of at least two repeated bit patterns for increasing a probability of detecting the training pattern. In a preferred embodiment, the calibration logic further sends out a training pattern for calibrating the data wherein the training pattern containing a set of bits detectable as a head reference. In a preferred embodiment, the calibration logic further sends out a training pattern for calibrating the data wherein the training pattern containing a set of bits detectable for compensating a frequency. In a preferred embodiment, the calibration logic further sends out a training pattern for initiating a calibration process. In a preferred embodiment, the calibration logic further includes a training pattern detector for detecting if a training pattern is received for initiating a calibration process. In a preferred embodiment, the calibration logic further includes a calibration-enabling device for initiating a calibration by sending out a training pattern. In a preferred embodiment, the calibration logic further comprising a de-skewing buffer for aligning a clock-phase of data transmitted in the two bundled transceivers. In a preferred embodiment, the network communication system further includes a force calibration device for allowing an external command for initiating a calibration. In a preferred embodiment, the network communication system further includes a coding error detector for detecting a code error for initiating a calibration. In a preferred embodiment, the network communication system further includes a disparity error detector for detecting a disparity error for initiating a calibration. In a preferred embodiment, the network communication system further includes an elastic first in first out (FIFO) buffer for simultaneously transmitting a detected header between the two bundled transceivers for aligning the clock-phase.

This invention further discloses a method configuring a network communication system that includes a step of connecting at least two bundled transceivers to a communication port and employing a calibration logic in each of the bundled transceivers for aligning a clock- phase of data transmitted in the two bundled transceivers. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration during a power startup. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration when a data transmission error occurs in one of the two bundled transceivers. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration when a phase lock data generated from a phase lock loop indicating a phase is locked. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration when a clock signal indicating a clock operation is stabilized. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern for calibrating the data. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of compensating a frequency difference between the transceivers and a switch fabric connected to the bundled transceivers via the common communication port. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern containing a set of bits representing a comma character for calibrating the data. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern containing a set of bits representing two polarity disparities and a neutral disparity. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration sending out a training pattern containing consecutive sets of at least two repeated bit patterns for increasing a probability of detecting the training pattern. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern for calibrating the data wherein the training pattern containing a set of bits detectable as a head reference. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern for calibrating the data wherein the training pattern containing a set of bits detectable for compensating a frequency. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a calibration by sending out a training pattern for initiating a calibration process. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of starting a employing a training pattern detector for detecting if a training pattern is received for initiating a calibration process. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of employing a calibration-enabling device for initiating a calibration by sending out a training pattern. In a preferred embodiment, the step of aligning the clock-phase of data further includes a step of employing a deskewing buffer for aligning a clock-phase of data transmitted in the two bundled transceivers. In a preferred embodiment, the method further includes a step of initiating a force calibration device by receiving and processing an external force calibration command.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention. Those approaches and mechanisms in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. As a result, the invention is not limited to the specific examples and illustrations discussed above, but only the following claims and their equivalents.

Claims

CLAIMS We claim: 1. A network communication system comprising: at least two bundled transceivers connected to a communication port wherein each of said bundled transceivers includes a calibration logic for aligning a clock- phase of data transmitted in said two bundled transceivers. 2. The network communication system of claim 1 wherein: said calibration logic starting a calibration during a power startup. 3. The network communication system of claim 1 wherein: said calibration logic further starting a calibration when a data transmission error occurs in one of said two bundled transceivers.

The network communication system of claim 1 wherein: said calibration logic starting a calibration when a phase lock data generated from a phase lock loop indicating a phase is locked.

5. The network communication system of claim 1 wherein: said calibration logic starting a calibration when a clock signal indicating a clock operation is stabilized.

6. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern for calibrating said data.

7. The network communication system of claim 1 wherein: said calibration logic further compensates a frequency difference between said transceivers and a switch fabric connected to said bundled transceivers via said common communication port.

8. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern containing a set of bits representing a comma character for calibrating said data.

9. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern containing a set of bits representing two polarity disparities and a neutral disparity.

10. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern containing consecutive sets of at least two repeated bit patterns for increasing a probability of detecting said training pattern.

11. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern for calibrating said data wherein said training pattern containing a set of bits detectable as a head reference.

12. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern for calibrating said data wherein said training pattern containing a set of bits detectable for compensating a frequency.

13. The network communication system of claim 1 wherein: said calibration logic further sends out a training pattern for initiating a calibration process.

14. The network communication system of claim 1 wherein: said calibration logic further comprising a training pattern detector for detecting if a training pattern is received for initiating a calibration process.

15. The network communication system of claim 1 wherein: said calibration logic further comprising a calibration enabling device for initiating a calibration by sending out a training pattern. 16. The network communication system of claim 1 wherein: said calibration logic further comprising a de-skewing buffer for aligning a clock-phase of data transmitted in said two bundled transceivers

17. The network communication system of claim 1 further comprising: a force calibration device for allowing an external command for initiating a calibration.

18. The network communication system of claim 1 further comprising: a coding error detector for detecting a code error for initiating a calibration.

19. The network communication system of claim 1 further comprising: a disparity error detector for detecting a disparity error for initiating a calibration.

20. The network communication system of claim 1 further comprising: a elastic first in first out (FIFO) buffer for simultaneously transmitting a detected header between said two bundled transceivers for aligning said clock-phase.

21. A method configuring a network communication system comprising: connecting at least two bundled transceivers to a communication port and employing a calibration logic in each of said bundled transceivers for aligning a clock-phase of data transmitted in said two bundled transceivers.

22. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration during a power startup. 23. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration when a data transmission error occurs in one of said two bundled transceivers.

24. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration when a phase lock data generated from a phase lock loop indicating a phase is locked.

25. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration when a clock signal indicating a clock operation is stabilized.

26. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern for calibrating said data.

27. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of compensating a frequency difference between said transceivers and a switch fabric connected to said bundled transceivers via said common communication port.

28. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern containing a set of bits representing a comma character for calibrating said data.

29. The method of claim 1 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern containing a set of bits representing two polarity disparities and a neutral disparity.

30. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration sending out a training pattern containing consecutive sets of at least two repeated bit patterns for increasing a probability of detecting said training pattern.

31. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern for calibrating said data wherein said training pattern containing a set of bits detectable as a head reference.

32. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern for calibrating said data wherein said training pattern containing a set of bits detectable for compensating a frequency.

33. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a calibration by sending out a training pattern for initiating a calibration process.

34. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of starting a employing a training pattern detector for detecting if a training pattern is received for initiating a calibration process.

35. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of employing a calibration enabling device for initiating a calibration by sending out a training pattern.

36. The method of claim 21 wherein: said step of aligning said clock-phase of data further comprising a step of employing a de-skewing buffer for aligning a clock-phase of data transmitted in said two bundled transceivers

37. The method of claim 21 further comprising: initiating a force calibration device by receiving and processing an external force calibration command.