WO2004088889A1

WO2004088889A1 - Transparent multiplexing method and device

Info

Publication number: WO2004088889A1
Application number: PCT/JP2003/004146
Authority: WO
Inventors: Toshihiro Homma; Yoshikazu Terayama; Noriaki Mizuguchi; Kenichi Kaburagi
Original assignee: Fujitsu Limited
Priority date: 2003-03-31
Filing date: 2003-03-31
Publication date: 2004-10-14
Also published as: JP3875251B2; JPWO2004088889A1

Abstract

Frequency synchronization between opposed stations is achieved, and a signal including an OH on the client side can be transparent-transmitted. On the transmission side, frames (1, 2) inputted through channels are multiplexed (Step S1). Control information defining the clock frequencies of the frames (1, 2) is set in a frame byte (5a) in the overhead (5b) of the multiplexed frame (5) (Step 2). On the receiving side, the control information (6a) defining the clock frequencies of the frames (1, 2) is extracted from the frame byte (5a). Then, the multiplexed frame (5) is separated into the frames (1, 2). The frames (1, 2) with the corresponding clock frequencies are outputted to the corresponding channels.

Description

Transparent multiplexing method and apparatus

The present invention relates to a transparent multiplexing method and apparatus for realizing transparent multiplexing transmission, a transparent multiplexed signal separating method and a transparent multiplexing signal separation method.

More particularly, the present invention relates to a transparent multiplexing method and apparatus for performing transparent transmission including overhead, and a transparent multiplexed signal separation method and apparatus. Background art

One form of digital transmission system is a transmission system that transparently multiplexes and separates client signals. Here, the client signal refers to a low-speed signal to be multiplexed in Synchronous Optical NETwork (SONET) / Synchronous Digital Hierarchy (SDH). For example, when multiplexing four lines of a line with a speed of OC48 to form one line with a speed of OC192, the preceding OC48 signal is a client signal.

One conventional technique for enabling transparent transmission is to multiplex multiple client signals using digital wrapper (DW) technology and add artband information to the overhead of the wrapper. Digital wrapper technology is used for OTN (Optical Transport Network) included in Recommendation G.709, International Telecommunications Lnion-Telecommunication Standardization Sector (ITU). This is a frame format technology. However, this method requires a new control mechanism for multiplexing, which complicates the method. As a result, application to existing equipment is difficult.

Another method is to perform pseudo-transparent transmission by adding in-band information. That is, multiple client signals (the number of OC n X channels) are At the end, each SOH (Section Ovei'Head) passes a specific signal (E1, F1, D1-12, K1, K2, etc.) and redefines the SOH. As a result, apparently transparent transmission is realized. The reason for terminating once is that the client signal is asynchronous and has a frequency deviation, so it cannot pass through SOH that does not have stuff and pointer processing.

FIG. 12 shows a network configuration example of a conventional transmission system. In this example, transmission devices 91 1 to 914 on networks 941 to 944 (stations A, B, C, and D, respectively) are transmitted from transmission devices 921 to 924 on networks 951 to 954 (E, respectively). Station, F station, G station, H station).

In the example of FIG. 12, client signals (eg, OC48 # 1 to OC48 # 1 to 914) from a plurality of transmission devices 91 to 914 having oscillation clock sources independent of each other (eg, fl, f2, f3, f4) # 4) is once transmitted to the OC 192 speed line via the transmission device 931 (station X). The OC 192 speed line is connected to the transmission device 932 (station Y) and transmitted to other transmission devices 921 to 924 via the transmission device 932. In this case, the transmission devices 921 to 924 transmit client signals (for example, OC48 # 5 to # 8) on the networks 951 to 954 at a predetermined operation clock: fX. Note that the transmission devices 931 and 932 are provided with OH processing units 933 and 934, respectively, and S〇H is redefined.

As described above, as a technique for redefining the overhead and enabling transmission of a plurality of low-speed SDH signals using high-speed SDH signals, the OH pointer action byte (H3) is used as the overhead frequency. Some are used for absorption bits (see, for example, Patent Document 1).

Patent Document 1

JP 2000-269912 (Fig. 5)

By the way, the ideal transparent transmission is as shown in Fig. 12 from station A to station E, station B to station F, station C to station G, station D to station H, and station X to station Y: There are four optical fibers, and the signals of OC48 # 1, # 2, # 3, and # 4 are transmitted through as they are. In other words, station A-E, station B-F, station C-G, and station D-H are frequency synchronized between communicators including OH. In this case, the client thinks that it can communicate freely within the OC48 signal standard. One example is network management and communication between terminals using undefined bits of SOH.

However, in the conventional transmission method, the stations E to H are synchronized uniformly to fx, so that E1 (order wire) of the SOH, Dl—D3 (section data), etc. However, the bits prepared for the client (between sections) are passed through, but if undefined bits are used first, the SOH of OC48 will be lost due to termination and communication will not be possible. .

For example, in the technique described in Patent Document 1, the pointer action byte (1Ί3) used for the overhead frequency absorption bit collides with the section data and the communication channel. Therefore, the transparent transmission cannot be performed for all the multiplexed channels (see paragraph “038” of Patent Document 1).

As in this example, the conventional example is not completely transparent transmission from the viewpoint of the client. In other words, in order to realize transparent transmission, it is necessary to achieve frequency synchronization between the stations # 1 to # 2 and the opposite stations # 1 to # 2 in Fig. 12 with regard to overhead (S OH).

On the other hand, in recent years, with the development of new business such as line reselling, complete transparent transmission of client signals is strongly desired. For example, if transparent transmission including SOH is realized, it is possible to provide a special control signal on SOH and provide advanced data communication services. Disclosure of the invention

The present invention has been made in view of such a point, and provides a transparent multiplexing transmission apparatus that achieves frequency synchronization between opposing stations and is capable of transmitting a signal on the client side transparently including OH. With the goal.

In the present invention, in order to solve the above-mentioned problems, a transparent multiplexing method as shown in FIG. 1 is provided. In the transparent multiplexing method according to the present invention, the following processing is performed in order to multiplex a plurality of transmission signals transparently. First, A plurality of frames 1 and 2 input from a plurality of channels are multiplexed (step S 1), and a frame byte 5 a in an overhead 5 b of the multiplexed multiplexed frame 5 is added to each of the plurality of frames 1 and 2. Set the control information that defines the clock frequency (step S2).

According to such a transparent multiplexing method, a plurality of frames 1 and 2 are multiplexed, and the clock frequency of each frame to be multiplexed is defined in the frame pit 5a of the multiplexed multiplexed frame 5. Control information 6a is set. In order to solve the above problem, a transparent multiplexed signal separation method for separating a multiplexed frame 5 in which a plurality of transmission signals are transparently multiplexed into a plurality of frames 1 and 2 includes: Extract control information 6a that defines the clock frequency of each of multiple frames 1 and 2 from frame byte 5a in overhead 5b of 5 and separate multiplexed frame 5 into multiple frames 1 and 2. In addition, there is provided a transparent multiplexed signal separation method characterized in that a plurality of frames 1 and 2 are output to corresponding channels at clock frequencies corresponding to the respective channels.

According to such a transparent multiplexed signal separation method, a plurality of frames 1 and 2 superimposed on the multiplexed frame 5 are transmitted at the clock frequency defined in the control information 6a set in the frame byte 5a. Is output.

The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a network configuration example according to the embodiment of the present invention.

FIG. 3 is a diagram showing the structure of a frame byte. FIG. 3 (A) shows a state before securing a transparent byte, and FIG. 3 (B) shows a state after securing a transparent byte.

FIG. 4 is a diagram showing an example of the contents of a transparent byte to be multiplexed. FIG. 5 is a diagram illustrating an example of a block configuration of a multiplexing circuit. FIG. 6 is a diagram illustrating a block configuration example of the separation circuit.

FIG. 7 is a diagram illustrating an example of a frame configuration in a case where the operating speed difference of the channel to be multiplexed is indicated by a hot line.

FIG. 8 is a diagram illustrating an example of a frame configuration in a case where a difference in operation speed between channels to be multiplexed is absorbed by stuffing.

FIG. 9 is a block diagram showing a multiplexing circuit.

FIG. 10 is a block diagram showing a separation circuit.

FIG. 11 is a diagram illustrating an example of the contents of a transparent byte.

FIG. 12 shows a network configuration example of a conventional transmission system. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the outline of the invention applied to the embodiment will be described, and then the specific contents of the embodiment will be described.

FIG. 1 is a diagram illustrating the principle of the present invention. In the transparent multiplexing method according to the present invention, the following processing is performed in order to multiplex a plurality of transmission signals transparently.

First, a plurality of frames 1 and 2 input from a plurality of channels are multiplexed (step S 1). Frame 1 is composed of overhead lb, 1c, payload 1d, and so on. Overhead 1b contains frame byte 1a. Similarly, frame 2 is composed of overheads 2b and 2c, a payload 2d, and the like. The overhead 2b includes the frame byte 2a. Here, when multiplexing, frames 3 and 4 excluding the frame bytes l a and 2 a are multiplexed.

The multiplexed multiplexed frame 5 is composed of overheads 5b and 5c, a payload 5d, and the like. The overhead 5b includes the frame byte 5a. The data after multiplexing frames 3 and 4 is stored in payload 5d.

Also, the frame byte in the overhead 5b of the multiplexed multiplexed frame 5 5 In a, set control information that defines the clock frequencies f1, f2 of the plurality of frames 1 and 2 (step S2). For example, the frame synchronization signal 6b is left in a part of the frame byte 5a, and the control information 6a is set in the other part. For example, in SONETZSDH transmission, the frame synchronization signal 6 b is a frame synchronization signal 6 b which is a predetermined byte at the boundary between the A1 and A2 bytes of SOH (overheads 5 b and 5 c in FIG. 1). Area.

As a result, a multiplexed frame 5 having control information 6a in which the clock frequencies fl and f2 of the frames 1 and 2 to be multiplexed are defined in the frame pipe 5a is generated.

When such a multiplexed frame 5 is generated in the transmission device and passed to another transmission device, the multiplexed frame 5 is separated in the other transmission device. The method of transparent multiplexed signal separation is as follows.

First, control information 6a that defines the clock frequencies f1 and f2 of each of a plurality of frames 1 and 2 is extracted from the frame byte 5a in the overhead 5b of the multiplexed frame 5. Next, the multiplexed frame 5 is separated into a plurality of frames 1 and 2. Then, a plurality of frames 1 and 2 are output to the corresponding channels at the corresponding clock frequencies f1 and f2.

According to such a transparent multiplexed signal separation method, a multiplexed frame

A plurality of frames 1 and 2 superimposed on 5 are output at clock frequencies f 1 and f 2 defined in control information 6 a set in frame byte 5 a.

In this way, all information other than the frame bytes 1a and 2a of the frames 1 and 2 can be multiplexed and stored in the payload 5d of the multiplexed frame 5. That is, the overheads l b, l c, 2 b, and 2 c of frames 1 and 2 are also multiplexed and transmitted. As a result, transparent transmission including overhead is realized. The frame bytes l a and 2 a of frames 1 and 2 are

—Because of the predetermined bit pattern for system synchronization, the original state can be reproduced by adding predetermined contents at the time of separation, without multiplexing and transmitting.

Moreover, since the clock frequencies fl and f2 of the frames 1 and 2 are set to the frame byte 5a, the transmission device that receives the multiplexed frame 5 receives the frame The clock frequencies fl and f2 of the frames 1 and 2 can be recognized by referring to FIG. As a result, the demultiplexed frames 1 and 2 can be transmitted at the same clock frequencies f1 and f2 as before the multiplexing, and the frequency synchronization between the opposing stations becomes possible. In addition, since the frame synchronization signal 6b necessary for frame synchronization is left in the frame byte 5a of the multiplexed frame 5, the frame synchronization of the multiplexed frame 5 can be correctly performed on the receiving side.

Hereinafter, an embodiment in the case of realizing on transparent transmission and SONETZSDH transmission as shown in FIG. 1 will be specifically described. In other words, in SONET ZSDH transmission, when synchronizing a client signal having a frequency variation (signal transmitting a frame to be multiplexed) asynchronously and multiplexing it into a higher-order layer, the SOH Al, A 2 bytes However, as a result of interleaving, consecutive A 1 and A 2 are arranged. Focusing on this, we leave some Al and A2 and use the other part as additional information for frequency fluctuation.

In addition, a frame having each client signal as a payload is reconstructed. Further, a pointer indicating the position of the client signal or staff information is multiplexed in the multiplex frame 5. This achieves synchronization between the qualants of the opposing station and achieves transparent transmission.

FIG. 2 is a diagram showing a network configuration example according to the embodiment of the present invention. As shown in FIG. 2, two transmission devices 11 and 12 are connected via a high-speed (for example, OC192) transmission line 13 for transmitting a multiplexed frame. Here, the transmission device 11 is referred to as “X station”, and the transmission device 12 is referred to as “Y station”. The transmission device 11 is provided with a ΟΗ processing unit 14, and the ΟΗ processing unit 14 reconfigures ΟΗ. Similarly, the transmission device 12 is provided with a ΟΗ processing unit 15, which analyzes ΟΗ and reproduces 解析 of an original frame. The transmission devices 11 and 12 that perform multiplexing and demultiplexing do not perform (1) termination processing.

The transmission device 11 of the X station is connected to four transmission devices 2 :! to 24 having a speed of OC48. The transmission device 21 is “station”, the transmission device 22 is “station”, the transmission device 23 is “station C”, and the transmission device 24 is “station D”.

The transmission device 21 has an operating frequency (clock frequency) f 1 within the network 41. Is provided. The transmission device 22 is provided in the network 42 having the clock frequency f2. The transmission device 23 is provided in a network 43 having a clock frequency f3. The transmission device 24 is provided in a network 44 having a clock frequency f4.

Four transmission devices 31 to 34 having a speed of OC48 are connected to the transmission device 12 of the Y station. The transmission device 31 is referred to as “station E”, the transmission device 32 is referred to as “station F”, the transmission device 33 is referred to as “station G”, and the transmission device 34 is referred to as “station H”.

The transmission device 31 is provided in a network 51 having a clock frequency of ί1. The transmission device 32 is provided in a network 52 having a clock frequency f2. The transmission device 33 is provided in a network 53 having a clock frequency f3. The transmission device 34 is provided in a network 54 having a clock frequency f4. Here, regarding SOH, between the transmission device 21 of the A station and the transmission device 31 of the E station (synchronization of f 1), and between the transmission device 22 of the B station and the transmission device 32 of the F station ( ί2), between station C's transmitter 23 and station G's transmitter 33 (synchronous to f 3), between station E's transmitter 24 and station H's transmitter 34 (Synchronize with f4) and perform transparent transmission including SOH. Of course, the payload is transmitted correctly.

In order to realize transparent transmission including overhead and payload, it is necessary to absorb the frequency difference between a plurality of asynchronous low-speed SDH / SONET signals. In other words, it absorbs the frequency difference between asynchronous low-speed signals and synchronizes them with high-speed signals. At this time, the payload signal can be processed using a technique such as Boyne et al. However, the overhead signal does not have additional pits for frequency absorption for multiplexing between sections and lines.

Thus, in the present embodiment, bits 81 and A2 in 3011 are used as bits for frequency absorption. The A l and A 2 bits are called frame bytes and are signals used for frame synchronization. When a plurality of client signals are multiplexed, the A1 pit and the A2 bit have the same code consecutively. Moreover, if the boundary between the A1 bit and the A2 bit can be detected, frame synchronization is possible. Therefore, control for frequency absorption is performed in the area other than the boundary between A1 bit and A2 bit. Setting the information does not adversely affect frame synchronization. Hereinafter, an area for storing control information for frequency absorption is referred to as a transparent byte.

The configuration of the frame byte will be described below by comparing before and after the transparent byte is secured.

FIG. 3 is a diagram showing the structure of a frame byte. Fig. 3 (A) shows the state before securing the transparent byte, and Fig. 3 (B) shows the state after securing the transparent byte. The example in FIG. 3 shows a frame configuration of Al and A2 bytes when transmission is performed according to the SDHZSONET transmission method.

As shown in FIG. 3A, in the frame byte 71 before securing the transparent byte, the frame synchronization information is set in all N bytes provided in A1. Similarly, frame synchronization information is set in all N bytes provided in A2. N indicates the level of the transmission speed in SONET. For example, in the case of the speed of OC48, N = 48, and A1 and A2 each have a 48-byte configuration.

Here, when the client signal is multiplexed, a transparent byte is secured, and the boundary between the A1 byte and the A2 byte is left in the frame byte 72 as shown in FIG. 3 (B). The control information for frequency absorption is set in other parts. In this embodiment, the N-1 byte and the Nth byte of A1 and the 1st and 2nd bytes of A2 are left as a frame synchronization pattern, and the other bytes are regarded as surplus bytes. Is multiplexed.

FIG. 4 is a diagram showing an example of the contents of a transparent byte to be multiplexed. The total number of bytes for transparent bytes is 2N-4. In other words, the total number of bytes for transparent bytes is the capacity obtained by subtracting the four bytes that leave the frame synchronization pattern from the entire frame bytes.

The control information 73 includes a maximum speed CH management byte part 73a and a phase difference indication byte 73b. The maximum speed CH management byte part 73a is an area for setting information indicating a channel with the highest frequency among the multiplexed lines OCn (STM-m). The number of bytes used by the maximum speed CH management byte part 73a is, for example, 1 byte. The phase difference display byte 73b is an area for setting information (difference in phase) between each channel and the maximum speed channel frequency. The content of the phase difference display byte 73b differs depending on whether the pointer method or the stuff method is used. In the case of the pointer method, position information of data of each channel is set in the phase difference display byte 73b. The number of bytes used for the phase difference display byte 73b in the pointer method is, for example, 9 × the number of low-order group frames to be multiplexed. In the case of the stuffing method, the presence / absence of a buffer bit and information on the number of stuff bits are set in the phase difference display byte 73b. The number of bytes used for the phase difference display byte 73 b in the case of the stuff method is 1 × the number of low-order group frames to be multiplexed.

Next, a circuit configuration for multiplexing signals will be described.

FIG. 5 is a diagram illustrating an example of a block configuration of a multiplexing circuit. This example shows a case where OC48 is input for four channels (OC48 # l to # 4). The multiplexing circuit consists of opto-electric converters 81 to 84, maximum speed CH detection selector 85, duplexer (PLL unit) 86, inter-channel (CH) phase detection unit 87, and frame byte information addition unit 88 .

The photoelectric converters 81 to 84 are provided in correspondence with the input signals of four channels. The opto-electric converters 81 to 84 convert the input light signals into electric signals. The electric signals converted by the photoelectric converters 81 to 84 are output to the maximum speed channel (CH) detection selector 85 and the inter-CH phase detection unit 87.

The highest speed CH detection selector 85 receives the clock signals from the photoelectric converters 81 to 84 and determines the clock signal with the highest frequency. Then, the highest speed CH detection selector 85 selects the channel (CH) number of the clock signal having the highest frequency, and outputs the CH number to the frame byte information adding section 88. The clock signal having the highest frequency is output to the multiplier (PLL unit) 86. The PLL unit 86 generates a high-order clock signal synchronized with the input clock, and outputs it to the frame byte information adding unit 88.

The inter-channel phase detector 87 generates frequency difference information of the clock frequency between the channels. As a result, frequency difference information between the clock frequency determined by the maximum speed CH detection selector 85 and another channel is generated for each channel. Phase detection between channels The output unit 87 outputs the generated frequency difference information to the frame byte information adding unit 88. Further, the inter-CH phase detection section 87 deletes (DROP) the frame byte from the signal of each channel and outputs the signal of each channel to the frame byte information adding section 88.

The frame byte information adding unit 88 is a FIF0 (Fast In Fast Out) buffer, and temporarily stores data transmitted by a signal of each channel. Then, the frame byte information adding unit 88 synchronizes the signal of each channel with the clock supplied from the PLL unit 86. Further, the frame byte information adding section 88 starts with the frame synchronization consisting of the channel number and the frame pattern detected by the maximum speed CH detection selector 85, and starts with the phase information of each channel measured by the inter-CH phase detecting section 87 ( It multiplexes the signals of the other channels that have absorbed the frequency difference based on the frequency difference information) and outputs it. Regarding the method of absorbing the frequency difference at the time of multiplexing, the phase information may be indicated by a pointer or stuffing may be performed. These methods can be selected according to the number of multiplexes.

The following operation is performed by the multiplexing circuit having such a configuration.

First, the signals of each channel are converted into electric signals by photoelectric converters 81 to 84. Based on the signal of each channel, the channel with the highest frequency is selected by the highest speed CH detection selector 85, and the channel number of that channel is transmitted to the frame byte information adding unit 88. For example, it is assumed that the frequency of the channel with the channel number “CH # 2” is the highest. At this time, a high-order mixed signal synchronized with the signal of the channel with the highest frequency is generated by the PLL section 86 and supplied to the frame byte information adding section 88.

Further, based on the signals converted by the opto-electrical converters 81 to 84 into electric signals, the inter-CH phase detecting section 87 detects the frequency difference between the respective channels and supplies the detected difference to the frame byte information adding section 88. For example, if the fastest channel is CH # 2, the frequency difference between that channel and the other channels (CH # 1, CH # 3, CH # 4) is detected. Further, the inter-CH phase detecting section 87 removes the frame byte from the input signal of each channel and sends the frame byte to the frame byte information adding section 88.

Then, in the frame byte information adding section 88, the signals of each channel are multiplexed. Is done. At this time, control information for absorbing the frequency difference is added to the multiplexed multiplexed frame bytes. The contents of the frame bytes after multiplexing are as shown in Fig. 3 (B).

Next, the configuration of the separation unit will be described.

FIG. 6 is a diagram illustrating a block configuration example of the separation circuit. This example shows a case where a multiplexed signal is separated from a signal having a speed of 〇C 192 into four channels by 〇C 48 (OC48 # 1 to # 4). The separation circuit consists of a CH phase detection section 91, a CH division ratio specification section 92,? It comprises a 1 ^ 1 ^ section 93, a phase alignment section 94 between channels, and electro-optical converters 95-98.

The inter-CH phase detecting section 91 receives an input of the multiplexed signal and detects a frame pattern from the input signal. Then, the inter-CH phase detecting section 91 extracts frequency difference information of each channel multiplexed on the unique header of the frame. The extracted frequency difference information is passed to the CH dividing ratio designating section 92. In addition, the inter-CH phase detection section 91 removes (DROPs) free bits from the input signal and outputs the result to the PLL section 93 and the inter-CH phase alignment section 94.

The CH dividing ratio designating section 92 generates a divided signal for reproducing each channel clock from the frequency difference information. The CH dividing ratio designating section 92 outputs the generated divided signal to the PLL section 93.

The PLL units 93 are provided for the number of channels. In the example of FIG. 6, four PLLs for four channels are provided. this? The section 93 reproduces a clock signal for each channel having a frequency designated by the divided signal generated by the CH dividing ratio designation section 92, based on the signal from the inter-CH phase detection section 91. ? The 1 ^ unit 93 outputs the generated clock signal to the inter-CH phase alignment unit 94.

The inter-CH phase alignment unit 94 reads out each channel signal from the multiplexed signal in the multiplexed order in accordance with the clock signal supplied from the PLL unit. Then, the inter-CH phase alignment unit 94 adds a frame byte (Al, A2) to each channel signal, and thereafter outputs each channel signal to the electro-optical converters 95 to 98.

The electro-optical converters 95 to 98 are provided in association with each channel. Electric light The converters 95 to 98 convert the input electric signal into an optical signal and output it. The following processing is performed by the separation unit configured as described above.

When the OC 192 speed signal is input to the inter-CH phase detection unit 91, the inter-CH phase detection unit 91 detects a frame pattern, detects frequency difference information of each channel, and removes frame bytes. .

The frequency difference information is sent to the CH dividing ratio designating section 92. Then, a frequency-divided signal specifying the frequency is sent from the CH frequency dividing ratio specifying unit 92 to the PLL unit 93. The PLL unit 93 generates a clock signal for each channel according to the frequency-divided signal, and supplies the clock signal to the inter-CH phase alignment unit 94.

In the inter-CH phase alignment unit 94, the channel signal is read out according to the clock signal for each channel, and after adding the frame byte (Al, A2), it is sent to the electro-optical converters 95 to 98. Then, the signals of each channel are converted into optical signals by the electro-optical converters 95 to 98, and output at an OC48 speed.

Absorbing the frequency fluctuation of SOH by the multiplexing and demultiplexing method as described above enables transparent transmission of SOH.

Next, as a method of indicating a frequency difference before multiplexing in a frame after multiplexing, there are a method using a point and a method using a staff. Hereinafter, the frame configuration when the operating speed difference (clock frequency difference) is indicated by each method will be described.

FIG. 7 is a diagram illustrating an example of a frame configuration when the operation speed difference of the multiplex target channel is indicated by a pointer. FIG. 7 shows an example in which the present invention is applied to a SONET (SDH) frame configuration. Although FIG. 7 shows the frame bytes separately from the overhead for easy understanding of the features of the embodiment of the present invention, the frame pipe is actually one of the constituent elements of the overhead. It is. Here, it is assumed that the OC 48 (channel numbers # 1 to # 4) for four channels have different clock frequencies. Channel number "CH # 1" OC48 clock frequency is f1, channel number "CH # 2" OC48 clock frequency is f2, and channel number "CH # 3" OC48 clock frequency is f3. The clock frequency of the OC48 with the number “CH # 4” is f4.

Frame 110 of the channel with channel number “CH # 1” is frame byte 1 11, overhead (OH) 112 and 113 other than frame byte 111, and payload 114. The frame 120 of the channel with the channel number “CH # 2” is composed of a frame pipe 121, overheads (OH) 122 and 123 other than the frame byte 121, and a payload 124. The frame 130 of the channel with the channel number “# 3” includes a frame byte 131, overheads (OH) 132 and 133 other than the frame byte 131, and a payload 134. The frame 140 of the channel with the channel number “# 4” includes a frame byte 141, overheads (OH) 142 and 143 other than the frame byte 141, and a payload 144.

When frames 110, 120, 130, and 140 of each channel are input, frame bytes 111, 121, 131, and 141 are extracted from each of frames 110, 120, 130, and 140, and a new frame byte 151 is generated. Is performed. Here, the frames 110a, 120a, 130a, 140a after the frame bytes 111, 121, 131, 141 are taken out are to be multiplexed. In the generated frame byte 151, pointer information indicating the head of the frame 110a, 120a, 130a, 140a to be multiplexed is set. The frame byte 151 also includes information for specifying a channel having the highest click frequency. Thereafter, the frames 110a, 120a, 130a, and 140a are multiplexed, and a new frame 150 is generated together with the frame bytes 151.

The frame 150 includes a frame byte 151, overhead heads 152 and 153, and a payload 154. Frames 110a, 120a, 130a and 140a excluding the frame bytes 111, 121, 131 and 141 of each channel of the OC48 are interleaved and multiplexed and treated as a payload 154 in the frame 150. Multiplexing is performed by, for example, a TDM (Time Division Multiplex) method.

FIG. 8 is a diagram illustrating an example of a frame configuration in a case where a difference in operation speed between channels to be multiplexed is absorbed by stuffing. FIG. 8 shows an example in which the present invention is applied to a SONET (SDH) frame configuration. FIG. 8 shows the operation of the present invention. Although the frame bytes are shown separately from the overhead in order to make the features of the embodiment easy to understand, the frame byte is actually one of the components of the overhead. Here, the configuration of input frames 110, 120, 130, and 140 is the same as the example shown in FIG.

When frames 110, 120, 130, and 140 of each channel are input, frame bytes 111, 121, 131, and 141 are extracted from the frames 110, 120, 130, and 140, and a new frame byte 161 is input. Generated. Here, the frames 110a, 120a, 130a, and 140a after the frame bytes 111, 121, 131, and 141 have been extracted are to be multiplexed. In the generated frame byte 161, the presence or absence of stuff of each channel and the number of stuff bits per frame are set. The frame byte 161 also includes information designating the CH having the highest clock frequency. Thereafter, the frames 110a, 120a, 130a, and 140a are multiplexed, and a new frame 160 is generated together with the frame byte 161.

The frame 160 is composed of a frame byte 161, overhead 162, 163, and a payload 165. Frames 110 a, 120 a, 130 a, and 140 a excluding the frame bytes 111, 121, 131, and 141 of each channel of the OC48 are interleaved and multiplexed and treated as a payload 165 in the frame 160. In the payload 165, a staff pit 164a is set. The number of stuff bits 164a is the sum of the number of stuff bits per frame of each channel.

The pointer method or the stuffing method described above has advantages and disadvantages, respectively. The pointer method is simple because it does not require the phase adjustment of the client signal, but as the number of multiplexes increases, the amount of information indicating the pointer increases. In stuffing, since it is necessary to determine the head position of a signal at the time of multiplexing, sufficient memory is required, but control information is less than in the pointer method. Therefore, efficient transmission is possible by adding a function that can be used according to the number of multiplexes.

Next, a specific circuit between the multiplexing circuit of the transparent multiplexing system and the demultiplexing circuit will be described. An example of a road configuration will be described.

FIG. 9 is a block diagram showing a multiplexing circuit. In the example of FIG. 9, signals of the speed of ΔC48 (ST Ml 6) are input for four channels (CH # 1 to CH # 4).

The CH # 1 signal is input to the clock extracting unit 211, the transmission frame detecting unit 241 and the FIF0281. The CH # 2 signal is input to the clock extraction unit 212, the transmission frame detection unit 242, and the FIFO 282. The signal of CH # 3 is input to clock extraction section 213, transmission frame detection section 243, and FIF0283. The signal of CH # 4 is input to clock extraction section 214, transmission frame detection section 244 and FIF I284.

The clock extracting unit 211 extracts a clock signal from the signal of CH # 1 and transmits the signal of clock frequency ί1 to the counter 221 and the maximum clock (MAXCLK) selecting unit 232. The clock extracting unit 212 extracts a clock signal from the signal of CH # 2, and transmits the signal of the clock frequency f2 to the counter 222 and the maximum clock selecting unit 232. The clock extraction unit 2 13 extracts a clock signal from the signal of CH # 3, and transmits the signal of the clock frequency f3 to the counter 223 and the maximum clock selection unit 232. The clock extracting unit 214 extracts a clock signal from the signal of CH # 4, and transmits the signal of the clock frequency f4 to the counter 224 and the maximum clock selecting unit 232.

To the counters 221 to 224, a signal of a predetermined frequency f0 is input from a local oscillator (OSC: OSCillator) 220. The frequency f 0 of OS C 220 needs to be at least twice the frequency of CH # 1 to CH # 4. The counter 221 counts the number of rises (or falls) of the input signal, and outputs the number of clock signals (COUNT # l) to the highest speed channel (CH) detector 231. The counter 222 counts the number of times the input signal rises (or falls), and outputs the number of clock signals (COUNT # 2) to the highest-speed CH detector 2 31. The counter 223 counts the number of times the input signal rises (or falls), and outputs the number of clock signals (COUNT # 3) to the maximum speed CH detector 231. The counter 224 counts the number of rising (or falling) times of the input signal, and counts the number of clock signals (COU). NT # 4) is output to the maximum speed CH detector 231.

The maximum speed CH detector 231 determines the maximum value of the number of clock signals (COUNT # l to # 4). Maximum speed CH detection section 231 outputs the channel (CH) number of the channel having the maximum number of clock signals to OH multiplexing section 300. Further, the maximum speed CH detection section 231 outputs a selection signal of the channel having the maximum number of clock signals to the maximum clock selection section 232 and the maximum (MAX) transmission frame detection section 251.

The maximum clock selection unit 232 selects one of the signals sent from the clock extraction units 211 to 214 (the signal of the highest speed channel) according to the maximum value CH selection signal. Then, the maximum clock selecting unit 232 transmits the selected signal to the quadruple unit (PLL unit) 233. .

The 1 ^ unit 233 generates a clock signal for the STM 64 and outputs the generated clock signal to the counters 261 to 264 and the FIFOs 281 to 284 as the maximum (MAX) clock.

The transmission frame detection unit 241 receives the signal of CH # 1, detects the transmission frame of CH # 1, and outputs the detected transmission frame to the counter 261 and the maximum transmission frame detection unit 251. The transmission frame detection unit 242 receives the signal of CH # 2, detects the transmission frame of CH # 2, and outputs the detected transmission frame to the counter 262 and the maximum transmission frame detection unit 251. The transmission frame detection unit 243 receives the signal of CH # 3, detects the transmission frame of CH # 3, and outputs the detected transmission frame to the counter 263 and the maximum transmission frame detection unit 251. The transmission frame detector 244 receives the signal of CH # 4, detects the transmission frame of CH # 4, and outputs the detected transmission frame to the power supply 264 and the maximum transmission frame detector 251.

Maximum transmission frame detection section 251 detects a signal of a transmission frame of a channel corresponding to the selection signal sent from maximum speed CH detection section 231 and outputs the signal to difference detection sections 271 to 274.

The counter 261 counts the number of input transmission frame signals in synchronization with the maximum clock, and compares the counted value (COUNT # 5) with the difference detection unit 271. And output. The counter 262 counts the number of input transmission frame signals in synchronization with the maximum clock, and outputs the counted value (C〇UNT # 6) to the difference detection unit 272. The counter 263 counts the number of input transmission frame signals in synchronization with the maximum clock, and outputs the counted value (COUNT # 7) to the difference detection unit 273. The counter 264 counts the number of input transmission frame signals in synchronization with the maximum clock, and outputs the counted value (COUNT # 8) to the difference detection unit 274.

The difference detection unit 271, based on the value of COUNT # 5 and the signal transmitted from the maximum transmission frame detection unit 251, detects a difference between the signal of CH # 1 and the signal of the highest speed CH, Output to OH multiplexing section 300. The difference detector 2 72 detects the difference between the signal of C C # 2 and the signal of the highest speed CH based on the value of COUN T # 6 and the signal transmitted from the maximum transmission frame detector 2 51. , ΟΗ Output to multiplexing section 300. The difference detection section 273 detects the difference between the signal of CH # 3 and the signal of the highest-speed CH based on the value of COUNT # 7 and the signal transmitted from the maximum transmission frame detection section 251. , OH multiplexing section 300. The difference detection unit 274 detects a difference between the signal of CH # 4 and the signal of the highest speed CH based on the value of COUNT # 8 and the signal transmitted from the maximum transmission frame detection unit 251, and performs OH multiplexing. Output to the conversion unit 300.

The clock signal CK1 and the maximum (MAX) clock are also input to FIF0281. The FIFO 282 further receives the clock signal CK2 and the maximum (MAX) clock. The clock signal CK3 and the maximum (MAX) clock are further input to FIF0283. In addition, the clock signal CK4 and the maximum (MAX) clock are input to the FIFO 284.

FI F0281 reads the signal in accordance with clock signal CK1 and outputs the signal to OH extraction section 291, in accordance with the maximum clock signal. The FI F0282 reads the signal in accordance with the clock signal CK2 and outputs the signal to the OH extraction unit 292 in accordance with the maximum clock signal. The FI FO 283 reads the signal according to the clock signal CK3 and outputs the signal to the OH extraction unit 293 according to the maximum clock signal. FI FO 2 84 is synchronized with clock signal CK 4 The signal is read, and the signal is output to the OH extraction unit 294 according to the maximum clock signal.

The OH extracting section 291 extracts an overhead (OH section) from the input CH # 1 signal in synchronization with the maximum clock signal, and outputs the overhead (OH section) to the OH multiplexing section 300.

The OH extraction section 292 extracts the overhead (OH section) from the input CH # 2 signal in synchronization with the maximum clock signal, and outputs it to the OH multiplexing section 300. The H extracting section 293 extracts the overhead (OH section) from the input CH # 3 signal in synchronization with the maximum clock signal, and outputs the overhead (OH section) to the OH multiplexing section 300.

The OH extracting section 294 extracts the overhead (OH section) from the input CH # 4 signal in synchronization with the maximum clock signal, and outputs the overhead (OH section) to the OH multiplexing section 300.

The OH multiplexing section 300 multiplexes the OH sections sent from the OH extracting sections 291 to 294. At this time, the OH multiplexing unit 300 stores information identifying the channel indicated by the highest-speed CH number in the frame byte area in the OH unit, and information on the other channels when compared with the highest-speed channel. Set the information indicating the speed difference (number of clock pulses). Then, the OH multiplexing section 300 outputs the multiplexed 0H. With the multiplexing circuit configured as described above, the input OC 48 speed signal is multiplexed and output. At this time, in the multiplexed OH, information for identifying the channel with the highest speed and information indicating the difference between the speeds of the other channels when compared with the channel are set.

FIG. 10 is a block diagram showing a separation circuit. The multiplexed signal is input to OH separation section 400. The OH separator 400 separates OH of each channel from the input signal. Then, OH separation section 400 sends the input signal to CK extraction section 411. Also, the OH separation unit 400 outputs the difference information for each channel included in the frame byte in the OH to the maximum (MAX) CH determination unit 412, and supports the difference calculation units 431 to 434. Output channel difference information.

The difference information of CH # 1 is sent to the difference calculation unit 431, the difference information of CH # 2 is sent to the difference calculation unit 432, the difference information of CH # 3 is sent to the difference calculation unit 433, and the difference information of CH # 4 is sent. The difference information is sent to the difference calculation unit 434. Further, OH separation section 400 outputs the OH section for each channel to FIs F451-454. FI F0451 The OH section of CH # 1 is output to FIF # 452, the 〇H section of CH # 2 is output to FIF # 452, the OH section of CH # 3 is output to FI F0453, and 1 # 454.

The OH section of H # 4 is output.

The CK extraction unit 411 extracts a clock signal from the input signal and outputs the clock signal to the PLL units 441 to 444 and the FIFs 0451 to 454.

Maximum channel determination section 412 determines the channel having the maximum speed from the difference information, and outputs the channel number of the channel to difference calculation sections 431 to 434. The difference calculation unit 431 calculates a difference (the number of pulses of the clock signal) from the channel based on the difference information of the CH # 1 signal and the channel number of the channel having the highest speed. Output. The difference calculation unit 432 calculates the difference (the number of pulses of the clock signal) from that channel from the difference information of the signal of CH # 2 and the channel number of the channel with the highest speed, Output. The difference calculation unit 433 calculates a difference (the number of pulses of the clock signal) from the channel based on the difference information of the CH # 3 signal and the channel number of the channel having the highest speed. Output to The difference calculation unit 434 calculates the difference (the number of pulses of the clock signal) from the channel based on the difference information of the signal of CH # 4 and the channel number of the channel having the highest speed. Output.

The extracting unit 441 generates a clock signal of the clock frequency f 1 of CH # 1 based on the clock signal (the highest-speed clock signal) input from the CK extracting unit 411 and the difference input from the difference calculating unit 431. Generate The PLL unit 442 converts the clock signal of the CH # 2 clock frequency f 2 based on the clock signal (the highest-speed clock signal) input from the CK extraction unit 411 and the difference input from the difference calculation unit 432. Generate. ? Unit 443 generates a clock signal of CH # 3 clock frequency f3 based on the clock signal (the highest speed clock signal) input from CK extraction unit 411 and the difference input from difference calculation unit 433. I do.

The PLL unit 444 converts the clock signal of the clock frequency f4 of CH # 4 based on the clock signal (the highest-speed clock signal) input from the CK extraction unit 411 and the difference input from the difference calculation unit 434. Generate. FI F0451 Is your company? Generated by unit 441: Receives clock signal of f1, and sends out OH of CH # 1 separated by OH separation unit 400 at OC48 (STM16) speed. The FI F0452 receives the clock signal of f2 generated by the PLL unit 442, and sends out the OH of CH # 2 separated by the 〇H separation unit 400 at a speed of 〇C48 (STM16). FI F0453 Is your company? The f3 clock signal generated by the 1 ^ unit 443 is received, and the OH of CH # 3 separated by the OH separation unit 400 is transmitted at the OC48 (STM 16) speed. The FI F0454 receives the clock signal of f4 generated by the PLL unit 444, and sends out the OH of CH # 4 separated by the OH separation unit 400 at the speed of OC48 (STM16).

With such a separating circuit, O H of each channel is separated from OH of the multiplexed frame, and 0 H of each channel is output at a clock frequency corresponding to each channel.

In the above description, the information indicating the channel number of the highest-speed channel is set in the frame pipe. However, a CH with a difference of “0” can be regarded as the highest-frequency CH. In this case, there is no need to include information indicating the channel number of the highest-speed channel in the OH after multiplexing.

Hereinafter, an example of the content of a transparent byte when a CH having a difference of “0” is regarded as a CH having the highest frequency will be described.

FIG. 11 is a diagram illustrating an example of the contents of a transparent byte. In this example, the frequency deviation between CH # 1 and CH # 4 is 3 bytes (corresponding to the frequency deviation of 0.4 GHz at 2.4 GHz), and the frequency of CH # 2 of OC48 (STM16) is the highest ( f2 is the maximum value). Also, set the clock frequency of each other channel to fl = S-0.001ppm (corresponding to 1 byte of 2.4GHz), f3 = f2-0.006ppm (corresponding to 2 bytes of 2.4GHz), f4 = £ 2-0.009ppm ( 2.4GHz 2 bytes).

Then, the highest-speed CH detector 231 in FIG. 9 determines that the frequency of CH # 2 is the highest, and the difference value of each channel is stored in the OH transparent byte 510. The difference value 51 1 of CH # 1 is “00001000”. The difference value 5 1 2 of CH # 2 is “00000000”. The difference value 5 13 of CH # 3 is “00010000”. The difference value 514 of 〇 ^ 1 # 4 is “00100000”. Thus, for CH # 2, all values are 0, indicating that it is the highest frequency. The difference value of the other channels CH # 1, CH # 3, and CH # 4 indicates the CH frequency deviation by the number of bits.

In the case of OC48, the A1 byte stores the same 48-byte synchronization pattern in the conventional technology. Similarly, A2 byte stores the same synchronization pattern of 48 bytes in the prior art. Therefore, 48 × 2 = 4 = 92 bytes are secured as the transparent byte 510 (when 4 bytes are used as a synchronization pattern).

When a frame including such a transparent byte is transmitted, on the receiving side, first, the CK extracting section 411 extracts the clock frequency f2 of CH # 2. The difference calculation units 431 to 434 and the PLL units 441 to 444 determine the clock frequency of CH # 1 f 1 = f 2— (the difference value of CH # 1) and the clock frequency of CH # 3 f 3 − f2- (difference value of CH # 3) and clock frequency f4 = f2- (difference value of CH # 4) of CH # 4 are obtained.

As described above, transparent transmission including SOH is possible in SONETZSDH. For clients, despite the fact that they are multiplexed in higher-order layers, the communication format as if they are using optical fiber communication at the client's speed layer can be easily achieved without affecting existing equipment. A system can be built. As a result, even when communication between clients is performed using the undefined bits of the SOH, it is possible to transmit to the communication partner including the undefined bits of the SOH. Moreover, the maintainability is improved by multiplexing the order wire information / section data of the multiplexed frame and transmitting the multiplexed data transparently.

Note that an error correction code can be added to the transparent byte. As a result, highly reliable communication can be performed.

Also, information other than frame bytes (including transparent bytes) can be scrambled. This can prevent malicious acts by a third party.

Also, using the above technology, it is possible to synchronize multiple frames via transparent transmission. As described above, in the present invention, the clock frequency of each frame of a plurality of channels is set to a frame byte, so that the transmission apparatus that has received the multiplexed frame refers to the frame byte before multiplexing. The clock frequency of the frame can be recognized. The resulting frame can be transmitted at the same clock frequency as before the multiplexing, and the frequency synchronization between opposing stations can be achieved. The above merely illustrates the principles of the invention. In addition, many modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact construction and application shown and described above, but all corresponding modifications and equivalents. Is deemed to be within the scope of the present invention by the appended claims and their equivalents.

Claims

The scope of the claims

1. In a transparent multiplexing method for transparently multiplexing a plurality of transmission signals,

Multiplexing multiple frames input from multiple channels,

Control information that defines the click frequency of each of the plurality of frames is set in the frame byte in the overhead of the multiplexed multiplexed frame.

A transparent multiplexing method characterized by the above-mentioned.

2. The transparent multiplexing method according to claim 1, wherein a signal for frame synchronization is left in a part of the frame byte, and the control signal is set in another part.

3. The transparent multiplexing method according to claim 2, wherein an area of at least 4 bytes is used for setting the frame synchronization signal.

4. The transparent multiplexing method according to claim 2, wherein the area in which the signal for frame synchronization is set is a boundary portion between two areas divided by a transmission protocol.

5. The control information includes the fastest channel information specifying the fastest channel having the highest frequency, and frequency difference information indicating a frequency difference between the frequency of the fastest channel and another channel. 2. The transparent multiplexing method according to claim 1.

6. The transparent multiplexing method according to claim 5, wherein a frequency difference 0 is set in association with the fastest channel.

7. The multiplex method according to claim 1, wherein, when multiplexing a plurality of frames, another signal is synchronized with a signal having the highest frequency.

8. The transparent multiplexing method according to claim 1, wherein the control information includes pointer information indicating a head of each of the frames.

9. The transformer according to claim 1, wherein said control information includes staffing information indicating the number of staff pulses added to each said frame. Allent multiplexing method.

10. Depending on the number of channels to be multiplexed, either one of the void information indicating the head of each frame and the stuffing information indicating the number of stuff pulses added to each frame is included in the control information. 3. The transparent multiplexing method according to claim 1, wherein the method comprises:

11. The transparent multiplexing method according to claim 1, wherein, when multiplexing a plurality of frames, multiplexing is performed including overhead of the plurality of frames.

1 2. In a transparent multiplexed signal separation method for separating a multiplexed frame in which a plurality of transmission signals are multiplexed transparently into a plurality of frames,

Extracting control information defining the click frequency of each of the plurality of frames from a frame byte in the overhead of the multiplexed frame;

Separating the multiplexed frame into a plurality of the frames;

Outputting the plurality of frames to the respective corresponding channels at the respective corresponding peak frequencies;

A transparent multiplexed signal separation method characterized by the above-mentioned.

1 3. In a transparent multiplexing device that multiplexes a plurality of transmission signals transparently,

A multiplexing unit that multiplexes a plurality of frames input from a plurality of channels; A control information setting section for setting the defined control information;

A transparent multiplexing device comprising:

1 4. In a transparent multiplexed signal demultiplexing apparatus for separating a multiplexed frame in which a plurality of transmission signals are multiplexed transparently into a plurality of frames, a plurality of the frame bytes in an overhead of the multiplexed frame are A control information extracting unit for extracting control information defining a clock frequency of each frame; a separating unit for separating the multiplexed frame into a plurality of the frames; An output unit that outputs the plurality of frames to the respective corresponding channels at the respective corresponding clock frequencies;

1. A transparent multiplexed signal demultiplexing device comprising: