WO2004084127A1 - メモリカードおよびその初期化設定方法 - Google Patents

メモリカードおよびその初期化設定方法 Download PDF

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Publication number
WO2004084127A1
WO2004084127A1 PCT/JP2003/003414 JP0303414W WO2004084127A1 WO 2004084127 A1 WO2004084127 A1 WO 2004084127A1 JP 0303414 W JP0303414 W JP 0303414W WO 2004084127 A1 WO2004084127 A1 WO 2004084127A1
Authority
WO
WIPO (PCT)
Prior art keywords
mmc
register
data
processing
reset
Prior art date
Application number
PCT/JP2003/003414
Other languages
English (en)
French (fr)
Inventor
Motoki Kanamori
Shigeo Kurakata
Chiaki Kumahara
Hidefumi Odate
Atsushi Shikata
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to US10/549,614 priority Critical patent/US7296097B2/en
Priority to PCT/JP2003/003414 priority patent/WO2004084127A1/ja
Priority to JP2004569590A priority patent/JP4173863B2/ja
Priority to TW092118385A priority patent/TW200502975A/zh
Publication of WO2004084127A1 publication Critical patent/WO2004084127A1/ja
Priority to US11/925,004 priority patent/US20080133860A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

　ホストから出力された初期化コマンドが'ＣＭＤ１'、'ＣＭＤ５５＋ＣＭＤ４１'のいずれであるかを初期化コマンド検出部８により検出し、その結果をＳＤ／ＭＭＣレジスタ１３にセットする。そして、ＳＤ／ＭＭＣレジスタ１３にセットされた検出結果に基づいて、ハードウェア、およびファームウェアのリセット処理をそれぞれ実行する。その後、マイクロコンピュータ７は、ファームウェアのリセット処理がマルチメディアカードモード、またはＳＤモードのいずれのモードによって実行されたかを示すデータをＦ／Ｗ処理ＳＤ／ＭＭＣレジスタ１４にセットする。Ｈ／Ｗ−Ｆ／Ｗモード比較回路１５は、ＳＤ／ＭＭＣレジスタ１３、およびＦ／Ｗ処理ＳＤ／ＭＭＣレジスタ１４のデータを比較し、一致していればリセットビジーを解除してコマンド待ち状態とし、不一致の際には、不一致発生検出信号をマイクロコンピュータ８に出力し、パワーオンリセット処理を再度行う。
PCT/JP2003/003414 2003-03-20 2003-03-20 メモリカードおよびその初期化設定方法 WO2004084127A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/549,614 US7296097B2 (en) 2003-03-20 2003-03-20 Memory card and initialization setting method thereof to avoid initializing operation failure in a memory card
PCT/JP2003/003414 WO2004084127A1 (ja) 2003-03-20 2003-03-20 メモリカードおよびその初期化設定方法
JP2004569590A JP4173863B2 (ja) 2003-03-20 2003-03-20 メモリカードおよびその初期化設定方法
TW092118385A TW200502975A (en) 2003-03-20 2003-07-04 Memory card and format setting method thereof
US11/925,004 US20080133860A1 (en) 2003-03-20 2007-10-26 Memory card and initialization setting method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/003414 WO2004084127A1 (ja) 2003-03-20 2003-03-20 メモリカードおよびその初期化設定方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/925,004 Continuation US20080133860A1 (en) 2003-03-20 2007-10-26 Memory card and initialization setting method thereof

Publications (1)

Publication Number Publication Date
WO2004084127A1 true WO2004084127A1 (ja) 2004-09-30

Family

ID=33018169

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/003414 WO2004084127A1 (ja) 2003-03-20 2003-03-20 メモリカードおよびその初期化設定方法

Country Status (4)

Country Link
US (2) US7296097B2 (ja)
JP (1) JP4173863B2 (ja)
TW (1) TW200502975A (ja)
WO (1) WO2004084127A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100373404C (zh) * 2005-09-13 2008-03-05 北京中星微电子有限公司 一种初始化存储卡的方法
WO2008029904A1 (en) * 2006-09-05 2008-03-13 Ricoh Company, Ltd. Memory card complying with a plurality of standards
JP2009506420A (ja) * 2005-08-29 2009-02-12 サンディスク アイエル リミテッド フラッシュメモリコントローラを構成するための装置および方法
US7987308B2 (en) 2005-08-01 2011-07-26 Samsung Electronics Co., Ltd. Multi-interface controller, memory card having the multi-interface controller, and interface setting method
JP2011175429A (ja) * 2010-02-24 2011-09-08 Fujitsu Semiconductor Ltd メモリコントローラ及び情報処理装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM264642U (en) * 2004-08-27 2005-05-11 Incomm Technologies Co Ltd Flash memory device having plural communication protocols
TWI242720B (en) * 2004-08-27 2005-11-01 Incomm Technologies Co Ltd A method, a control unit and a memory device for soft configuring communication protocols
WO2006057049A1 (ja) 2004-11-26 2006-06-01 Kabushiki Kaisha Toshiba カードおよびホスト機器
US8122232B2 (en) * 2007-06-21 2012-02-21 Arm Limited Self programming slave device controller
JP5728292B2 (ja) 2011-02-04 2015-06-03 株式会社東芝 メモリデバイス及びホストシステム
US9886080B2 (en) 2014-12-30 2018-02-06 Sandisk Technologies Llc Low voltage detection and initialization for non-volatile memory systems
US10437498B2 (en) 2016-09-28 2019-10-08 Samsung Electronics Co., Ltd. Electronic device configured to reset storage device non-directly connected to application processor among storage devices serially connected to one another and method of operating the same
CN111414125A (zh) * 2018-12-18 2020-07-14 华为技术有限公司 一种存储设备的操作方法及存储设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06187133A (ja) * 1992-04-15 1994-07-08 Internatl Business Mach Corp <Ibm> オペレーティングシステムのロードシステム、装置接続検出システム、及びオペレーティングシステムローダ決定方法
JP2003030613A (ja) * 2001-07-13 2003-01-31 Hitachi Ltd 記憶装置及び記憶装置を備えたデータ処理装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6168077B1 (en) * 1998-10-21 2001-01-02 Litronic, Inc. Apparatus and method of providing a dual mode card and reader
US6708231B1 (en) * 1999-08-12 2004-03-16 Mitsumi Electric Co., Ltd. Method and system for performing a peripheral firmware update
US20040064686A1 (en) * 2002-09-30 2004-04-01 Miller Gregory L. Method and apparatus for marking current memory configuration

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06187133A (ja) * 1992-04-15 1994-07-08 Internatl Business Mach Corp <Ibm> オペレーティングシステムのロードシステム、装置接続検出システム、及びオペレーティングシステムローダ決定方法
JP2003030613A (ja) * 2001-07-13 2003-01-31 Hitachi Ltd 記憶装置及び記憶装置を備えたデータ処理装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987308B2 (en) 2005-08-01 2011-07-26 Samsung Electronics Co., Ltd. Multi-interface controller, memory card having the multi-interface controller, and interface setting method
JP2009506420A (ja) * 2005-08-29 2009-02-12 サンディスク アイエル リミテッド フラッシュメモリコントローラを構成するための装置および方法
JP4734413B2 (ja) * 2005-08-29 2011-07-27 サンディスク アイエル リミテッド フラッシュメモリコントローラを構成するための装置および方法
CN100373404C (zh) * 2005-09-13 2008-03-05 北京中星微电子有限公司 一种初始化存储卡的方法
WO2008029904A1 (en) * 2006-09-05 2008-03-13 Ricoh Company, Ltd. Memory card complying with a plurality of standards
KR100993885B1 (ko) 2006-09-05 2010-11-11 가부시키가이샤 리코 복수의 규격에 대응하는 메모리 카드
JP2011175429A (ja) * 2010-02-24 2011-09-08 Fujitsu Semiconductor Ltd メモリコントローラ及び情報処理装置

Also Published As

Publication number Publication date
JP4173863B2 (ja) 2008-10-29
US20060248388A1 (en) 2006-11-02
TW200502975A (en) 2005-01-16
US7296097B2 (en) 2007-11-13
JPWO2004084127A1 (ja) 2006-06-22
US20080133860A1 (en) 2008-06-05

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