WO2004066576A1

WO2004066576A1 - Method and device for transmitting a pulse width modulated self-clocking signal

Info

Publication number: WO2004066576A1
Application number: PCT/SG2003/000012
Authority: WO
Inventors: Biju Sukumaran
Original assignee: Infineon Technologies Ag
Priority date: 2003-01-20
Filing date: 2003-01-20
Publication date: 2004-08-05

Abstract

Data is transferred between a plurality of processors using a binary signal consisting of alternating clock signal portions (clock) including a transition indicative of clock signal, and portions (data 1, data 0) encoding a binary bit. The clock signal portions are trnasitions from a first binary value (e.g. logic high), while the binary bits are encoded as either the continuation of the second binary value (data 1) or a period of the first binary value (data 0).

Description

METHOD AND DEVICE FOR TRANSMITTING A PULSE WIDTH MODULATED SELF-CLOCKING SIGNAL

Field of the Invention

The present invention relates to a method of transferring data as a data stream consisting of binary values.

5 Background of the Invention

It is conventional to use two signals for communication between two processors, one of the signals being a data signal and one being a clock signal. The clock signal requires a separate clock line.

The presence of such clock lines increases the complexity and cost of the 10 data processing systems. For this reason it has been proposed that the need for the clock lines may be obviated by adapting the processing operations performed the processors. Unfortunately, such techniques invariably increase significantly the complexity of the processing operations the processors must perform.

15 Summary of the invention

The present invention aims to provide new and useful methods for transferring data, and new and useful data processing systems.

In general terms, the present invention proposes that data is transferred using a binary signal in which some portions of the binary signal include a clock 20 signal, and other portions of the binary signal encode a data signal.

Preferably, the clock signal portions are periodic portions of the data signal including a transition between the binary values indicative of the clock signals, the transition indicating the timing of the clock signal. More preferably, the clock signal portions contain a transition from a first binary value (e.g. a low value) to a second binary value (e.g. a high value), and the binary data is encoded as the duration for which the clock signal remains in the second binary value.

For example, the binary signal may include, in alternation (i) clock signal portion consisting of the first binary value followed by the second binary value, and (ii) data signal portions which are either equal to the first binary value to encode a first binary digit or equal to the second binary value to encode a second binary digit. Thus, the timing of transitions from the first to the second binary value is indicative of the clock signal, and the timing of transitions from the second binary value to the first binary value is indicate of which binary digit is being transmitted.

Note that the processor which receives the binary signal is not required to extract the conventional clock signal from it. Instead, the processor can use the binary signal itself for clocking, provided that (i) it performs the clocking using only the transition from the first binary value to the second binary value, and (ii) the frequency of the these transitions is adequate.

Note that the concept of combining the timing and data into a single signal is not entirely new. The well-known "Manchester encoding" scheme, for example, is a coding scheme in which a first binary bit is encoded by transitions between first and second binary values, while a second binary bit is encoded by transitions in the opposite direction between the second and first binary values. The timing of the transitions encodes the clock signal, while the direction of transition encodes the binary bit. However, such a scheme is inappropriate for transferring both a clock signal and binary data between digital processing circuits, because the timing of the transitions is very difficult to extract by digital circuitry, and instead requires analogue circuitry of a kind which is difficult to implement in a fully digital integrated circuit.

Brief Description of The Figures

Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following figures in which:

Fig. 1 shows a binary signal according to the invention;

Fig. 2 shows a first input interface portion of a processor according to the invention; Fig. 3 illustrates the operation of the interface portion of Fig. 2;

Fig. 4 shows a first implementation of the input interface portion of Fig. 2; and

Fig. 5 shows a second implementation of the input interface portion of Fig. 2.

Detailed Description of the embodiments

Referring firstly to Fig. 1 , a data signal 1 according to the invention is shown, consisting of an alternating series of clock portions ("clock"), and data portions "data 1" and "data 0" which respectively represent the binary digits 1 and 0. Thus, Fig. 1 represents the data transfer of a bit pattern 0110. The clock portions ("clock") and data portions ("data 1" and "dataO") are each of the same length, which is termed the "clock period".

The clock portions all consist of a first binary value (logic low in Fig. 1 ) followed by a transition 3 to the other binary value (logic high in Fig. 2). The portions "data 1" consist of a period in which the second binary value is continued, while the portions "data 0" consist of periods an immediate transition to the first binary value.

Note that transitions 3 from the first binary value (logic low) to the second logic value (logic high) are always indicative of a clock signal. The duration for which the signal remains at the second logic value is indicative of whether the succeeding data period is indicative of the first or second binary value.

Fig. 2 shows an input interface portion for a processor which receives the data signal 1 of Fig. 1 and extracting the data from it. The interface portion includes an input 5 (which receives the data signal 1 ), a delay element 7 which delays its input by one clock period and then outputs it, and a flip-flop 9. The flip-flop 9 has inputs 11 , 13 and output 15. At any moment, the output 15 of the flip- flop 9 is the value of the input 11 at moment when the input 13 last changed from logic low to logic high. These transitions are always the result of respective transitions 3 caused in the data signal 1. Typically, the data processor extracts data from output 15 of the flip-flop 9 using a clock signal generated within the processor (and normally having a frequency which is much higher than the clock signal carried by the data signal 1 ) once a byte or word has been received. Such a system typically uses a shift register (not shown).

This is illustrated in Fig. 3, in which the data signal 1 is shown in relation to the data signal 16 which is the output 17 of the delay element 7. Data signal 16 is the data signal 1 delayed by one clock period. The transitions 3 in the data signal 16 always coincide with the centres of the data portions "data 0" and "data 1". Thus, the output 15 is a set of binary values which represent the sequence of respective binary bits in the data portions. Note that delay element 7 can be implemented by delay cells. Alternatively, Fig. 4 illustrates an implementation of Fig. 2 in which the delay element 7 is implemented using the flip-flops 17. This embodiment is applicable in the case that the processor receiving the data signal 1 includes an internal clock signal 19 having a frequency higher than the reciprocal of the clock period of the data signal 1. Each of the successive flip-flops 17 has inputs 111 , 113 and output 115, and has functions identically to the flip-flop 9 discussed above. Each of the flip-flops 17 passes on the signal it receives through its input 111 with a delay which is equal to the clock period of the signal 19, so that the set of flip-flops delays the binary signal 1 by an amount equal to the clock period of the signal 19 multiplied by the number of flip-flops 17. Thus, the arrangement of Fig. 4 is appropriate in the case that the period of the digital signal 1 is three times that of the clock signal 19.

Fig. 5 is a further embodiment of the interface portion including an additional flip-flop 21 at the input. The flip-flop 21 increases the stability of the circuit, to protect it against "metastability", i.e. the risk that the transitions 3 in the input signal 1 are close to the transitions in the input signal 19. The function of the flip-flop 21 will be understood to one skilled in this field.

Although only a few embodiments of the invention have been illustrated above, the invention is not limited in this respect and many variations are possible within the scope of the invention as will be clear to a skilled reader.

For example, although as illustrated in Fig. 1 the binary data signal 1 includes clock portions and data portions which are of the same duration (the clock period) the invention is not limited in this respect, and the duration of the clock portions may be different from that of the data portions. For example, it is possible for the clock portions to be shorter than the data portions. In this case, assuming that the duration of the data portions remains unchanged, the number of data bits which can be transmitted per second increases as the clock portions become progressively shorter. As this happens, the minimum time during which the data signal remains at the second binary value in the case that the clock portion is followed by a "data 0" becomes progressively shorter. This may set a minimum value for the duration of the clock portions such that the communication remains reliable, according to the properties of the data channel through which the transmission of the data signal 1 occurs.

Furthermore, note that in the embodiments above the binary signal 1 consists of an alternating sequence of (i) clock periods and (ii) data periods which each encode only a single binary bit. As explained, this is advantageous because it means that the binary signal can be such that the transition from the first to second binary value is always indicative of clock signals. Although this is advantageous, the invention is not limited in this respect. In alternative embodiments it is possible for each of the clock signals to be followed by a pair of data periods which each encode a single binary bit. This possibility is not preferred, however, since in this case more sophisticated circuitry is required to extract the binary data. This circuitry is however such that a skilled person will can implement straightforwardly.

Claims

1. A method of transmitting data between two processors, the method including transmitting a binary signal including clock signal portions encoding a clock signal, and data portions encoding binary data.

2. A method according to claim 1 in which the clock signal portions comprise a transition from a first binary value to a second binary value, and the binary data is encoded as the duration for which the binary signal remains in the second binary value.

3. A method according to claim 2 which the binary signal includes in alternation (i) clock signal portions consisting of the first binary value followed by the second binary value, and (ii) data signal portions which are equal to the first binary value to encode a first binary digit and equal to the second binary value to encode a second binary digit.

4. A method according to claim 3 in which the clock signal portions are of equal duration to the data signal portions.

5. A method according to claim 3 in which the clock signal portions are shorter than the data signal portions.

6. A data processor including an input interface portion including:

an input for receiving a binary signal including clock portions encoding a clock signal and data portions encoding binary data,

a delay portion for delaying the binary data signal; and

a selection portion for selecting a portion of the data signal based on the output of the delay portion.

7. A data processor according to claim 6 in which the delay portion contains of a sequence of one or more delay elements receiving a clock signal with a frequency higher than the reciprocal of the duration of the data portions of the binary signal.