WO2004061861A3 - Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same - Google Patents

Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same Download PDF

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Publication number
WO2004061861A3
WO2004061861A3 PCT/US2003/041848 US0341848W WO2004061861A3 WO 2004061861 A3 WO2004061861 A3 WO 2004061861A3 US 0341848 W US0341848 W US 0341848W WO 2004061861 A3 WO2004061861 A3 WO 2004061861A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory array
unselected
nand
nand strings
memory cells
Prior art date
Application number
PCT/US2003/041848
Other languages
French (fr)
Other versions
WO2004061861A2 (en
Inventor
En-Hsing Chen
Andrew J Walker
Roy E Scheuerlein
Sucheta Nallamothu
Alper Ilkbahar
Luca G Fasoli
Original Assignee
Matrix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/335,078 external-priority patent/US7505321B2/en
Priority claimed from US10/335,089 external-priority patent/US7005350B2/en
Priority claimed from US10/729,831 external-priority patent/US7233522B2/en
Application filed by Matrix Semiconductor Inc filed Critical Matrix Semiconductor Inc
Priority to AU2003300480A priority Critical patent/AU2003300480A1/en
Publication of WO2004061861A2 publication Critical patent/WO2004061861A2/en
Publication of WO2004061861A3 publication Critical patent/WO2004061861A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
PCT/US2003/041848 2002-12-31 2003-12-31 Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same WO2004061861A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003300480A AU2003300480A1 (en) 2002-12-31 2003-12-31 Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US10/335,078 US7505321B2 (en) 2002-12-31 2002-12-31 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US10/335,089 2002-12-31
US10/335,078 2002-12-31
US10/335,089 US7005350B2 (en) 2002-12-31 2002-12-31 Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US10/729,831 US7233522B2 (en) 2002-12-31 2003-12-05 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
US10/729,831 2003-12-05

Publications (2)

Publication Number Publication Date
WO2004061861A2 WO2004061861A2 (en) 2004-07-22
WO2004061861A3 true WO2004061861A3 (en) 2004-10-28

Family

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Family Applications (1)

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PCT/US2003/041848 WO2004061861A2 (en) 2002-12-31 2003-12-31 Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Country Status (2)

Country Link
AU (1) AU2003300480A1 (en)
WO (1) WO2004061861A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7317641B2 (en) 2005-06-20 2008-01-08 Sandisk Corporation Volatile memory cell two-pass writing method
US7764549B2 (en) 2005-06-20 2010-07-27 Sandisk 3D Llc Floating body memory cell system and method of manufacture
US7505326B2 (en) 2006-10-31 2009-03-17 Atmel Corporation Programming pulse generator
US7417904B2 (en) * 2006-10-31 2008-08-26 Atmel Corporation Adaptive gate voltage regulation
KR100890016B1 (en) 2007-05-10 2009-03-25 삼성전자주식회사 Nonvolatile memory device, memory system having its and program method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
EP0528367A1 (en) * 1991-08-13 1993-02-24 Fujitsu Limited Three-dimensional multi-chip module
EP0575051A1 (en) * 1992-05-22 1993-12-22 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US6005270A (en) * 1997-11-10 1999-12-21 Sony Corporation Semiconductor nonvolatile memory device and method of production of same
US6061270A (en) * 1997-12-31 2000-05-09 Samsung Electronics Co., Ltd. Method for programming a non-volatile memory device with program disturb control
US20010055838A1 (en) * 2000-04-28 2001-12-27 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6456528B1 (en) * 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
EP0528367A1 (en) * 1991-08-13 1993-02-24 Fujitsu Limited Three-dimensional multi-chip module
EP0575051A1 (en) * 1992-05-22 1993-12-22 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US6005270A (en) * 1997-11-10 1999-12-21 Sony Corporation Semiconductor nonvolatile memory device and method of production of same
US6061270A (en) * 1997-12-31 2000-05-09 Samsung Electronics Co., Ltd. Method for programming a non-volatile memory device with program disturb control
US20010055838A1 (en) * 2000-04-28 2001-12-27 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6456528B1 (en) * 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode

Also Published As

Publication number Publication date
AU2003300480A1 (en) 2004-07-29
WO2004061861A2 (en) 2004-07-22

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