WO2004030226A1

WO2004030226A1 - Method of calculating an intra-row permutation pattern for an interleaver

Info

Publication number: WO2004030226A1
Application number: PCT/IB2003/004058
Authority: WO
Inventors: Sébastien CHARPENTIER; Yordan Tabakov
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-09-25
Filing date: 2003-09-15
Publication date: 2004-04-08
Also published as: AU2003263448A1

Abstract

The invention relates to a method of calculating an intra-row permutation pattern for an interleaver. The intra-row permutation pattern comprises intra-row permutation elements stored in a matrix comprising rows and columns. The method comprises the steps (31, 32, 33) of calculating the numbers of rows and columns, a prime number and a primitive root and calculating a prime integer sequence (34). The method further comprises the steps of calculating (35) a new primitive root for each row of the matrix and, for each row of the matrix, defining (36) the intra-row permutation element corresponding to the first column and recursively calculating (37) the permutation elements corresponding to the other columns by multiplying modulo-p the permutation element corresponding to the preceding column with the new primitive root.

Description

Method of calculating an intra-row permutation pattern for an interleaver.

FIELD OF THE INVENTION

The present invention relates to a method of calculating an intra-row permutation pattern for an interleaver, said intra-row permutation pattern comprising intra-row permutation elements which are intended to be stored in a matrix comprising rows and columns, the method comprising the steps of calculating the numbers of rows and columns, a prime number and a primitive root, as a function of a length of a data block to be interleaved and calculating a prime integer sequence.

The present invention also relates to a circuit for implementing this method, a decoding circuit comprising an interleaver implementing this method, an electronic device and a telecommunication network comprising such a decoding circuit and a computer program for implementing this method.

The present invention is particularly relevant for a system for communicating data by satellite, or a system implementing the UMTS standard (UMTS stands for Universal Mobile Telecommunication System). For example, a third generation mobile phone might implement such a method.

BACKGROUND OF THE INVENTION

Interleavers are used in many coding and decoding circuits. For example, a turbo decoding circuit compliant with the UMTS standard uses an interleaver for mixing the positions of received data in order to randomise the error positions so that consecutive error accumulation due to Raleigh channel fading is avoided. Such an interleaver is described in the "3GPP TS 25.212 V3.9.0 (2002-03)" specification.

An object of this interleaver is to mix the positions of data bits in a data block comprising K bits, K being a variable integer varying from 40 to 5114. The interleaver transforms the data block into an interleaved data block, thanks to an interleaving pattern defined by an interleaving matrix comprising R rows and C columns.

Fig. 1 illustrates how the interleaving matrix is defined and how the bits of the data block are mixed thanks to this interleaving matrix. In this example, a data block B comprising 25 bits is interleaved and an interleaved data block B' is obtained. This example aims at showing, in a simple way, how the interleaved data block B' is obtained, and does not correspond to any real example. In particular, this example is not relevant for the "3GPP TS 25.212 V3.9.0 (2002-03)" specification, where the block length K is between 40 and 5114.

In this example, each bit of the data block B is identified by an identifier, from 0 to 24. The identifiers are first written in a first matrix Ml row by row. Then, an intra-row permutation is effected on the matrix Ml, according to an intra-row permutation pattern, and a matrix M2 is obtained. An inter-row permutation is then effected on the matrix M2, according to an inter-row permutation pattern, and a matrix M3 is then obtained. This matrix M3 is the interleaving matrix. The identifiers of the bits of the interleaved data block B' are then obtained by reading the identifiers from the interleaving matrix, column by column. In this example, the bit having the identifier "0", which is in the first position in block B, is in the twenty-fourth position in block B'. The bit having the identifier "5" in block B is on the second position in bloc B', and so on. For each value of K, a different interleaving pattern has to be determined.

Determining an interleaving pattern requires determining an intra-row permutation pattern and an inter-row permutation pattern. The above-mentioned specification specifies only four inter-row permutation patterns, which are defined in table 1. For example, the inter-row permutation pattern having the number "1" puts the twentieth row of the matrix M2, which is denoted as "19", instead of the first row of the matrix M2, which is denoted as "0", the tenth row instead of the second row and so on.

Table 1 : inter-row permutation patterns

The number of rows in the interleaving matrix and the inter-row permutation pattern directly depend on the block length K, as described in table 2. This table is stored in a memory and, knowing the block length K, the interleaver determines the number of rows R and the inter-row permutation pattern which have to be used. Therefore, when a data block with a given length K has to be interleaved, the interleaver does not have to calculate the number of rows of the matrix and the inter-row permutation pattern, as these parameters are predetermined. Conversely, as the number of columns C can adopt any integer value between 2 and 256, storing intra-row permutation patterns for each possible number of columns C would require a large memory. That is why the intra-row permutation pattern is calculated by the interleaver each time a data block with a new length K has to be interleaved.

Table 2: inter-row permutation patterns and R as function of K

Calculating the intra-row permutation pattern for a given block length K requires calculation of many parameters, which are described hereinafter.

First, a prime number p is determined, which is the minimum prime so that : (p-l) - K/R > 0

Then, the number of columns C is determined, which is the minimum of (p-1), p or (p+l) so that K≤ R*C

Then a primitive root v is determined as a function of p, as described in table 3.

Table 3: primitive root v as a function of prime number p

Then, a minimum prime integer sequence g is calculated, which is composed of R values and is constructed as follows:

- q[0] = 1 for j>0, q[j] is the smallest primary number so that :

• the greatest common divisor between q[j] and (p-1) is 1

• qϋ]>6

^• q[j]> q-j-i]

Then a permuted prime integer sequence r is calculated, which is a permuted version of g, using the inter-row permutation pattern T : r[T[j]] = q[j]

Then a base sequence s for intra-row permutation is calculated, which is composed of p-1 values and is constructed as follows:

- s[0] = 1

- s[i] = (v*s[i-l])mod p, where "mod p" indicates that the multiplication is effected modulo-p.

Finally, the intra-row permutation pattern is calculated for each column j. For a given column j, C intra-row permutation pattern elements Uj are calculated according to the following scheme, which is given for C=p :

- U_j[i] = s[(i*rD^'])mod(p-l)] for i = 0, 1, , p-2

- U_j[p-1] = 0

As a consequence, calculating the intra-row permutation pattern requires calculating a base sequence s for intra-row permutation and quantities (i*r[j])mod(p-l). This requires to perform a "modulo-p" operation in order to calculate the base sequence s and a "modulo-(p-l)" operation in order to calculate the Quantities (i iDmodCu-l . However, "modulo" ooerations consume a lot of resources in a circuit carrying out such operations. The calculation of the intra-row permutation pattern is therefore resource and power consuming.

Furthermore, a circuit for calculating the intra-row permutation pattern is complicated and requires a large silicon area. Fig.2 illustrates a circuit, which might be used to carry out the calculation of the intra-row permutation pattern as described hereinbefore. Such a circuit comprises a first register 20 for storing the permuted prime integer sequence, a multiplier modulo-(p-l) 21, an address decoder 22 and a second register 23. In order to calculate an intra-row permutation element Uj[i], the permuted prime integer is fetched from the first register 20 and multiplied by the value i by the multiplier 21, this multiplication being effected modulo-(p-l). The quantity (i*r[j])mod(p-l) is thus obtained, and the address decoder 22 checks the value s[(i*r[j])mod(p-l)] in the second register 23.

This circuit thus requires an address decoder, which is resource, power and area consuming. Moreover, the second register is large, because it has to store 257 values, as p can adopt the value 257. Such a register is therefore also area consuming. Furthermore, as the address decoder 22 has to access the second register 23 in a random way, the second register is a random access register, which is complicated and power consuming.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a method of calculating an intra-row permutation pattern, which might be implemented by a circuit, which is less resource, area and power consuming.

To this end, a method of calculating an intra-row permutation pattern according to the invention, as described in the opening paragraph, is characterised in that it comprises the steps of calculating a new primitive root for each row of the matrix, said new primitive root depending on a power of the primitive root, said power depending on the prime integer sequence and , for each row of the matrix, defining the intra-row permutation element corresponding to the first column and recursively calculating the permutation elements corresponding to the other columns by multiplying the permutation element corresponding to the preceding column by the new primitive root, said multiplication being carried out modulo the prime integer.

According to the invention, only one operation "modulo-p" is performed to calculate an intra-row permutation element. Furthermore, the calculation of an intra-row permutation element only requires multiplications, which are effected recursively. A circuit implementing this method thus does not need any address decoder. Moreover, as only C new primitive roots have to be calculated, a small register is required to store these new primitive roots, and this small register does not need to be a random access register, as the data might be accessed in a predetermined order. The method according to the invention might thus be implemented by a circuit, which is less resource, area and power consuming. The invention also relates to a circuit for implementing such a method. This circuit comprises a first circular register for storing the new primitive roots of each row, a modulo-p multiplier for calculating the permutation elements and a second circular register for temporarily storing the results of the calculations carried out by the modulo-p multiplier.

This circuit only requires two small circular registers, which have to store at most 20 values in the case of a circuit according to the "3GPP TS 25.212 V3.9.0 (2002-03)" specification.

Advantageously, as the modulo-p multiplication requires many clock cycles to be performed, the modulo-p multiplier is pipelined. This means that new values to be multiplied modulo-p enters the modulo-p multiplier at each clock cycle and that a result of a modulo-p multiplication exits the modulo-p multiplier at each clock cycle. The circuit thus allows calculating an intra-row permutation element at each clock cycle.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 illustrates the calculation of an interleaving matrix and an interleaved block; - Fig. 2 is a block diagram illustrating a circuit for calculating an intra-row permutation pattern according to the prior art;

Fig. 3 is a diagram illustrating a method of calculating an intra- row permutation pattern in accordance with the invention;

Fig. 4 is a block diagram illustrating a circuit for implementing the method of Fig.3;

Fig.5 is a block diagram illustrating a modulo-p multiplier, which might be used in the circuit of Fig.4.

DETAILED DESCRIPTION OF THE INVENTION A method of calculating an intra-row permutation pattern according to the invention is depicted in Fig.3.

At step 31, the number of rows is calculated, as it has been described hereinbefore. At step 32, the prime number p and the primitive root v are calculated i and at step 32 the number of columns is calculated. All these quantities depend on the block length K. At step 34, a prime integer sequence is calculated. This prime integer sequence is, for example, the minimum prime integer sequence g_, or the permuted prime integer sequence r.

At step 35, a new primitive root v'[j] is calculated for each row j. This J) new primitive root depends on a power of the primitive root v, said power depending on the prime integer sequence. In the following, the new primitive root v'[j] is defined by : v'[j] = v^r[j] Of course, other primitive roots might be used for implementing the 5 method according to the invention. For example, the following primitive roots might be used :

^■ v'[j] = v^rϋ:ιmod p

^■ v'[j] = v^q[j]

■ v'[j] = v^q[j]modp

,0 Once the new primitive root for a given row j has been calculated, the intra-row permutation element U_j[0] corresponding to the first row is defined at step 36. For example, it is possible to define Uj[0] = 1 for each row. It is important to notice that this step 36 might be performed at any stage of the method in accordance with the invention. For example, the intra-row permutation elements Uj[0] might be

>5 predetermined before performing the other steps of the method in accordance with the invention.

Then, the other intra-row permutation elements corresponding to the given row j are calculated at step 37. It is important to notice that the intra-row permutation elements might be calculated column by column, instead of row by row. 0 A column-by-column calculation is described in the description of Fig.4. A row-by- row calculation is detailed hereinafter.

The intra-row permutation elements corresponding to the given row j are calculated according to the expression: Uj[i+1] = (v'[j]* Uj[i])mod p It is easy to show that this expression corresponds to the calculation of the intra-row permutation elements according to the prior art. Actually:

- The expression s[i] = (v*s[i-l])mod p is equivalent to the expression s[i] = (v'*s[0])mod p = v'mod p. i - As a consequence, the expression Uj[i] = s[(i*r[j])mod(p-l)] is equivalent to the expression Uj[i] = v^'^^^^^mod p.

- Furthermore, let us write a = v and i*r[j] = b, then:

- a^bmod p = [a^n(p-¹⁾][a ^{mod ( "1}}]mod p, where n is such that b = n(p-l) + bmod

(P-1). ) - Thus, a^bmod p = [a^n(p-^1}mod ρ][a^{bmod (p"1}}]mod p

= [(a^^mod p][a^{bmod (p}-^υ]mod p = [a^-^mod p]ⁿ[a^{bmod (p'1}}]mod p

- A well-known theorem indicates that, if p is a primary number and the greatest common divisor between a and p is 1, then a^(p_1)mod p = 1. In this example,

5 a = v and v is never equal to p, which implies that the greatest common divisor between a and p is 1. Thus, [a^(p_1)mod p]ⁿ = 1. As a consequence: a^bmod p = a^{bmod (p}-¹⁾mod

- Then, replacing a by v and b by i*r[j] in this expression leads to the following expression: v^ od p = v^^^mod p = U_j[i]

:0 - This expression is equivalent to the expression: U_j[i] = (v'[j])^Imod p, where v'[j] = v^r[j]

- Applying this expression recursively leads to the following expression:

U_j[i+l] = (v'ϋ]* U_j[i])mod p

Suppose another new primitive root is used for implementing this method, for 5 example v' [j] = v^q[j]. Then it is easy to show that; Uτrj][i+l] = (v'[j]* Uτ[_j][i])mod p

This expression might also be used in order to calculate the intra-row permutation elements corresponding to the row T[j].

As a consequence, the intra-row permutation elements of a given row 0 might easily be calculated by implementing the method in accordance with the invention. Knowing the first intra-row permutation element of this given row and the new primitive root for this given row, the second intra-row permutation element is calculated by multiplying the first intra-row permutation element by the new primitive root, this multiplication being carried out modulo-p. The third intra-row permutation element is calculated by multiplying the second intra-row permutation element by the new primitive root, this multiplication being carried out modulo-p, and so on.

Fig. 4 illustrates a circuit for implementing the method in accordance with the invention. Such a circuit comprises a first circular register 41, a second circular register 42 and a modulo-p multiplier 43. The new primitive roots of each row are stored in the first circular register 41, which can store 20 values in order to be able to store the new primitive roots for any block length K, as R new primitive roots are calculated in accordance with the invention, and R has at most the value 20.

First, the intra-row permutation elements U_j[0] corresponding to the first column are stored in the second circular register 42. Then, the intra-row permutation element U₀[l] corresponding to the second column of the first row is calculated. In order to carry out this calculation, the new primitive root v'[0] is fetched from the first circular register 41 and the intra-row permutation element U₀[0] is fetched from the second circular register 42. The new primitive root v'[0] is then recopied at the end of the first circular register 41. These two values are multiplied by the modulo-p multiplier 43, this multiplication being carried out modulo-p. The result U₀[l] is sent to the interleaving matrix M3, and recopied at the end of the second circular register 42.

Then, the intra-row permutation element Uι [l] is calculated. In order to carry out this calculation, the new primitive root v'[l] is fetched from the first circular register 41 and the intra-row permutation element Uι [0] is fetched from the second circular register 42. The new primitive root v'[l] is then recopied at the end of the first circular register 41. These two values are multiplied by the modulo-p multiplier 43, this multiplication being carried out modulo-p. The result Uι [l] is sent to the interleaving matrix M3, and recopied at the end of the second circular register 42. The intra-row permutation elements Uj[l] are calculated the same way for each row j.

Once the intra-row permutation element corresponding to the second column of the last row has been calculated, i.e. U₁₉[l] in the example of Fig.4, the value at the beginning of the first circular register 41 is v'[0] and the value at the beginning of the second circular register 42 is U₀[l]. The intra-row permutation element U₀[2] can thus be calculated by fetching the value v'[0] from the first circular register 41 and the value U₀[l] from the second circular register 42. Then the intra-row permutation element Uι[2] is calculated, and so on.

The circuit of Fig.4 thus allows easy calculation of the intra-row permutation pattern. Only two circular registers are required, which have to store only a few values. This circuit thus does not take up a lot of resources, power and area.

Fig. 5 illustrates a modulo-p multiplier, which might be used in the ) circuit of Fig.4, to decrease the time required to calculate the intra-row permutation pattern. Actually, in the description hereinbefore, it was supposed that an intra-row permutation element Uj₊ι [i] is not fetched from the second circular register 42 until the calculation of the intra-row permutation element Uj [i+1] is effected. However, the operation carried out by the modulo-p multiplier might require a few clock cycles. The time required to calculate the intra-row permutation pattern is therefore quite large. In order to remedy this drawback, the modulo-p multiplier is pipelined, as explained hereinafter.

The circuit of Fig. 5 comprises four modulo-p shifters 501 to 504, four modulo-p adders 511 to 514, five multiplexers 521 to 525 and twelve registers 531 to 542.

Multiplying two values x and y modulo-p with the circuit of Fig.5, wherein x and y are smaller than p, might be effected in the following way, when x and y are written in binary language. Suppose the length of x and y is 5 bits, which are written x(0), x(l), x(2), x(3) and x(4) from the least significant bit to the most significant bit, and y(0), y(l), y(2), y(3) and y(4). At step 51, the value x is sent to the modulo-p shifter 501 and to the multiplexer 521, and the value y is sent to the register 531. If the bit y(0) is equal to 1, the value x is copied in the register 539. Otherwise, the value 0 is copied in the register 539. The modulo-p shifter shifts the value x to the left, and compares the result of the shift with p. This result is written x(l) x(2) x(3) x(4) 0. If this result is greater than p, a modulo-p operation is performed on this result and the new result is written in the register 535. Otherwise, this result is copied in the register 535.

At step 52, the value stored in the register 535 is sent to the modulo-p shifter 502 and to the multiplexer 522, and the value y is sent to the register 532. Each step requires one clock cycle to fetch the values from the registers. If the second bit y(l) of the value y is equal to 1, the value stored in the register 535 is sent to the modulo-p adder 511. Otherwise, the value 0 is sent to the modulo-p adder 511. The value stored in the register 539 is also sent to the modulo-p adder 511. The modulo-p adder 511 thus performs a modulo-p addition with these two values, and sends the result to the register 540.

Similar operations are carried out at steps 53, 54 and 55, and the result of the modulo-p multiplication between x and y is obtained at the output of the modulo-p adder 514. As the steps 51 to 55 are performed one after the other, the circuit of

Fig. 5 might be pipelined. Such a pipelined circuit might be used in order to implement the method in accordance with the invention, as described hereinafter.

Suppose the length of the new primitive roots and of the intra-row permutation elements is 5 bits. Then, a modulo-p multiplication between a new primitive root and an intra-row permutation element requires 5 clock cycles. In order to calculate the intra-row permutation element U₀[l], the new primitive root v'[0] is sent at step 51 to the register 531, and the intra-row permutation element U₀[0] is sent to the modulo-p shifter 501 and to the multiplexer 521. After a first clock cycle, step 52 is performed during a second clock cycle. During this second clock cycle, the new primitive root v'[l] is sent to the register 531, and the intra-row permutation element U^O] is sent to the modulo-p shifter 501 and to the multiplexer 521, in order to perform the first step of the modulo-p multiplication between v'[l] and

Uι [0], while the second step of the modulo-p multiplication is performed between v'[0] and U₀[0]. Then, during a third clock cycle, the second step of the modulo-p multiplication is performed between v'[l] and Uι [0] and the third step of the modulo-p multiplication is performed between v'[0] and Uo[0]. During this third clock cycle, the new primitive root v'[2] is sent to the register 531, and the intra-row permutation element U₂[0] is sent to the modulo-p shifter 501 and to the multiplexer

521, in order to perform the first step of the modulo-p multiplication between v'[2] and U₂[0].

Fig. 5 illustrates the calculations performed during a fifth clock cycle. The fifth step of the modulo-p multiplication is performed between v'[0] and U₀[0], where the multiplexer 525 checks if the fifth bit v'[0](4) of the new primitive root v'[0] is equal to 1. The fourth step of the modulo-p multiplication is performed between v'[l] and Uι [0], where the multiplexer 524 checks if the fourth bit v'[l](3) of the new primitive root v'[l] is equal to 1, and so on. The first step of the modulo- p multiplication is performed between v'[4] and U₄[0], where the multiplexer 521 checks if the first bit v'[4](0) of the new primitive root v'[4] is equal to 1. After this fifth clock cycle, the intra-row permutation element U₀[l] is sent to the interleaving matrix. After a sixth clock cycle, the intra-row permutation element Uι [l] is sent to the interleaving matrix, and so on. The pipelined circuit of Fig. 5 thus allows calculating an intra-row permutation element at each clock cycle, after a predetermined number of clock cycles, depending on the bit length of the intra-row permutation elements, which depends on the block length K. Using such a pipelined circuit thus allows to reduce the time required for calculating the intra-row permutation pattern.

An interleaver implementing the method in accordance with the invention may be implemented in a decoding circuit, which may be implemented in an electronic device, such as a mobile phone. Such a decoding circuit may form part of a telecommunication network comprising a transmitter for sending encoding signals, a transmission channel and a receiver for receiving said signal.

The method for calculating an intra-row permutation pattern according to the invention might be implemented in an integrated circuit, which is intended to be integrated in a decoding circuit. A set of instructions that is loaded into a program memory causes the integrated circuit to carry out the method for calculating an intra-row permutation pattern. The set of instructions may be stored on a data carrier such as, for example, a disk. The set of instructions can be read from the data carrier so as to load it into the program memory of the integrated circuit, which will then fulfil its role.

Any reference sign in the following claims should not be construed as limiting the claim. It will be obvious that the use of the verb "to comprise" and its conjugations does not exclude the presence of any other elements or steps besides those defined in any claim. The word "a" or "an" preceding an element or a step does not exclude the presence of a plurality of such elements.

Claims

1. A method of calculating an intra-row permutation pattern for an interleaver, 5 said intra-row permutation pattern comprising intra-row permutation elements which are intended to be stored in a matrix comprising rows and columns, the method comprising the steps (31, 32, 33) of calculating the numbers of rows and columns, a prime number and a primitive root, as a function of a length of a data block to be interleaved and calculating (34) a prime integer sequence, the method further being characterized in that it comprises the

L0 steps of calculating (35) a new primitive root for each row of the matrix, said new primitive root depending on a power of the primitive root, said power depending on the prime integer sequence and, for each row of the matrix, defining (36) the intra-row permutation element corresponding to the first column and recursively calculating (37) the permutation elements corresponding to the other columns by multiplying the permutation element corresponding to

15 the preceding column by the new primitive root, said multiplication being carried out modulo the prime integer.

2. A circuit for implementing the method as claimed in claim 1, said circuit comprising a first circular register (41) for storing the new primitive roots of each row, a 0 modulo-p multiplier (43) for calculating the permutation elements and a second circular register (42) for temporarily storing the results of the calculations carried out by the modulo-

P-

3. A circuit as claimed in claim 2, wherein the modulo-p multiplier is pipelined. 5

4. A decoding circuit comprising an interleaver implementing the method as claimed in claim 1.

5. An electronic device comprising a decoding circuit as claimed in claim 4. 0

6. A telecommunication network comprising a transmitter for sending encoding signals, a transmission channel, a receiver for receiving said signal and a decoding circuit as claimed in claim 4.

7. A computer program comprising a set of instructions which, when loaded into a processor or a computer, causes the processor or the computer to carry out the method as claimed in claim 1.