WO2004002041A2

WO2004002041A2 - Broadcast router having a multirate serial digital audio data stream encoder

Info

Publication number: WO2004002041A2
Application number: PCT/US2003/019390
Authority: WO
Inventors: Carl Christensen; David Lynn Bytheway; Lynn Howard Arbuckle
Original assignee: Thomson Licensing S.A.
Priority date: 2002-06-21
Filing date: 2003-06-20
Publication date: 2003-12-31
Also published as: WO2004002041A3; AU2003251573A8; AU2003251573A1

Abstract

An average bit time (406) and an excess sample count (406) are determined for a selected N-bit frame of AES serialized output digital audio data (404) to be encoded. An N-bit bi-phase encoded frame is then constructed (412, 414) from the N-bit frame of digital audio data, the average bit time, the excess sample count and a selected bit sampling rate (401) for the digital audio data stream. If the excess sample count is determined to be equal to zero (410), each data bit of the encoded frame would have the same time duration and thus contain the same number of samples therein (412). If the excess sample count is determined to be greater than zero (410), X bits of the encoded frame would have a time duration greater and thus contain a greater number of samples than that of the remaining N-X bits of the encoded frame (414).

Description

BROADCASTTtOUTER HAVING A MULTIRATE SERIAL DIGITAL AUDIO DATA STREAM ENCODER

CROSS REFERENCE

This application is related to U.S. Provisional Patent Application Ser. No. 60/390,353 filed June 21, 2002.

This application is also related to co-pending U.S. Patent Application Ser. Nos.

PCT/ (Atty. Docket No. IU010620), PCT/ (Atty. Docket No. IU020157),

PCT/ (Atty. Docket No. IU020159), PCT/ (Atty. Docket No. IU020160),

PCT/ (Atty. Docket No. IU020161), PCT/ (Atty. Docket No. IU020162), PCT/ (Atty. Docket No. IU020252), PCT/ (Atty. Docket No. IU020253),

PCT/ (Atty. Docket No. IU020254), PCT/ (Atty. Docket No. IU020255), and PCT/ (Atty. Docket No. IU020256), all of which are assigned to the Assignee of the present application and hereby incorporated by reference as if reproduced in their entirety. FIELD OF THE INVENTION

The present invention relates to serial digital audio data stream encoders suitable for use in broadcast routers and, more particularly, to a serial digital audio data stream encoder capable of encoding data at various sample rates.

BACKGROUND OF THE INVENTION Traditionally, serial digital audio encoders have used either a PLL or clock rate changes to change the sample rate at which incoming data is encoded. Either approach, however, tends to increase the complexity of the serial digital audio encoder. For example, to use a PLL in a serial digital audio encoder, external components are typically required. As a result, serial digital audio encoders which incorporate a PLL tend to be both more expensive and unwieldy. It is an object of this invention, therefore, to provide a serial digital audio encoder and an associated method of encoding serial which improves upon traditional techniques.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is directed to a method of encoding a digital audio data stream at a selected sample rate. In accordance with the method, a segment from a digital audio data stream and a sample rate at which the selected segment is to be encoded are selected. Preferably, the selected sample rate is generally equal to the product of an average bit time for the selected segment and an integral value. A corresponding segment of an encoded serial digital audio data stream is then constructed from the selected segment such that it is characterized by having a sampling count generally equal to the product of the total number of data bits in the selected segment, an average bit time for the selected segment and the selected sample rate. The constructed segment is further characterized by each data bit thereof having a time duration determined based upon the distribution of the sampling count over the constructed segment. In various aspects thereof, the sampling count may be integrally, unevenly or evenly distributed over the constructed segment. In further aspects thereof, the even distribution of the sampling count may be a distribution in which each data bit of the constructed segment contains an equal number of samples or may be a distribution in which at least one data bit of the constructed segment contains N samples and at least one data bit of the constructed segment contains N+l samples.

In another embodiment, the present invention is directed to a method of encoding digital audio data into a digital audio data stream. In accordance with this method, an average bit time ("A") and an excess sample count ("XSC") are determined for a N-bit frame of digital audio data to be encoded. An N-bit encoded frame of a digital audio data stream is then constructed from the N-bit frame of digital audio data, the average bit time, the excess sample count and a bit sampling rate ("MR") for the digital audio data stream. Preferably, the bit sampling rate is selected such that it is an integral factor of the average bit time. If the excess sample count is determined to be equal to zero, each data bit of the encoded frame would have the same time duration and thus contain the same number of samples therein. If the excess sample count is determined to be greater than zero, X bits of the encoded frame would have a time duration greater and thus contain a greater number of samples than that of the remaining N-X bits of the encoded frame.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a fully redundant, linear expandable broadcast router; FIG.

2 is an expanded block diagram of a first broadcast router component of the fully redundant, linearly expandable broadcast router of FIG. 1 ;

FIG. 3 is an expanded block diagram of an AES output circuit of the first broadcast router component of FIG. 2 within which a bi-phase encoder constructed in accordance with the teachings of the present invention resides; and

FIG. 4 is a flow chart of a method for encoding audio digital data using the bi-phase encoder of FIG. 3. DETAILED DESCRIPTION

Referring first to FIG. 1, a fully redundant, linearly expandable broadcast router 100 will now be described in greater detail. As may now be seen, the fully redundant, linearly expandable broadcast router 100 is comprised of plural broadcast router components coupled to one another to form the larger fully redundant linearly expandable broadcast router 100. Each broadcast router component is a discrete router device which includes first and second router matrices, the second router matrix being redundant of the first router matrix. Thus, each broadcast router has first and second routing engines, one for each of the first and second router matrices, each receiving, at an input side thereof, the same input digital audio data streams and placing, at an output side thereof, the same output digital audio data streams. As disclosed herein, each of the broadcast router components used to construct the fully redundant, linearly expandable broadcast router are N x M sized broadcast routers. However, it is fully contemplated that the fully redundant, linearly expandable broadcast router 100 could instead be constructed of broadcast router components of different sizes relative to one another.

As further disclosed herein, the fully redundant, linearly expandable broadcast router 100 is formed by coupling together first, second, third and fourth broadcast router components 102, 104, 106 and 108. Of course, the present disclosure of the fully redundant, linearly expandable broadcast router 100 as being formed of four broadcast router components is purely by way of example. Accordingly, it should be clearly understood that a fully redundant, linearly expandable broadcast router constructed in accordance with the teachings of the present invention may be formed using various other numbers of broadcast router components. The first, second, third and fourth broadcast router components 102, 104, 106 and 108 which, when fully connected in the manner disclosed herein, collectively form the fully redundant, linearly expandable broadcast router 100, may either be housed together in a common chassis as illustrated in FIG. 1 or, if desired, housed in separate chassis. While, as previously set forth, the broadcast router components 102, 104, 106 and 108 may have different sizes relative to one another or, in the alternative, may all have the same N x M size, one size that has proven suitable for the uses contemplated herein is 256 x 256. Furthermore, a suitable configuration for the fully redundant, linear expandable broadcast router 100 would be to couple five broadcast router components, each sized at 256 x 256, thereby resulting in a 1,280 x 1,280 broadcast router. The first broadcast router component 102 is comprised of a first router matrix 102a and a second (or "redundant") router matrix 102b used to replace the first router matrix 102a in the event of a failure thereof. Similarly, each one of the second, third and fourth broadcast router components 104, 106, and 108 of the fully redundant, linearly expandable broadcast router 100 are comprised of a first router matrix 104a, 106a and 108a, respectively, and a second (or "redundant") router matrix 104b, 106b and 108b, respectively, used to replace the first router matrix 104a, 106a and 108a, respectively, in the event of a failure thereof. Of course, the designation of the second router matrices 102b, 104b, 106b and 108b as a redundant matrix for use as a backup for the first router matrices 102a, 104a, 106a and 108a, respectively, in the event of a failure thereof is purely arbitrary and it is fully contemplated that either one of a router matrix pair residing within a broadcast router component may act as a backup for the other of the router matrix pair residing within that broadcast router component.

As may be further seen in FIG. 1, the first router matrix 102a of the first broadcast router component 102, the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108 are coupled together in a first arrangement of router matrices which conforms to a fully connected topology. Similarly, the second router matrix 102b of the first broadcast router component 102, the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108 are coupled together in a second arrangement which, like the first arrangement, conforms to a fully connected topology. In a fully connected topology, each router matrix of an arrangement of router matrices is coupled, by a discrete link, to each and every other router matrix forming part of the arrangement of router matrices.

Thus, for the first arrangement of router matrices, first, second and third bi-directional links 110, 112 and 114 couples the first router matrix 102a of the first broadcast router component 102 to the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108, respectively. Additionally, fourth and fifth bi-directional links 116 and 118 couple the first router matrix 104a of the second broadcast router component 104 to the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108, respectively. Finally, a sixth bi-directional link 120 couples the first router matrix 106a of the third broadcast router component 106 to the first router matrix 108a of the fourth broadcast router component 108.

Similarly, for the second arrangement of router matrices, first, second and third bi- directional links 122, 124 and 126 couples the second router matrix 102b of the first broadcast router component 102 to the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108, respectively. Additionally, fourth and fifth bi-directional links 128 and 130 couple the second router matrix 104b of the second broadcast router component 104 to the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108, respectively. Finally, a sixth bi-directional link 132 couples the second router matrix 106b of the third broadcast router component 106 to the second router matrix 108b of the fourth broadcast router component 108. Variously, the bi- directional links 110 through 120 may be formed of copper wire, optical fiber or another transmission medium deemed suitable for the exchange of digital signals. Of course, rather than the single bi-directional links between pairs of broadcast router components illustrated in FIG. 1, in an alternate embodiment of the invention, it is contemplated that the pairs of broadcast router components may instead be coupled together by first and second uni- directional links. Such an alternate configuration is illustrated in FIG. 2.

The broadcast router components 102, 104, 106 and 108 will now be described in greater detail. FIG. 2 shows the first broadcast router component 102. The second, third and fourth broadcast router components 104, 106 and 108, on the other hand, are similarly configured to the first broadcast router component 102 and need not be described in greater detail. Of course, it should be clearly understood that certain components of the foregoing description of the first broadcast router component 102, as well as the second, third and fourth broadcast routers 104, 106 and 108 have been simplified for brevity of description. It is noted, however, that further details thereof may be found by reference to co-pending U.S. patent application Ser. No. 10/ (Atty. Docket No. IU020160) and previously incorporated by reference.

As may be seen in FIG. 2, the broadcast router 102 includes N selectors 138-1 through 138-N arranged such that the output of each one of the selectors provides one of N transport streams to an input side of each one of the router matrices 102a, 102b of the first broadcast router component 102. As disclosed herein, each one of the selectors 138-1 through 138-N is a first 2: 1 selector circuit having, as a first input thereto, a first transport stream built by an Audio Engineering Society ("AES") input circuit 140-1 through 140-N, respectively, and, as a second input thereto, a second transport stream built from a decoded digital audio data stream conforming to the multichannel digital audio ("MADI") standard by a MADI input circuit 142-1 through 142-N, respectively. Each one of the first selector circuits 138-1 through 138- N further includes a control input (not shown) for selecting between the two transport streams. The selected transport stream output each one of the first selector circuits 138-1 through 138-N is fed to an input side of a routing engine 144, a transmitting (or "TX") expansion port 276, a first receiving (or "RX") expansion port 278, a second receiving expansion port 280 and a third receiving expansion port 282 of the first router matrix 102a. By the term "transmitting" expansion port, it is intended to refer to an expansion port from which data is transmitted to a selected destination. Similarly, by the term "receiving" expansion port, it is intended to refer to an expansion port which receives data from a destination. In a broad sense, the transmitting expansion port 276 of the first router matrix 102a is comprised of a memory subsystem in which the transport streams received from the first selector circuits 138-1 through 138-N of the first broadcast router component 102 are buffered before transfer to plural destinations and a processor subsystem for controlling the transfer of the transport streams received from the first selector circuits 138-1 through 138-N to a receiving expansion port of the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108. Conversely, each one of the first, second and third expansion ports 278, 280 and 282 of the first router matrix 102a are, in a broad sense, comprised of a memory subsystem in which input transport streams received from a transmitting expansion port of the first router matrix of another broadcast router component may be buffered before transfer to their final destination and a processor subsystem for controlling the transfer of the input transport streams received from the transmitting expansion port of the first router matrix of the other broadcast router component to inputs of the routing engine 144 of the first router matrix 102a of the first broadcast router component 102.

From the first selector circuits 138-1 through 138-N, transport streams 1 through N containing information extracted from AES input 1-32N and/or MADI inputs 1-N are transmitted to the routing engine 144 and the transmission expansion port 276. From the transmission expansion port 276, input transport streams 1 through N are forwarded to the first router matrix 104a of the second broadcast router component 104 over the link 110, to the first router matrix 106a of the third broadcast router 106 over the link 112 and to the first router matrix 108a of the fourth broadcast router 108 over the link 114. In return, input transport streams N+l through 2N are transmitted, from the transmission expansion port of the first router matrix 104a of the second broadcast router component 104, to the first receiver expansion port 278 over the link 110; input transport streams 2N+1 through 3N are transmitted, from the transmission expansion port of the first router matrix 106a of the third broadcast router component 106, to the second receiver expansion port 280 over the link 112; and input transport streams 3N+1 through 4N are transmitted, from the transmission expansion port of the first router matrix 108a of the fourth broadcast router component 108, to the third receiver expansion port 282 over the link 114. Finally, input transport streams N+l through 2N, 2N+1 through 3N and 3N+1 through 4N are input, by the first, second and third receiver expansion ports 278, 280 and 282, respectively, the routing engine 144. As previously set forth, the first and second router matrices 102a and 102b are redundant matrices relative to one another. To function in this manner, routing engine 152 of the second router matrix 102b must have the same set of input transport streams as the routing engine 144. Accordingly, in a fashion like that hereinabove described, the selected transport streams output each one of the first selector circuits 138-1 through 138-N are also fed to an input side of the routing engine 152 as well as a transmitting port 284. Similarly, the transport streams fed to the first receiving expansion port 278, the second receiving expansion port 290 and the third receiving expansion port 282 are also fed to a first receiving expansion ports 286, a second receiving expansion port 288 and a third receiving expansion port 290, respectively, of the second router matrix 102b. In a broad sense, the transmitting expansion port 284 of the second router matrix 102b is comprised of a memory subsystem in which the transport streams received from the first selector circuits 138-1 through 138-N of the first broadcast router component 102 are buffered before transfer to plural destinations and a processor subsystem for controlling the transfer of the transport streams received from the selector circuits 138-1 through 138-N to a receiving expansion port of the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108. Conversely, each one of the first, second and third expansion ports 286, 288 and 290 of the second router matrix 102b are, in a broad sense, comprised of a memory subsystem in which the transport streams received from a transmitting expansion port of the first router matrix of another broadcast router component may be buffered before transfer to their final destination and a processor subsystem for controlling the transfer of the transport streams received from the transmitting expansion port of the first router matrix of the other broadcast router component to inputs of the routing engine 152 of the second router matrix 102b of the first broadcast router component 102.

From the first selector circuits 138-1 through 138-N, input transport streams 1 through N are transmitted to the routing engine 152 and the transmission expansion port 284. From the transmission expansion port 284, input transport streams 1 through N are forwarded to the second router matrix 104b of the second broadcast router component 104 over the link 122, to the second router matrix 106b of the third broadcast router 106 over the link 124 and to the second router matrix 108b of the fourth broadcast router 108 over the link 126. In return, input transport streams N+l through 2N are transmitted, from the transmission expansion port of the second router matrix 104b of the second broadcast router component 104, to the third receiver expansion port 290 over the link 122; input transport streams 2N+1 through 3N are transmitted, from the transmission expansion port of the second router matrix 106b of the third broadcast router component 106, to the second receiver expansion port 288 over the link 124; and input transport streams 3N+1 through 4N are transmitted, from the transmission expansion port of the second router matrix 108b of the fourth broadcast router component 108, to the first receiver expansion port 288 over the link 126. From the third, second and first receiver expansion ports 290, 288 and 286, the input transport streams N+l through 2N, 2N+1 through 3N and 3N+1 through 4N are transmitted, by the third, second and first receiver expansion ports 290, 288 and 286, respectively, to the routing engine 154.

Residing within the routing engine 144 of the first router matrix 102a is switching means for assigning any one of the 4N AES streams received as inputs to the routing engine 144 to any one of the M output lines of the routing engine 144. Variously, it is contemplated that the routing engine 144 may be embodied in software, for example, as a series of instructions; hardware, for example, as a series of logic circuits; or a combination thereof. Similarly, residing within the routing engine 152 of the second router matrix 102b is switching means for assigning any one of the 4N input AES streams received as inputs to the routing engine 152 to any one of the M output lines of the routing engine 152. Again, it is contemplated that the routing engine 152 may be variously embodied in software, hardware or a combination thereof. Each one of the 1 through M AES streams output the routing engines 144 and 152 of the first and second routing matrices 102a and 102b, respectively, of the first broadcast router component 102 are propagated to a corresponding one of second selector circuits 160-1 through 160-M. The second selector circuits 160-1 through 160-M collectively determine whether the 1 through M AES streams output the routing engine 144 of the first routing matrix 102a or the 1 through M AES streams output the routing engine 152 of the second routing matrix 102b shall be the output of the first broadcast router component 102. Each one of the second selector circuits 160-1 through 160-M share a common control input (not shown) for selecting whether the AES streams output the routing engine 144 or the AES streams output the routing engine 152 shall be passed by the second selector circuits 160-1 through 160-M.

From the second selector circuits 160-1 through 160-M, the selected AES streams are propagated to a respective one of information duplication circuits 162-1 through 162-M. In turn, the information duplication circuits 162-1 through 162-M pass the received AES streams to either the AES output circuits 164-1 through 164-M or the MADI output circuits 166-1 through 166-M for encoding and output from the first broadcast router component 102. Similarly, if the received information streams were MADI streams, they, too, could be passed to either the AES output circuits 164-1 through 164-M or the MADI output circuits 166-1 through 166-M for encoding and output from the first broadcast router component 102.

Referring next to FIG. 3, the AES output circuits 164-1 through 164-M will now be described in greater detail. FIG. 3 shows the AES output circuit 160-1. The remaining AES output circuits, specifically, the AES output circuits 164-2 through 164-M are similarly configured to the AES output circuit 164-1 and need not be described in greater detail. As may now be seen, the AES output circuit 164-1 includes a transport stream demultiplexer 285 and AES bi-phase encoder circuits 287-1 through 287-M. Input to the transport stream demultiplexer 285 is a transport stream containing 32 decoded output digital audio data streams which conform to the AES-3 standard. The transport stream demultiplexer 285 deconstructs the transport stream and passes each one of the 32 decoded output digital audio data streams to a respective one of the AES bi-phase encoder circuits 287-1 through 287-32.

Continuing to refer to FIG. 3, the AES bi-phase encoder 287-1 forming part of the AES output circuit 164-1 and the process by which the AES bi-phase encoder 287-1 generates a bi-phase encoded serialized stream of digital data will now be described in greater detail. Of course, it should be clearly understood that the AES bi-phase encoders 287-2 through 287-32 function in a similar manner and need not be described in greater detail. As shown in FIG. 3, the AES bi-phase encoder 287-1 is coupled to receive a first decoded AES output digital audio data stream from the transport stream demultiplexer 285. The AES bi-phase encoder 287-1 is also coupled to receive a master clock signal, a sample rate signal and a bit time signal. It should be noted, however, that the bit time signal is carried in the first decoded AES output digital audio data stream and does not, therefore, appear as a discrete input to the AES biphase encoder 287-1.

The bit time input signal provides, in seconds, the length of a frame of the incoming AES serialized output digital audio data stream. Generation and distribution of the master clock signal to the encoding logic 292 is described in greater detail in co-pending U.S. Patent Application Ser. No. 10/ (Atty. Docket No. IU020253) and previously incorporated by reference. For purposes of this disclosure, the bi-phase encoder 292 should be considered to be a clock-demanding component as defined in the aforementioned patent application. Finally, the sample rate input provides the bi-phase encoder 297 with any one of a wide variety of values for the sample rate at which the AES serialized output digital audio data stream is to be encoded.

The process by which the bi-phase encoder 287-1 encodes the AES serialized output digital audio data stream into a bi-phase encoded serialized stream of digital data will now be described in greater detail. The method commences at step 400 and, at step 401, a bit sample rate ("BSR") at which the AES serialized output digital audio data stream is to be encoded, is selected. While the bit sample rate may be expressed in a variety of ways, at this point, it is best expressed in terms of an integral value relative to the time duration of a data bit. For example, a common bit sample rate suitable for selection as the BSR would be the value 20. Such a value would mean that 20 samples would fit within a single data bit having a time duration generally equal to the average bit time for the digital audio data streams. In turn, the bi-phase encoder 287-1 would sample the AES serialized output digital audio data stream at a bit sample rate generally equal to l/20^th of the average bit time for the AES serialized output digital audio data stream.

Continuing on to step 404, a segment of the AES serialized output digital audio data stream having a selected size is selected. In the example described herein, a 64-bit segment of the AES serialized output digital audio data stream output the selector circuit 162-1 is selected by the bi-phase encoder 287-1 for encoding. It should be clearly understood, however, that the selected segment of the AES serialized output digital audio data stream may be of any desired size. The use of 64-bit segments is particularly advantageous if the input digital audio data stream conforms to the AES-3 specification in that an AES-3 digital audio data stream is divided into 64-bit frames of data, each of which is headed by a 4-bit preamble. It should be further understood that, if necessary, the bi-phase encoder 297-1 shall include one or more buffers (not shown) to hold the incoming digital data until selected for encoding. Proceeding on to step 406, an average time ("A") for each bit (hereafter referred to as a

"bit time") of the selected segment is determined by dividing, in binary, the duration (in time) of the selected segment by the number of data bits in the selected segment and dropping any remainder from the result. As previously set forth, the duration of the selected segment is carried by the input digital audio data stream. In the example described herein, the time duration of the selected segment would be divided by 64. The resultant average bit time would have a degree of precision generally equal to log₂64 or 6. In other words, the result would have a 6-bit binary remainder R which could vary from 000000 (0) to 111111 (63).

Continuing on to step 408, the sample rate, as a time value, at which the AES output serialized digital audio data stream is to be encoded is determined. By doing so, the number of samples which will fit within a data bit having a time duration generally equal to the average bit time, determined at step 406, for a data bit is determined. As previously set forth, in a suitable example, it is contemplated that 20 samples will fit within a data bit of the selected segment. At step 410, the method determines whether there is any remainder resulting from the determination at step 406. Any remainder is the excess sample count ("XSC), i.e., the total number of additional samples, to be distributed over the selected data segment. If there is no remainder, the method proceeds to step 412 where a 64-bit encoded data word is constructed such that each bit of the data word has a time duration generally equal to the average bit time and containing twenty samples therein.

If, however, it is determined at step 410 that there was a remainder, the method will instead proceed to step 414 where a 64-bit encoded data word is constructed such that different bits of the data word will have different time durations and contain different number of samples therein. More specifically, the 64-bit encoded word will be constructed such that (64 - R)-bits of the encoded data word will have a time duration generally equal to twenty samples and R-bits of the encoded data word will have an additional sample added, thereby extended the duration of each one of the R-bits to 21 samples. Of course, extending the time duration of R-bits of the 64-bit encoded data word by a single sample is but one way to adjust the duration of the encoded data word such that no time information is lost during the encoding process. Alternately, selected ones of the data bits of the 64-bit encoded data word may be adjusted by durations other than a single sample. Typically, more of the data bits would be selected if the durations were adjusted by durations less than a single sample while less of the data bits would be selected if the durations were adjusted by durations more than a single sample. Finally, as disclosed herein, the R-bits of the 64-bit encoded data word which are selected to have their time duration incremented are evenly distributed throughout the 64- bit data word. For example, if R=8, the time duration of bits-0, 7, 15, 23, 31, 39, 47 and 55 would be incremented. Of course, in evenly distributing the bits selected to have their time duration incremented, a bit other than bit-0 may be selected. Further, the bits selected need not necessarily be evenly distributed throughout the 64-bit encoded data word. For example, the 64-bit encoded data word may instead be front-loaded with the incremented data bits by selecting bits-0, 1, 2, 3, 4, 5, 6 and 7 to have their time duration extended.

After constructing the 64-bit encoded data word such that all bits thereof have the same time duration at step 412 or after constructing the 64-bit encoded data word such that selected bits thereof will have a time duration extended by one sample at step 414, the method proceeds to step 420 where it is determined if there is additional data from the AES serialized output digital audio data stream to be selected for encoded. If there is additional data to be selected for encoding, the method returns to step 404 for further processing in the manner previously described. If, however, it is determined at step 420 that there is no additional data from the AES serialized output digital audio data stream to be selected for encoding, the method ends at step 422.

Thus, there has been disclosed and illustrated herein a serial digital audio data stream encoder capable of encoding data at various sample rates that neither requires the use of a PLL nor the need to change an incoming master clock. Of course, while preferred embodiments of this invention have been shown and described herein, various modifications and other changes can be made by one skilled in the art to which the invention pertains without departing from the spirit or teaching of this invention. Accordingly, the scope of protection is not limited to the embodiments described herein, but is only limited by the claims that follow.

Claims

1. A method of encoding, at a selected sample rate, a digital serial audio data stream comprised of a plurality of data bits, comprising: selecting a sample rate (401); selecting a segment from said digital audio data stream (404), said selected segment comprised of a plurality of data bits; and constructing a segment of an encoded serial digital audio data stream from said selected segment of said at least one digital audio data stream, said constructed segment having a sampling count generally equal to the product of the total number of data bits in said selected segment, an average bit time for said selected segment and said selected sample rate

(412, 414); wherein said segment of said encoded serial digital audio data stream is constructed such that each data bit thereof has a respective time duration determined which is based upon the distribution of said sampling count over said constructed segment.

2. The method of claim 1, wherein said sampling count is integrally distributed over said constructed segment (412, 414).

3. The method of claim 2, wherein said sampling count is unevenly distributed over said constructed segment (412, 414).

4. The method of claim 2, wherein said sampling count is evenly distributed over said constructed segment (412, 414).

5. The method of claim 4, wherein said sampling count is evenly distributed over said constructed segment such that each data bit of said constructed segment contains an equal number of samples (412).

6. The method of claim 4, wherein said sampling count is evenly distributed over said constructed segment such that at least one data bit of said constructed segment contains N samples and at least one data bit of said constructed segment contains N+l samples (414).

7. The method of claim 1, wherein selecting a sample rate further comprises: determining an average bit time for said selected segment of said at least one digital audio data stream (406); and selecting a sample rate such that the product of said sample rate and an integral value is said average bit time (408).

8. The method of claim 7, wherein said integral value is at least twenty.

9. The method of claim 8, wherein said sampling count is evenly distributed over said constructed segment (412, 414).

10. The method of claim 9, wherein said sampling count is evenly distributed over said constructed segment such that at least one data bit of said constructed segment contains N samples and at least one data bit of said constructed segment contains N+l samples (414).

11. The method of claim 10, wherein said sampling count is evenly distributed over said constructed segment such that at least one data bit of said constructed segment contains 20 samples and at least one data bit of said constructed segment contains 21 samples (414).

12. A method of encoding digital audio data into a digital audio data stream, comprising: determining an average bit time ("A") for a N-bit frame of digital audio data to be encoded (406); determining an excess sample count ("X"), 0<X<N, for said N-bit frame of digital audio data (408); and constructing an N-bit encoded frame of a digital audio data stream from said N-bit frame of digital audio data, said average bit time, said excess bit count and a frame sampling rate ("FSR") for said digital audio data stream (412, 414); wherein said frame sampling rate is an integral factor of said average bit time.

13. The method of claim 12, wherein X is equal to zero and wherein each one of said N- bits of said encoded frame has the same time duration (410, 412).

14. The method of claim 12, wherein X is between 0 and N and wherein X bits of said N- bit encoded frame have a time duration greater than a time duration of the remaining N-X bits of said N-bit encoded frame (410, 414).

15. The method of claim 14, wherein said time duration of each one of said N-X bits of said N-bit encoded frame is equal to A (414).

16. The method of claim 15, wherein said time duration of each one of said X bits of said

N-bit encoded frame is equal to [ESR + 1] (414).

FSR

17. The method of claim 16, wherein said average bit time has a degree of precision generally equal to log₂N (408).

18. The method of claim 17, wherein said excess samples are evenly distributed throughout said N-bit encoded frame (414).