WO2003098819A1

WO2003098819A1 - A transmitter

Info

Publication number: WO2003098819A1
Application number: PCT/AU2003/000581
Authority: WO
Inventors: Dale John Butler
Original assignee: Dcr Global Limited
Priority date: 2002-05-15
Filing date: 2003-05-15
Publication date: 2003-11-27

Abstract

A transmitter, for transmitting RF signals, includes a plurality of switches arranged to apply one of a plurality of voltage sources to an output of the transmitter, and timing control to control the plurality of switches. The timing control is configured to selectively control the switches such that a desired modulation scheme is applied and a stepwise approximation of the desired output signal is created. The transmitter can be used in mobile telephones to conserve power.

Description

A TRANSMITTER

Field of the Invention

The present invention relates to a transmitter for transmitting Radio Frequency (RF) signals.

Background of the Invention

Currently, transmitters for transmitting RF signals tend to include several discrete components. In many applications, this tends to increase price, complexity and size, and also has an adverse effect on reliability. In certain fields, particularly cellular telephony, commercial pressure to drive down price and size particularly are great.

Figure 1 shows a top level view of the main elements which make up a transmitter 10. The baseband circuitry which generates data for transmission is represented by 20. In a typical cellular telephone application, the baseband circuitry accepts analog voice data, converts it into digital form, encodes and encrypts it before passing the data onto modulator 30. Modulator 30 has another input produced by synthesiser 25. Synthesiser 25 generates a carrier signal which is modulated by the digital signal from the baseband block 20. The signal produced by the modulator is thus at the correct output frequency, but is not generally at a suitable power level for transmission.

Amplifier 35 therefore accepts the modulated signal from modulator 30 and amplifies it to the correct output level. This signal is next filtered by filter 40 before being transmitted via antenna 45.

Also shown is the path 50 of the receive circuitry which is included in a cellular telephone but not shown here. A particular problem with transmitters in general, but particularly in cellular telephones, is the non-linearity of the amplifier. The effects of non-linearities in the amplifier response tend to introduce spurious signals in the output of the amplifier. These spurious signals can cause interference to other wanted signals near by. The regulations governing operation of cellular telephones mandate certain limits for spurious transmissions, and it is therefore necessary to take steps to make allowance for the non-linearity of the transmitter.

To achieve true linearity, the amplifier must be biased to operate as a Class-A amplifier. However, in practice, such an amplifier arrangement consumes too much power for it to be a practicable solution in a battery powered device.

Cellular telephones therefore tend to use amplifier configurations which are inherently non-linear, and additionally include extra circuitry to compensate for the non-linearity. This extra circuitry can include pre-distortion, feed-forward or feedback circuitry. All of these solutions add complexity to the transmitter and can introduce other problems of their own.

Accordingly it is desired to obviate or alleviate the above, or at least provide a useful alternative.

Summary of the Invention

In accordance with the present invention there is provided a transmitter for transmitting RF signals including: a plurality of switches arranged to apply one of a plurality of voltage sources to an output of the transmitter; timing control means to control said plurality of switches; wherein the timing control means is configured to selectively control said plurality of switches such that a desired modulation scheme is applied and a stepwise approximation of the desired output signal is created. Preferably, the timing control means includes a Delay Locked Loop (DLL) to create a plurality of time delayed timing control signals from a reference clock signal input signal.

In order to minimise the number of reference voltage signals required, the transmitter preferably includes bridge circuitry to invert the output signal as required.

Preferably, the transmitter further includes a filter at its output for reconstructing the stepwise approximation of the output signal. The filter may suitably be a low pass filter.

The voltage sources may preferably be provided in the ratio of 100%:83%:54%. Other ratios may be possible depending on the number of voltage sources provided and the exact requirements of the output signal.

The voltage sources may be arranged to be kept at defined levels, or, if non- constant envelop modulation schemes are to be implemented, or burst to burst power control is used, then the individual levels may be variable, whilst maintaining the ratio between the levels.

The frequency of the output signal is preferably controlled by changing the frequency of a reference clock signal. The reference clock signal may be directly modulated if phase modulation of the output signal is required.

The transmitter may preferably be implemented using CMOS VLSI technology as an ASIC.

Preferably, the plurality of voltage sources includes a single primary winding of a transformer coupled to a plurality of differently configured secondary windings of the transformer, each secondary winding being selectively connectable to a single reference voltage, such that temporary connection of the reference voltage to a particular secondary winding induces a particular voltage in the primary winding. Use of such a configuration reduces the number of different voltage sources required. In certain preferred embodiments, a single reference voltage may be supplied, with the different voltage levels used to create the stepwise approximation of the waveform being created by use of the different secondary transformer windings.

Preferably, individual timing control signals are applied to ones of the plurality of switches via respective intermediate transformers.

Preferably, a primary winding of each transformer is arranged to receive a timing control signal and a secondary winding of each transformer is arranged to control a respective switch.

In the above case, preferably, the switch is a transistor and the secondary winding of the transformer is arranged to be connected to the base of the transistor.

The present invention also provides a method of creating an RF signal waveform for direct transmission, including the steps of: providing a plurality of reference voltage sources; and selectively operating ones of a plurality of switches to apply one of said plurality of reference voltage sources to an output of said transmitter such that a signal at said output is a stepwise approximation of a desired output signal.

Furthermore, the present invention also provides a transmitter for transmitting RF signals including: a plurality of switches arranged to selectively connect one of a plurality of secondary transformer windings to a voltage source; a primary transformer winding arranged to be coupled to said plurality of secondary transformer windings and connected to an output of the transmitter; and timing control means configured to selectively control said plurality of switches such that a desired modulation scheme is applied and a stepwise approximation of a desired output signal is generated at said output.

Preferably, the method further includes the step of filtering the waveform before transmission.

Preferably, the method further includes the step of selectively operating ones of the plurality of switches includes the step of generating a plurality of time delayed copies of a reference clock input signal, and using selected ones of said plurality of time delayed copies to control ones of said plurality of switches.

Different modulation schemes may be implemented within the method by altering the switching patterns and control signals used to switch the plurality of switches on and off.

Embodiments of the present invention allow the direct digital creation of modulated signals for transmission at signal levels which allow for direct output without the need for further amplification stages. Due to the digital nature of the signal creation, non-linearities introduced by power amplifiers of prior art transmitters are not an issue.

Embodiments of the present invention may be fabricated using CMOS ASIC technology, resulting in the majority of the circuitry necessary to construct a portable telephone being disposed within a single device.

Embodiments of the invention are expected to find particular utility in the portable telephone market where present techniques for transmitting RF signals involve many problems. Embodiments of the present invention at least ameliorate problems of non-linearity and excessive power consumption experienced with present solutions.

Embodiments of the invention also yield efficiency improvements over known transmitters. Since the output signal is created by switching in and out defined voltage sources, little power is wasted, and as such, embodiments of the invention offer efficiency improvements which are desirable in battery operated equipment.

Embodiments of the present invention also eliminate the need for a resonant tank circuit, because the stepped waveform that is produced includes sufficient information to allow the use of a simple low pass filter to re-create the desired output waveform.

Brief Description of the Drawings

Preferred embodiments of the present invention are hereinafter described, by way of example only, with reference to the appended drawings in which:

Figure 1 shows a typical transmitter configuration known in the prior art;

Figure 2 shows a transmitter circuit according to an embodiment of the invention;

Figures 3a-3e shows the features of a stepwise approximation to a sinewave for transmission;

Figure 4 shows the creation of a complete stepwise approximation of a sinewave including positive and negative half cycles;

Figure 5 shows a sinewave created by low-pass filtering the waveform of Figure 4; Figure 6 shows the operation of a Delay Locked Loop (DLL) used to generate timing signals for operating the circuit of Figure 2;

Figure 7 shows a circuit arrangement according to a further embodiment of the invention;

Figure 8 shows how the input reference voltages may be altered to produce an output signal of varying magnitude;

Figure 9 shows how the transmitter may be configured to directly receive a modulating signal;

Figure 10 shows an alternative embodiment having a different arrangement of switches for producing an output waveform;

Figure 11 shows a further embodiment employing an alternative means of controlling the switches;

Figure 12 shows how a transformer may be implemented using ASIC technology;

Figure 13 shows the timing control signals used to control the circuit of Figure 11 ;

Figure 14 shows a transmitter circuit according to an embodiment of the invention;

Figures 15a-c relate to the embodiment shown in Figure 14 and show the pulses induced in a primary winding in response to pulses created in the secondary windings;

Figure 16 shows the creation of a complete stepwise approximation of a sinewave. including positive and negative half cycles, and the resultant sinewave; and Figure 17 shows an embodiment of the invention utilising only two different voltage sources to create a desired output waveform.

Detailed Description of the Preferred Embodiments Figure 2 shows a transmitter according to an embodiment of the invention. The basic principle lying behind this circuit relies on switching a plurality of discrete d.c. voltage levels in a controlled manner to create a desired output waveform.

The circuit in Figure 2 utilises three distinct voltages which are connected at points 100, 105, 110. The voltages may be generated by standard circuits including voltage regulators or in a preferred embodiment, switched mode power supplies.

The absolute levels of the input dc voltages depend on the number of levels being used as well as on the device technology employed to implement the transmitter. In the present embodiment, using three levels, suitable values for the three levels are shown in Figure 3.

Figure 3 shows how a histogram-like series of voltage pulses 210, 220, 230 may be made to closely approximate a sine wave 200. It will be appreciated by the skilled addressee that the three levels used to describe this embodiment are exemplary only, and that a different number may be used depending on the requirements of the particular system in which the circuit is employed.

In the example waveform shown in Figure 3a, three discrete pulses are used to approximate a sine wave. The three pulses are symmetrical about a line formed at the 90° point of the sine wave. The highest magnitude pulse 210 is designated as 100% amplitude, and has a pulse width corresponding to 70-110° of the sine wave. The second pulse 220 has 83% of the magnitude of the first pulse 210 and has a pulse width corresponding to 50-130° of the sine wave. The third pulse has 54% of the magnitude of the first pulse 210 and has a pulse width corresponding to 30-150° of the sine wave. The histogram like shape of the three pulses, when filtered, produces a half sine wave as shown. The pulses 210, 220 and 230 are produced by switching the three voltage inputs 100, 105 and 110 of the circuit shown in Figure 1. Input 100 is the highest level input and produces the pulse 210 when switched by switch 115. Input 105 has a magnitude of 83% of input 100 and produces pulse 220 when switched by switch 120. Input 110 has a magnitude of 54% of input 100 and produces pulse 230 when switched by switch 125. The switches are implemented as CMOS switches and have a switching time of a few picoseconds. The diodes 130 and 135 immediately following switches 120 and 125 respectively allow for faster switching times. In effect, when switch 115 is closed, diodes 130 and 135 are reverse biased and no current will flow from 100 to 105 or 110, which are at lower potentials. In this way, the synchronism of the switches 115, 120 and 125 is not critical as the diodes act to protect the lower potentials from the higher potentials. Also, if Schottky diodes are used, their timing characteristics are superior to the CMOS switches.

Figure 3b shows just the histogram-like series of pulses which combine to create the desired output waveform. Figure 3c shows pulse 210 in isolation. The pulse 210 is created by the closure of switch 115.

Figure 3d shows that pulse 220 actually includes two discrete pulses 222, 224 positioned immediately adjacent to pulse 210. These pulses are created when switch 115 is opened and switch 120 is closed

Figure 3e shows that pulse 230 actually includes two discrete pulses 232 and 234 positioned immediately adjacent to pulses 222 and 224. These pulses are created when switch 125 is closed and switches 115 and 120 are open.

By operating the switches 115, 120 and 125 as described, the histogram waveform may be generated. However, by using three positive voltages as described, it is only possible to directly generate one half of a sine wave. In order to indirectly generate the negative half-cycle, the bridge circuit including switches 140, 145, 150 and 155 is required. In the bridge circuit, switches 140 and 155 are operated simultaneously, and switches 145 and 150 operate likewise, as shown by the dotted lines in Figure 2. The pairs of switches operate in alternate phase, meaning that when one pair is open, the other pair is closed.

To produce a positive half-cycle, switches 140 and 155 are closed, and to produce a negative half-cycle, switches 145 and 150 are closed. Figure 4 shows how the histogram like pulses are inverted in the negative half cycle of the sine wave.

The two outputs from the bridge circuit are taken from the mid points between switches 140, 145 and 150, 155. The outputs are fed into a low-pass or reconstruction filter 160. This acts to allow through only signals having a frequency lower than a defined cut off frequency. This allows the sharp edges of the step- wise approximation of the sine wave to be suppressed, while allowing the fundamental sine wave signal to pass and be output as waveform 165. Figure 5 shows the waveform of Figure 4 as a pure sine wave 200 after passing through filter 160.

By controlling the switches 115, 120, 125 and switch pairs 140, 155 and 145, 150, it is therefore possible to create an arbitrary waveform output signal 165. In the simplest non-square wave case, a sine wave may be constructed as described, but by altering the switch timing, it is possible to create waveforms of greater complexity. This effectively allows the circuit to be used directly to create modulated signals according to one or more modulation schemes.

In an alternative embodiment, where the requirements of signal spectral purity are more lenient, it has been found that creating an output waveform from only two voltage sources is possible. In this embodiment, the high and low level voltage references are defined by the relationship: V|₀ = sin(54) x V_hi_gh = 0.81 x V_high. The stepwise approximation is created from 3 pulses: V|_0W is active from 36° to 72°, and from 108° to144°, and V_hig_h is active from 72° to 108° of the first half cycle of the sine wave. There is no active voltage at other times. The three-pulse histogram thus created is inverted every half-cycle as previously shown to produce a complete sine wave.

Clearly, using more voltage levels, switched more frequently, results in a closer approximation to a sine wave. The choice of voltage levels used depends largely on the spectral purity required of the output signal.

To create a waveform having a fundamental frequency of X, the switches 115, 120, 125 operate at a frequency of 2X. This enables signals in the UHF range to be generated, making this type of transmitter well suited to the cellular telephony field.

The timing of the signals used to operate the switches 115, 120, 125 can be controlled in a number of different ways, but in embodiments where the output signal has a frequency of e.g. 2GHz, the period of a single cycle of the output waveform is 500picoseconds. In such cases, where the frequency of the output signal is in the UHF region, the resolution of the timing signals is very fine.

A technology known as Delay Locked Loop (DLL) provides a solution to the problem of generating timing control signals of such fine resolution. DLL techniques are currently used to alleviate problems with clock skew in high speed circuits, but the basic technique allows the creation of many phase delayed variants of an input signal to be generated. Figure 6 shows some of the outputs which may be produced by a DLL device when a simple clock signal is input. Each output signal is a phase delayed version of the input clock signal. In this particular example, only eighteen different outputs are shown giving phase delayed signals ranging from 10° to 180°. In practice, depending on the exact configuration of the DLL circuit, it is possible to devise other different outputs offering a much greater choice of phase delays.

Figure 6 shows how the various phase delayed signals may be used to create the control signals opening and closing the switches 115, 120, 125. The vertical dotted lines indicate the signal edges which may be used to create the various timing control signals. For instance, the rising edge of the signal delayed by 30° may be used to close switch 125 and thus generate pulse 230. Other rising edges, or indeed, falling edges, may be used as shown in Figure 6.

Additionally, the undelayed clock signal may be used to control the switch pairs 140, 155 and 145, 150 of the bridge circuit, and so produce the inverted negative half cycle of the output waveform.

The entire transmitter circuit including switches, bridge circuit and DLL can be implemented as a single device, and indeed, to enhance miniaturisation and size, it may be possible to implement the vast majority of a cellular telephone on a single chip. In this way, all digital and most analogue circuitry can be integrated into a single device, with ancillary components such as microphone, speaker, keypad, display and battery interfacing to the one device.

The transmitter can be implemented as a CMOS Application Specific Integrated Circuit (ASIC). The power output available from such a CMOS ASIC configuration does not require a separate amplification stage, as the output of the ASIC is able to directly drive an antenna, and thus transmit the created waveform 165. Removing the need for extra amplification stages following the transmitter, solves, or at least alleviates, the problems introduced by the non-linearities discussed previously in relation to prior art amplifiers.

Current GSM handheld devices are specified to transmit at a maximum output power of 2W. Such an output power may be generated in a CMOS ASIC by running the final stage components and tracks in parallel such that each of the parallel stages carries only a fraction of the current required to produce the output waveform. In this way, the output of the ASIC may be passed to a reconstruction filter and then on the antenna for transmission.

Individual transistors and tracking within an ASIC are not sufficiently robust to handle the power required for direct transmission, but it is possible to configure the ASIC to use parallel tracks and components such that the higher current flows can be safely supported.

A further embodiment of the invention which, it is believed, is better suited to implementation in a CMOS ASIC is presented in Figure 7. In this configuration, the bridge circuit 140, 145, 150, 155 of Figure 2 is combined with the individual switches 115, 120, 125 connected to the different voltage sources. In this way, each of the three voltage sources 100, 105, 110 is connected to its own bridge, and is enabled by operation of selective ones of the plurality of transistor switches 400 - 455.

The table below shows which pulses (referring to Figure 4) are produced by the operation of which switches.

It follows from this, that the four switches associated with each voltage input e.g. 405, 410, 430, 435 act in much the same way as the bridge described in relation to Figure 2. To simplify the switching arrangement, switches 430, 440, 450 operate simultaneously, as do switches 435, 445, 455. In this way, each group of three switches is closed for one half-cycle of the resultant sine wave and acts to alternately invert the voltage levels provided from inputs 100, 105, 110. The control of the voltage levels and their connection to the low pass filter 480 is achieved through use of switches 400 - 425 as shown in the table above.

Referring again to Figure 4, to generate the positive voltage pulses 210, 220, 230, switches 430, 440, 450 are closed. These switches remain closed until it is desired to create negative voltage pulses 260, 270, 280, when switches 430, 440, 450 are opened and switches 435, 445, 455 are closed.

To create pulse 230, switch 425 is closed. The next pulse 220 is created by closing switch 415. It is not necessary to open switch 425 as diode 475 acts to stop current flowing from voltage source 105 to source 110 which is at a lower potential.

The next pulse 210 is created by closing switch 405. Again, it is not necessary to open either of switches 415 or 425 as diodes 475 and 465 act to prevent current flow from the higher to the lower potential.

To create the downward trajectory of the second quadrant of the sine wave, the above switching pattern is reversed i.e switches 405, 415 and 425 are opened in that order.

To create pulse 280, the first negative pulse in the second half-cycle of the resultant sine wave 200, switch 420 is closed. A similar pattern of switching to that described above then follows with switches 410 and 400 being closed sequentially to generate the further pulses. Switches 400, 410 and 420 are then opened in sequence to generate the positive trajectory of the fourth quadrant of the resultant sine wave.

Each switch therefore makes only a single on-off cycle per half cycle of the resultant sinewave.

With certain switch technologies, diodes 460, 465, 470, 475 may not be required, and their inclusion in the circuit of Figure 7 is exemplary only.

The configuration described is useful for constant envelope modulation schemes such as GMSK used in GSM as the reference input voltages 100, 105, 110 are fixed, and as such can be provided simply and with high accuracy. For modulation systems which do not utilise constant envelope techniques, such as amplitude modulation and various forms of single sideband modulation, it is possible to vary the input voltage references 100, 105, 110 such that the resultant output signal has a time varying envelope.

In order to ensure output spectral purity, it is desirable to ensure that the defined ratios between the three input voltages are maintained while the absolute levels are varied. In the example used above, therefore, even though the absolute levels of the three voltage inputs would need to change in order to vary the amplitude envelope of the output signal, the relative levels would be preserved.

This scenario is shown in Figure 8. The three reference voltage inputs 105, 110 and 115 are shown as time varying d.c. signals. The absolute difference between the three signals is shown to alter over time, but the ratios defining the relationships between the signals do not alter. In this way, the spectral purity of the resultant signal may be retained, even though the absolute level of the output signal is changing over time. To generate time varying voltage reference signals as described, switched mode power supplies may be used which are configured to retain a defined ratio between the three signals generated.

In this way, it possible to generate non-constant envelope modulation signals as described. It is also possible implement power control of the transmit signal, i.e. alter the transmission power over a longer period of time. For instance the GSM standard requires transmit power to alter from burst to burst.

Figure 9 shows an example of how the circuit of Figure 2 may be used to produce a directly modulated signal suitable for transmission.

The fundamental structure of the circuit of Figure 9 is similar to that shown in Figure 2. Like reference numerals refer to like parts. The additional elements allow a digital data stream 315 to be used to modulate the clock signal 310 by XORing 320 them together. This simple modulation scheme allows the signal 165 to be demodulated at the receiver using a similar XOR gate 320.

Paired drivers 340, 355 and 345, 350 are used to control the switches 140 - 155 of the bridge circuit. Inverter 330 ensures that the paired drivers always operate in anti-phase.

The switches 115, 120, 125 are controlled as described previously by timing signals generated by a DLL (not shown).

The clock signal 310 controls the frequency of the transmitted signal, and can be adjusted as required to ensure that the output signal is set accordingly.

Sub-cycle phase variation can be created by directly modulating the DLL in either the analogue or digital domains. The digital clock frequency input to the DLL can be varied to provide phase or frequency modulation. It is also possible to apply modulation to the analogue section of the DLL.

The amplitude of the resultant signal 165 can also be altered by simultaneously altering the levels of the three input voltages 100, 105, 110 as described previously in connection with Figure 8.

Different modulation schemes can be implemented using different control means whilst still operating according to the fundamental principles described previously.

In the light of the foregoing description, it will be clear to the skilled addressee that various modifications may be made within the scope of the invention.

For instance, different switching arrangements may be envisaged which are capable of sequentially selecting one of a series of different voltage sources so as to create a desired output waveform as previously described. Figure 10 shows a configuration of switches which, it is believed, offers a suitable arrangement for implementation in a VLSI form. This arrangement minimises the use vertically cascaded devices and also removes the need for the series diodes described previously. This arrangement is particularly suitable for use in transmitters operating in the HF to UHF frequency bands.

The circuit configuration shown in Figure 10 is similar to that shown in Figure 7. Like numerals refer to like elements. The essential difference is that switches 430, 440 and 450 of Figure 7, which operate in unison, have been replaced with a single switch 490. Likewise, switches 435, 445 and 455 have been replaced by a single switch 495. Port 500 is connected to DC ground, as in Figure 7.

Figure 11 shows a further preferred embodiment 500 of the present invention. The basic structure of the circuit resembles the circuit shown in Figure 7. Three input voltage sources 510, 520, 530 are provided. Each of the voltage sources is connected to the collectors of a pair of NPN transistors 541 & 543, 545 & 547, 549 & 551. The emitters of one of each pair of transistors are then connected to the collector of transistor 560. The emitters of the other of each pair of transistors are connected to the collector of transistor 565. Connected to the base of each transistor 541 , 543, 545, 547, 549, 551 is the secondary winding of a respective transformer 540, 542, 544, 546, 548, 550.

The primary winding of each of the transformers is driven according to a scheme illustrated in Figure 13, which shows a series of eight pulsed waveforms, the first six of which are applied to the primary windings of the transformer associated with the transistor whose reference is given. Transformer action ensures that the pulses applied to the primary windings induce similar pulses in the secondary windings, thus causing the respective transistors to switch in accordance with the pulses. Figure 13 also shows a representation of the output 575.

Figure 13 also shows the timing which allows transistors 560 and 565 to act as a bridge to invert the polarity of the output signal for successive half-cycles of the output sine wave 575. The base drive signals for transistors 560 and 565 are arranged to operate in anti-phase such that when one of the transistors is 'on', the other is Off.

The timing of the pulses applied to the primary windings of the respective transformers, and hence, used to control the base switching of the identified transistors is shown. For example, the two pulses applied to transformer 540, and hence to the base of transistor 541 result in the two outer pulses of the first half- cycle of the output waveform 575. The magnitude of the pulses is determined by the voltage level 530 applied to the collector of transistor 541. It can similarly be seen how the other transistors are switched to create the output waveform 575.

The timing signals may be created, as before, using a DLL. The voltage levels 510, 520 and 530 used may be arranged in the same or similar proportions as used in previous embodiments of the invention. For instance, in the present embodiment, voltage source 510 may be 3.0V, 520 may be 2.45V and 530 may be 1.64V. The absolute and relative levels of these voltage sources may be adjusted in order to achieve a desired output waveform.

The transformers are provided to drive the bases of the transformers as they effectively act as a current source if they are configured with a suitably high turns ratio. This configuration ensures that the transistors remain in, or close to, saturation and do not operate as emitter followers. This has the effect of transferring maximum output power from the transmitter.

The transformers may be implemented in ASIC format according to known techniques and methodologies. Figure 12 illustrates a known technique for implementing a transformer 600 at ASIC level. Two interwound, generally spiral shaped tracks 610, 620 are disposed on a layer of the ASIC. One track 610 is designated as a primary winding, and the other track 620 as a secondary winding. The relative coupling between the two windings may be controlled by altering any or all of the track width, separation, track length, and substrate material. In multi- layer ASICs, it may be possible to dispose windings on different layers. This is particularly useful in embodiments of the present invention where more than one secondary winding is required.

Figure 14 shows a transmitter according to a further embodiment of the invention. The basic principle lying behind this circuit relies on selectively switching into circuit one of a plurality of transformers windings to create a desired output waveform.

In this way, only a single primary voltage source, V, is required and the secondary voltage sources are created according to the turns ratios of the secondary transformer windings 705, 701 , 715. In effect, switching into circuit one of the secondary windings induces a different voltage pulse in the primary winding 700. As such, each secondary winding may be considered as a different voltage source.

The circuit in Figure 14 utilises a transformer having a single primary winding 700 and three secondary windings 705, 710 and 715. The secondary windings are centre tapped, and applied between the common centre tap 730 and a common reference point 735 (which may conveniently be connected to a ground potential) is a d.c. voltage V. The voltage V may suitable be obtained from a voltage regulator or other stable voltage source.

Connecting each of the secondary windings to the common ground potential 735 is a pair of switches : S1 & S6; S2 & S5; and S3 and S4 respectively. Selective temporary closure of each switch causes a voltage pulse of magnitude V to be generated in the secondary winding attached to said switch. Since each secondary winding of the transformer has a different effective turns ratio with respect to the primary winding 700, a corresponding voltage pulse is induced in the primary winding by transformer action. The magnitude of the induced pulse in the primary winding 700 is governed by the known transformer ratio, where this is :

Vinduced = N_s/Np . V

where Ns/Np is the turns ratio of the selected transformer as determined by closure of one of the switches S1 to S6.

The absolute level of the input dc voltage V depends on the device technology employed to implement the transmitter.

The choice of the transformer ratios depends on the desired output format and the number of secondary transformer windings used. In the present embodiment, the transformer windings are configured such that they are able to produce respective voltage pulses in the primary winding having a ratio of 100%:83%"54%.

Figures 15a-c show how a histogram-like series of voltage pulses 740, 745, 750, 755, 760, 765, 770, 775, 780 and 785 may be made to closely approximate a sine wave 300 as shown in Figure 16. It will be appreciated by the skilled addressee that the three levels used to describe this embodiment are exemplary only, and that a different number may be used depending on the requirements of the particular system in which the circuit is employed.

In the example waveforms shown in Figures 15a-c, a number of discrete pulses are used to produce an approximation 795 of a sine wave 790. The pulses in each of Figures 15a-c are of different magnitudes, formed, as they are, as the result of selecting different secondary transformer windings. The pulses in each of Figures 15a-c are also of different time durations, the control of which will be described shortly.

The highest magnitude pulses 740, 745 are designated as 100% amplitude, and have a pulse width corresponding to 70-110° and 250-290° respectively of the sine wave. The first pulse 740 is produced by the temporary closure of switch S3. The second pulse 745 is produced by the temporary closure of switch S4, and in fact is of an opposite polarity to that shown in Figure 16. The opposite polarity is due to the fact that the sections of secondary winding 115 selected by the closure of switch S3 or S4 are of mutually opposite senses. This fact allow both positive and negative going pulses to be created using the circuit of Figure 14.

The pulses of Figure 15b have 83% of the magnitude of the pulses of Figure 15a. Pulses 750 and 755 are created by the temporary closure of switch S2, and pulses 220 and 225 are created by the temporary closure of switch S5. As before with pulse 745, pulses 760 and 765 are actually negative going pulses produced by selecting the opposite half of winding 710 to the half that produces pulses 750 and 755. The smaller magnitude of these pulses is due to a different transformer ratio than is used for producing the pulses of Figure 15a. The pulse widths of pulses 750, 755, 760 and 765 are equivalent to sections 50-70°, 110-130°, 230-250° and 290-310° respectively of the sine wave.

The pulses of Figure 15c have a magnitude of 54% of the magnitude of the pulses of Figure 3a. Pulses 770 and 775 are produced by the temporary closure of switch S1 , and pulses 780 and 785 are produced by the temporary closure of switch S6. As before, pulses 780 and 785 are actually negative going pulses produced by selecting the opposite half of winding 705 to the half that produces pulses 770 and 775. The smaller magnitude of these pulses is due to a different transformer ratio than is used for producing the pulses of either Figure 15a or 15b. The pulse widths of pulses 770, 775, 780 and 785 are equivalent to sections 0-50°, 130-180°, 180- 230° and 310-360° respectively.

The pulses are produced so that there is no overlap between any of them, and the result of their production is to create at the output of the transformer primary winding 700 a step-wise approximation 795 to a sine wave 790. This is shown in Figure 16. Figure 16 also shows how each of the individual pulses of Figures 15a- c contribute to the stepwise approximation 795.

The approximation 795, when filtered by a low pass filter 720, results in a sine wave 790 which is suitable for direct transmission.

The switches S1 to S6 are implemented as CMOS transistors and have a switching time of a few picoseconds.

By controlling the switches S1 to S6 it is possible to create an arbitrary waveform output signal. In the simplest, non-square wave case, a sine wave may be constructed as described, but by altering the switch timing, it is possible to create waveforms of greater complexity. This effectively allows the circuit to be used directly to create modulated signals according to one or more modulation schemes.

To create a waveform having a fundamental frequency of X, the S1 to S6 operate at a frequency of 2X. This enables signals in the UHF range to be generated, making this type of transmitter well suited to the cellular telephony field.

The timing of the signals used to operate the switches S1 to S6 can be controlled in a number of different ways, but in embodiments where the output signal has a frequency of e.g. 2GHz, the period of a single cycle of the output waveform is 500picoseconds. In such cases, where the frequency of the output signal is in the UHF region, the resolution of the timing signals is very fine.

A Delay Locked Loop (DLL) provides a solution to the problem of generating timing control signals of such fine resolution. The operation of the DLL has previously been described in relation to a different embodiment of the invention, and reference to the earlier explanation is invited.

Figure 6 shows how the various phase delayed signals may be used to create the control signals opening and closing the switches S1 to S6. The vertical dotted lines indicate the signal edges which may be used to create the various timing control signals. For instance, the rising edge of the signal delayed by 70° may be used to close switch S3 and thus generate pulse 740. Other rising edges, or indeed, falling edges, may be used as shown in Figure 6.

The entire transmitter circuit including switches and DLL can be implemented as a single device, and indeed, to enhance miniaturisation and size, it may be possible to implement the vast majority of a cellular telephone on a single chip. In this way, all digital and most analogue circuitry can be integrated into a single device, with ancillary components such as microphone, speaker, keypad, display and battery interfacing to the one device.

The transmitter can be implemented as a CMOS Application Specific Integrated Circuit (ASIC). The power output available from such a CMOS ASIC configuration does not require a separate amplification stage, as the output of the ASIC is able to directly drive an antenna, and thus transmit the created waveform 790. Removing the need for extra amplification stages following the transmitter, solves, or at least alleviates, the problems introduced by the non-linearities discussed previously in relation to prior art amplifiers.

The transformer windings 700, 705, 710, 715 may be implemented in ASIC format according to known techniques and methodologies as have been described previously with reference to Figure 12.

The configuration described is useful for constant envelope modulation schemes such as GMSK used in GSM as the reference input voltages V is fixed, and as such can be provided simply and with high accuracy. For modulation systems which do not utilise constant envelope techniques, such as amplitude modulation and various forms of single sideband modulation, it is possible to vary the input voltage reference V such that the resultant output signal has a time varying envelope.

In order to ensure output spectral purity, it is desirable to ensure that the defined ratios between the levels of pulses produced are maintained while the absolute levels are varied. In the example used above, therefore, even though the absolute levels of the voltage pulses would need to change in order to vary the amplitude envelope of the output signal, the relative levels would be preserved.

To generate a time varying voltage reference V as described, a switched mode power supply may be used. This is able to generate stable but varying voltage levels as needed.

In this way, it possible to generate non-constant envelope modulation signals as described. It is also possible to implement power control of the transmit signal, i.e. alter the transmission power over a longer period of time. For instance the GSM standard requires transmit power to alter from burst to burst.

Transmitters according to one of the various embodiments described may be used in a variety of applications which require an RF transmitter. Particular applications include, but are not limited to, cellular telephony, marine telephony, air-band transmitters, broadcast radio transmitters and RADAR systems. The transmitter has been described particularly in relation to cellular telephony, but it will be apparent to the skilled addressee that this context is exemplary only, and other fields may benefit from use of the transmitter.

The present invention has been illustrated by several different embodiments. The person skilled in the art will realise that one or more features from each embodiment may be combined with one or more features from other embodiments to achieve the intended effect of the invention. The embodiments are therefore illustrative only, and are not intended to limit the scope of the invention which is to be determined by the appended claims only.

In particular, embodiments of the present invention have been described which make use of three different voltage sources to create a desired output waveform. Clearly, the more different voltage levels that are used, the closer is the approximation to the ideal. However, embodiments of the invention are possible using only two different voltage levels. The particular performance of such embodiments may well make them useful in a variety of different applications, and they are found to operate particularly well at higher frequencies.

Figure 17 illustrates an embodiment of the invention which utilises only two voltages V1 and V2 in order to create a desired output waveform. The exact levels of V1 and V2 may be selected by trial and error to give the best result in a particular instance. In this example, as can be seen in the pre-filtered waveform 800 shown in Figure 17, V1 is set to approximately half the level of V2.

In use, the bridge circuit operates, as has been previously described in respect of three different voltage sources, to selectively create positive and negative sub- cycles of a stepped waveform which is low-pass filtered by filter 805 to produce the desired sinusoidal output for application to the load, such as an antenna. The switching of switches S1 - S6 may be controlled by use of a suitable timing generation circuit. A suitable circuit includes a Delay Lock Loop (DLL) as has been previously described.

Many modifications will be apparent to those skilled in the art without departing from the scope of the present invention as herein described with reference to the accompanying drawings.

Claims

1. A transmitter for transmitting RF signals including: a plurality of switches arranged to apply one of a plurality of voltage sources to an output of the transmitter; timing control means to control said plurality of switches; wherein the timing control means is configured to selectively control said plurality of switches such that a desired modulation scheme is applied and a stepwise approximation of the desired output signal is created.

2. A transmitter as claimed in claim 1 wherein the timing control means includes a Delay Locked Loop (DLL) arranged to create a plurality of time delayed timing control signals from a reference clock input signal.

3. A transmitter as claimed in claim 1 or 2 wherein the transmitter includes bridge circuitry to invert the output waveform as required.

4. A transmitter as claimed in an any one of the preceding claims wherein the transmitter includes a filter at its output for reconstructing the stepwise approximation of the desired output signal.

5. A transmitter as claimed in claim 4 wherein the filter is a low-pass filter.

6. A transmitter as claimed in any one of the preceding claims wherein the plurality of voltage sources consists of three voltage sources in the ratio

100%:83%:54%.

7. A transmitter as claimed in any one of the preceding claims wherein each of the plurality of voltage sources is variable and is arranged to maintain a fixed ratio between itself and the other ones of said plurality of voltage sources.

8. A transmitter as claimed in any one of claims 2 to 7 wherein the frequency of the output signal is determined by the frequency of the reference clock input signal to the DLL.

9. A transmitter as claimed in claim 8 wherein the reference clock input signal to the DLL is arranged to be directly modulated so that phase modulation of the transmitted signal may be achieved.

10. A transmitter as claimed in any one of the preceding claims wherein the plurality of switches include transistors.

11. A transmitter as claimed in claim 10 wherein the transmitter is implemented in Application Specific Integrated Circuit (ASIC) form.

12. A transmitter as claimed in any one of the preceding claims wherein the plurality of voltage sources includes a single primary winding of a transformer coupled to a plurality of differently configured secondary windings of the transformer, each secondary winding being selectively connectable to a single reference voltage, such that temporary connection of the reference voltage to a particular secondary winding induces a particular voltage in the primary winding.

13. A transmitter as claimed in any one claims 2 to 11 wherein individual timing control signals are applied to ones of the plurality of switches via respective intermediate transformers.

14. A transmitter as claimed in claim 13 wherein a primary winding of each intermediate transformer is arranged to receive a timing control signal and a secondary winding of each intermediate transformer is arranged to control a respective switch.

15. A transmitter as claimed in claim 14 wherein the switch is a transistor and the secondary winding of the intermediate transformer is arranged to be connected to the base of the transistor.

16. A method of creating an RF signal waveform for direct transmission, including the steps of: providing a plurality of reference voltage sources; and selectively operating ones of a plurality of switches to apply one of said plurality of reference voltage sources to an output of said transmitter such that a signal at said output is a stepwise approximation of a desired output signal.

17. A method as claimed in claim 16 wherein the method further includes the step of filtering the waveform before transmission.

18. A method as claimed in claim 16 or 17 wherein the step of selectively operating ones of the plurality of switches includes the step of generating a plurality of time delayed copies of a reference clock input signal, and using selected ones of said plurality of time delayed copies to control ones of said plurality of switches.

19. A method as claimed in any one of claims 16 to 18 wherein a modulation scheme applied to said RF signal waveform is determined by the switching pattern used to control said plurality of switches.

20. A method as claimed in claim 19 wherein an RF signal waveform conforming to a non-constant envelope modulation scheme may be created by varying the plurality of voltage reference sources.

1. A transmitter for transmitting RF signals including: a plurality of switches arranged to selectively connect one of a plurality of secondary transformer windings to a voltage source; a primary transformer winding arranged to be coupled to said plurality of secondary transformer windings and connected to an output of the transmitter; and timing control means configured to selectively control said plurality of switches such that a desired modulation scheme is applied and a stepwise approximation of a desired output signal is generated at said output.