WO2003095112A2

WO2003095112A2 - Circuit and method for carrying out a calculation

Info

Publication number: WO2003095112A2
Application number: PCT/EP2003/004841
Authority: WO
Inventors: Holger Bock
Original assignee: Infineon Technologies Ag
Priority date: 2002-05-14
Filing date: 2003-05-08
Publication date: 2003-11-20
Also published as: DE10221409A1; TW591560B; TW200400474A; WO2003095112A3; AU2003224151A1

Abstract

The invention relates to a circuit for carrying out a calculation of user input data in order to obtain user output data, comprising a device (12) for performing an algorithm with one or several algorithm steps and a control device (18). The control device (18) controls the performing device (12) in such a way that it performs one or more algorithm steps prior to performing the algorithm with the user input data in order to obtain user output data, and/or after performing said algorithm. Said algorithm steps are provided in order to destroy or at least reduce the correlation between overall execution time and user input data. Differentiation of the algorithm steps during the performance of the actual algorithm and the algorithm steps, making timing attacks more difficult either prior thereto or afterwards, is made more difficult by performing all algorithm steps using the same device whereby it is impossible to make a distinction using power attacks such as SPA, for example.

Description

Circuit and method for performing a calculation

The present invention relates to performing calculations on useful input data to obtain useful output data, and in particular to arrangements for such circuits against hardware attacks in the case of their use in cryptography.

With the advent of more and more small mobile crypto devices, such as Chip cards and SIM cards, a new category of attacks on cryptographic algorithms became relevant, which are aimed directly at the hardware implementation of the cryptosystem. Attacks of this type use the data from very fine measurements on the crypto device while it is in the process of encryption and derive secret information, such as e.g. a cryptographic key. For example, the attacker suspects a few key bits and tries to

Verify correctness of the presumption by correlation with the measurements.

Some hardware attacks have been proposed, such as Measuring the time required for encryption or other time periods or measuring the power or power consumption and radiation patterns in order to obtain information about a secret key or other type that is stored on the device. Attacks of this type are generally independent of the cryptographic algorithm used, which is implemented by the crypto device, and can be applied to any device that is not protected against such attacks.

A special type of hardware attack is the time measurement or timing attack, in which by precisely measuring the time it takes to complete a cryptographic attack. to carry out a graphic algorithm, attackers are enabled to receive information about the data processed by the implemented cryptographic algorithm or the key or keys used by the same. Timing attacks take advantage of the fact that crypto devices often take a slightly different amount of time to process different input data. The reasons for this can be varied and include, for example, performance optimizations to skip unnecessary operations, conditional jump commands, RAM cache hits and computing units that perform computing operations, such as multiplication and division, in different time periods, depending on both the cryptographic key as well as the input data.

Previous circuits for carrying out a cryptographic algorithm suffer from the fact that, because of their input data-dependent execution time for carrying out the algorithm, they represent a vulnerable target for timing attacks. This fact is even more serious when calculating cryptographic algorithms using asynchronous electronic circuits, since in general there is an inherently data-dependent execution time. In the case of synchronous circuits, where the constancy of the total duration of a calculation in terms of the number of clock cycles required can usually be ensured by appropriate control structures or software, attempts are often made to destroy the time base within the time clock pattern, thus correlative attacks (such as SPA attacks Simple power analysis) can be prevented. Although this property of the variable time base is inherent in asynchronous circuits, the need to guard against timing attacks remains.

There is consequently a need for circuits for performing a calculation on useful input data in order to obtain useful output data in which the execution time does not depend on shows usefulness of the input data, and thus the exploration of secret data or keys based on this dependency is effectively avoided.

The object of the present invention is to provide a circuit and a method for performing a calculation on useful input data in order to obtain useful output data, so that security against hardware attacks is increased.

This object is achieved by a circuit according to claim 1 and a method according to claim 13.

The present invention is based on the finding that the security of circuits for carrying out a calculation on useful input data in order to obtain useful output data can be effectively increased against hardware attacks by assigning a control device to a device for performing an algorithm with one or more algorithm steps, which control device controls the device for carrying out in such a way that before the actual algorithm is carried out with the user input data in order to obtain the useful output data and / or afterwards one or more algorithm steps are carried out which are only intended to correlate the total execution time and

Destroy useful input data or at least reduce it. The distinction between the algorithm steps during the execution of the actual algorithm and the algorithm steps which are carried out before or after to aggravate timing attacks is made more difficult according to the invention in that all algorithm steps are carried out using the same device, so that, for example, power attacks, such as SPA, no difference can be perceived.

An advantage of the present invention is that it is easy to use with many cryptographic algorithms is to be implemented since these algorithms have the repetition of calculation operations or algorithm steps anyway. Examples of cryptographic algorithms that have the repetition of operations with the same characteristic include, for example, the DES algorithm (data encryption standard), in which 16 rounds are carried out, the AES standard (advanced encryption standard) the 10th, 12th or 14th rounds, the RSA algorithm (named after its three founders Rivest, Shamir and Ademan), in which many modular multiplications have to be carried out, or the ECC algorithm (ECC = Elliptic Curve Cryptography = Elliptic curve cryptography) with many modular multiplications. The present invention consequently takes advantage of the characteristic inherent in these algorithms of repeated use of arithmetic operations.

Further preferred embodiments are the subject of the subclaims.

Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. Show it:

1 is a block diagram of a circuit for performing a calculation according to a general embodiment of the present invention; and

Fig. 2 is a block diagram of a circuit for performing a DES algorithm according to a specific embodiment of the present invention.

The present invention will first be described with reference to FIG. 1 using a general exemplary embodiment. 1 shows a circuit for performing a calculation on useful input data in order to obtain useful output data which is generally indicated at 10. The circuit 10 comprises means 12 for performing an algorithm, such as a DES, AES or RSA algorithm, or a part thereof with one or more algorithm steps, such as the rounds in the case of the DES and AES algorithm and the modular multiplications in the case of the RSA algorithm. At an input 14, the device 12 receives the useful input data to be processed, which it converts into useful output data in an execution time to be discussed below, which in turn is used at an output 16 after the expiry of the

Output execution time. The circuit 12 is connected to a control device 18, which controls the device 12 in such a way that it carries out one or more additional algorithm steps before carrying out the actual algorithm with the useful input data in order to obtain the useful output data and / or after the same.

The control device 18 controls the device 12 in such a way that the useful input data are not deleted while the additional algorithm steps are carried out before the actual algorithm is carried out and the useful output data obtained are not deleted during the additional algorithm steps after the actual algorithm is carried out. The execution time that the circuit 10 takes to receive the input data at the input 14

Outputting the useful output data at the output 16 is consequently the sum of the time periods which the device 12 takes before and after it to carry out the algorithm steps of the actual algorithm and the additional algorithm steps.

The circuit 10 above has two essential properties which protect it against hardware attacks. First of all, the correlation between the useful input data and the execution time of the circuit 10 is no longer dependent solely on the algorithm implemented by the device 12 and the useful input data, since the pure calculation duration is the time required to carry out the additional algorithm step or steps. A dependency of the execution time on the user input data due to, for example, different cache hits, conditional jumps or the like in the device 12 is thereby obscured. In particular in the case of an asynchronously operating device 12, the time period for performing an algorithm step is dependent on the input data. This is because asynchronous circuits are self-clocked, so that the intermediate results of the various logic components from which the asynchronous circuits are constructed are processed by the logic components of the subsequent stage independently of a clock whenever all are required as input data for a respective logic component Interim results are available. In addition, different input data in asynchronous circuits lead to different logic paths within the logic components from which the asynchronous circuit is constructed, which in turn have different run times. This leads to the fact that asynchronous circuits have an inherently data-dependent execution time, since each intermediate result and also the end result, depending on the logic paths taken within the logic components, are present immediately and not in units of a cycle sooner or later at the output. In the case of an asynchronously self-clocking device 12, the addition of performing the additional algorithm steps consequently obscures the data dependency of the execution time of the circuit 10.

Various measures can be taken to further reduce the dependency of the execution time of the circuit 10 on the user input data 14 or even to completely eliminate it. A first possibility is to calculate the number of additional algorithm steps carried out before and after the actual algorithm has been carried out, from calculation to calculation, ie from the user input date to the user input data. tum, to be redetermined at random. In this way, the part of the execution time of the circuit 10 caused by the additional algorithm steps performed per calculation varies, so that the dependence of the execution time on the useful input data is even less and timing attacks are even more difficult. In the case of circuits in which the execution time is dependent on the data to be processed, ie in particular in the case of asynchronous, self-clocking circuits, the dependence of the execution time on the useful input data can be further obscured by the fact that the additional performed algorithm steps before or after the execution of the actual algorithm are based on random "sham" input data. Due to the inherently data-dependent execution time of an asynchronously working device 12, the additional execution time caused by the additionally performed algorithm steps varies from that to the execution of the actual algorithm effected execution time is added, in the case of an asynchronous circuit even if the number of additional algorithm steps per calculation is the same, provided that the algorithm steps immediately r be executed in succession without being triggered by an external clock at certain times.

A further property of the circuit 10, which helps it to provide increased protection against hardware attacks, is that the additional algorithm steps carried out are based on arithmetic operations with the same characteristics, or in other words the additional algorithm steps carried out are carried out by the same device 12. In the above-mentioned examples and in the exemplary embodiment of FIG. 2, which is discussed below, the algorithm steps are based on the same arithmetic operations and differ from one another only by different input operands, such as the intermediate result of the previous algorithm step and those in this step key. In this case, an attacker, while observing the power consumption, cannot distinguish additional bogus algorithm steps from those algorithm steps that are carried out during the actual algorithm.

A special exemplary embodiment of a circuit for carrying out a DES calculation is described below with reference to FIG. 2, in which additional algorithm steps are carried out both before and after the actual algorithm has been carried out. The circuit of FIG. 2, indicated generally at 50, includes a circuit portion 52 for performing a DES algorithm and a control unit 54 for controlling circuit portion 52. Circuit portion 52 includes an input register 56, a result register 58, and a DES module 60. In addition, the circuit section 52 comprises multiplexers 62 and 64 and an additional register 66. The input register 56 is connected directly to an input 68 of the circuit 50. The multiplexer 62 connects either the input register 56 or the additional register 66 to an input of the DES module 60, depending on how it is indicated by a control signal which the multiplexer 62 receives from the control unit 54 connected to it. To return the result of a round of the DES algorithm as an input operand for the next DES round, the multiplexer 64 is able to connect the output of the DES module 60 to the register 66 via a further multiplexer 69. However, the multiplexer 64 can also connect the output of the DES module to the result register 58. The connection established by the multiplexer 64 depends on a control signal which the multiplexer 64 receives from the control unit 54 connected to it. The output register 58 is connected to an output 70 of the circuit 50. In addition to the input connected to the multiplexer 64, the multiplexer 69 also includes a further input via which, as will be described below, a random start value d _{z can be} loaded into the additional register 66 which an output of the multiplexer 69 is connected. Which of the two inputs, ie the one at which the value d _z is received or the one to which the intermediate result is supplied by the DES module via the multiplexer 64, the multiplexer 69 connects to the input of the register 62 depends on a control signal which the multiplexer 69 receives from the control unit connected to it. The control unit 54 comprises a counter 72 for counting the laps carried out during an overall calculation, as will be described in the following.

After the structure of the circuit of Fig. 2 has been described above, the operation of the same will be described below. The circuit 50 is provided to carry out a calculation on useful input data at the input 68 and to output the result in the form of useful output data at the output 70. In particular, it is assumed in FIG. 2 that the circuit 50 is provided for performing a DES calculation, which maps 64 bits of user input data to 64 bits of useful output data. The DES

Lap calculations are carried out by the DES module 60, which is asynchronous in the present case and works self-clocked. In other words, the execution time of the lap calculations by the DES module 60 is different for each lap or for each input value, and the result of a lap is present at the output of the DES module 60 immediately after the calculation, regardless of a clock. A lap calculation by the DES module 60 is therefore dependent on input data.

In the following, a calculation is used to understand the encryption of a 64-bit block of the user input data at input 68. During a calculation, the 64-bit block is subjected to 16 rounds that are performed by the DES module 60. Each round performed by the DES module 60 is based on the same arithmetic operation, which in turn consists of several arithmetic operations. These arithmetic part operations consist of the following steps: (1) dividing the 64-bit block of the previous round or, in the case of the first round, the usage data into a left half of 32 bits and a right half of 32 bits,

(2) mapping the right half of the previous round to a left half of a 64-bit block of the current round to be calculated,

(3) expanding the 32 bits of the right half of the previous block into a 48 bit block according to a selection table that doubles some of the bits of the right half of the previous round,

(4) subjecting the expanded 48-bit block to an XOR operation with a round key or partial key calculated from a DES key and assigned to the current round,

(5) access with each of eight groups of six bits each of the encrypted 48-bit block as an address to so-called "S-boxes" which represent functions which map a 6-bit block to a 4-bit block, where an S-Box is defined for each group,

(6) after mapping each 6-bit group into a 4-bit group, permuting the resulting 32-bit block, and

(7) Perform an XOR between the left half of the previous round and the permuted 32-bit block to get the current 32 bits of the right half of the current round.

A total of 16 rounds are thus processed for each 64-bit

Block performed. The circuit 50 carries out further permutations for a complete DES encryption. In particular, the 64 bits present at input 68 were previously subjected to a further permutation for complete DES encryption. In addition, the 64 bits resulting from the 16 DES rounds are subjected to an inverse permutation. However, these permutations, which are achieved, for example, via fixed wiring, make no or at least no significant contribution to the overall calculation time of DES encryption and are therefore only described below with regard to the execution time or duration of a complete DES encryption takes into account the time required for the 16 DES rounds. For the following discussion, the pure execution time for a calculation of the actual DES encryption of a 64-bit data block is therefore composed of the 16 rounds by the DES module 60. Due to the asynchronous nature of the DES module 60, it would be extremely dependent on the 64 bit input data.

For this reason, additional rounds are added to the actual 16 rounds of a DES calculation in order to determine the correlation between the execution time of the circuit 50 on the one hand and secret information, such as e.g. the user input data to be encrypted and the DES key or the round key.

To initialize a calculation, a random start value d _z is first loaded into the additional register 66 via the multiplexer 69, which serves as an input operand for the cyclically carried out additional rounds before the actual algorithm is carried out. The multiplexer 69 is then switched over in order to connect the input of the additional register 66 to the multiplexer 64 from now on. In addition, the counter 72 of the control unit 54 is set to a random start value z _o . When the 64-bit input block arrives, it is first stored in the input register 56. The control unit 54 controls the multiplexer 62 in such a way that the random value d _ε first the additional register 66 is fed to the DES module 60 for carrying out a DES round. For each DES round carried out, the payer 72 increments the counter value z (ie | N, i being the number of the DES round currently being carried out) in the control unit 54 by 1. For this purpose, the payer 72 is preferably designed such that the counter value Zj _, Gray-coded, so that in the bit representation of the counter value Zj _. changes only one bit per increment to provide little clues for hardware attacks.

In this way, the DES module 60 carried out a "false round", ie a round that does not belong to the actual rounds of the actual DES calculation and thus is not used to calculate the useful output data. The control unit 54 sets the multiplexer 64 in such a way that that the output of the DES module 60 is connected to the register 66 so that the result of the dummy round is copied into the additional register 66. The control unit 54 monitors how many false rounds are carried out and compared with the intermediate results stored in the additional register 66 constantly the counter value z _x in the counter 72 with a comparison value v.

As soon as the counter value z ^ of the counter 72 has reached the comparison value v, the control unit changes the multiplexer 62 in such a way that it connects the input register 56 to the input of the DES module 60. In this way, the DES module carried out 60 m = v - z _o false rounds, namely as many rounds starting from the initialization until the constant comparison value v was reached by incrementing the random value z ₀ . The number of bogus rounds at this time is therefore m = v - z _o . According to a further exemplary embodiment, the comparison value v can of course also be set randomly.

Due to the conversion of the multiplexer 62, the 64-bit user data input block, which as mentioned above, is now has already been subjected to a permutation in a permutation module, not shown, fed from the input register 56 into the DES module 60. After performing the first DES round on the 64-bit input block, the DES module 60 outputs the result or the first 64-bit useful intermediate data block via the multiplexer 64 into the intermediate register 66, whereupon the counter 72 increments its counter value Zi. The control unit 54 again switches the multiplexer 62 in such a way that the additional register 66 is connected to the input of the DES module 60. The 15 remaining rounds of the actual DES calculation are then carried out, the intermediate result to be encoded being entered by the additional register 66 into the DES module 60 and subjected to a DES round there, and the new intermediate result again in the additional one Register 66 is copied. Alternatively, each intermediate result could also be copied into the input register 56 during these 16 DES rounds of the actual DES calculation, in which case an additional data path from the output of the DES module 60 via the multiplexer 64 would lead to the register 56.

The control unit 54 ensures that after the 16 DES rounds of the actual calculation, the multiplexer 64 is changed over such that the register 58 is connected to the output of the DES module 60. The result of the 16 th DES round of the actual DES calculation, which consequently represents the encrypted 64-bit useful output block, is correspondingly copied into the register 58. From the point in time when the required result or the 64-bit useful output block is available, ie after 16 DES rounds of the actual DES calculation, further round results are only copied into the additional register 66, which depends on the characteristics, such as the current consumption and the switching times, behaves the same as the result register 58, in which the result now rests. The control unit 54 takes care of this by converting the multiplexer 64 again so that it connects the output of the DES module 60 to the additional register 66.

The gray-coded counter 72 or its counter value z has, however, continued to a value v + 16 = z ₀ + m + 16. Although the actual 64-bit result is already available in the result register 58, the control unit 54 the DES module 60 executes further false rounds and ensures that the result is held back in the result register 58 for as long as this. The control unit 54 monitors the payer value z _{x of} the payer 72 reaches a fixed or a random final value e. In the apparent rounds following the 16th round of the actual DES calculation, the intermediate results temporarily stored in the additional register 66 are fed to the DES module. In the first dummy round after the 16th round of the actual calculation, the DES module is consequently supplied with the same intermediate result which has led to the 64-bit useful data output block finally stored in the result register 58.

After the control unit 54 has determined that the counter value Zj _. of the payer 72 has reached the end value e, n + 16 + m rounds have been carried out by the DES module 60 in total, ie including the false rounds and the 16 DES rounds of the actual calculation, where n is the number of rounds after the actual one Calculation of rounds performed and n = e - z _o - m - 16 and m = v - z _o . When this counter value e is reached, the control unit 54 prevents any further DES rounds from being carried out in the current calculation and releases the result in the result register 58 for output at the output 70.

From the preceding discussion of the mode of operation during a DES calculation of the circuit 50, it is clear that the correlation between the 64-bit user input data and the execution time required for calculating the 64-bit useful output data, ie including the false rounds, is low. each The round carried out in the DES module 60 requires a different period of time, which depends on the 64 bit input data to be processed by the respective round and the respective round partial key. Assuming that the DES module 60 in the dummy rounds before and after the actual DES calculation also works with the round keys used during the actual DES calculation, the total calculation execution time therefore depends primarily on the total number m + 16 + n of the DES rounds carried out, ie the DES rounds of the actual DES calculation and the dummy rounds before and after. Due to the self-clocked mode of operation of the DES module 60 and the associated input data-dependent lap calculation time, the total execution time also depends on the random value on which the additional register 66 is initialized at the beginning of each calculation. The total number of rounds m + 16 + n in turn depends on the random value to which the counter 72 is initialized, and additionally, as mentioned above, possibly on a random comparison value v and a random final value e.

In the case of a hardware attack in which time measurements and power consumption measurements are carried out, it is initially difficult to draw conclusions from the execution time of secret data, such as the slot input data or the secret DES key are pulled. In addition, based on observations of the time course of the power consumption, false rounds cannot be distinguished from the actual 16 DES rounds, since all rounds are carried out by the same DES module 60, and thus each round, whether a false round or one of the 16 DES rounds has the same power consumption characteristics.

In the foregoing description, it was assumed that the counter 72, controlled by the round processing by the DES module 60, updated its counter value every time the round was completed. incremented, and that the round calculations by the DES module 60 thus follow one another immediately, without an external clock dictating the start of each DES round from the outside. In another embodiment, counter 72 is clocked, which clock is also used to activate DES rounds by DES module 60. In this case, a fixed end value e can ensure that the DES calculation by the circuit 50 always takes the same time.

In an alternative embodiment, the control unit 54 instead of the counter 72 comprises a timer which measures the time from the arrival of the user input data at the input 78, the control unit 54 performing the DES calculation by the circuit 50 before and after the DES bill round the actual DES calculation stops, on which the timer exceeds a certain predetermined period of time. In this case too, the execution time of the circuit 50 can be kept constant except for units of a calculation duration for a DES round.

In the event that the slot input data to be processed by the circuit 50 is data of a certain protocol with a constant block length, such as an ATM protocol (ATM = Asynchronous Transfer Mode), in which the block length is a multiple of the DES block length of 64 bits , the encryption of all DES blocks belonging to a protocol block can be carried out in a longer "mill pass" so that the circuit does not come to rest until the protocol block has been completely encrypted. The number of deflection rounds v _x and ni at the expense of increased latency and with the addition of additional registers. For example, in addition to the additional register per 64 bit block of a protocol block, an input register and an output register are provided, alternating false rounds and then the 16 rounds on one of the 64 bit Bucks are carried out. The embodiment of FIG. 2 consequently causes the execution time to be extended to any random or else to an adjustable constant value, from which no longer occurs, by temporally variable prepending or appending operations of the same characteristic as in the algorithm to be protected, but using random data the original data-dependent execution time can be inferred. It is important to note that not only the DES algorithm shown in FIG. 2, but also many other crypto-algorithms, involve repeating operations with the same characteristic anyway, such as the AES algorithm, which has 10, 12 or 14 rounds , or the RSA algorithm, which has the execution of several modular multiplications. The embodiment of FIG. 2 therefore makes use of the characteristic of many algorithms inherent in the reuse of a single operation for the additional operations.

In addition, as described above, the data dependent execution time of asynchronous circuits is made immeasurable by providing a flexible adjustable control unit which ensures that random calculations are carried out before and / or after the actual calculation in order to hide the true calculation duration.

With reference to the embodiment of FIG. 2, it is pointed out that in addition to the three registers shown, a fourth can be provided, in which the random value can be provided upon initiation of a DES calculation, which is used as the basis for the first DES round of notes , In addition, the exemplary embodiment shown in FIG. 2 could easily be transferred to the case that false rounds are only carried out before or only after the actual 16 DES rounds. In this case, either the input register 56 or the result register 58 may be missing. On the other hand, the above embodiment could without further res are transferred to the case that false rounds are also interspersed between the individual rounds of the actual calculation. It is also not necessary that a register is provided in this feedback path for the feedback of the preliminary result of a preliminary round to a subsequent round, regardless of whether it is a dummy round or two of the 16 DES rounds of the actual calculation. Furthermore, it is pointed out that the counter value of the counter 72 in FIG. 2 does not have to be incremented during the known fixed number of 16 DES rounds of the actual DES calculation, provided that a separate counter is available for the 16 DES rounds.

Furthermore, it is finally pointed out that the description with reference to FIG. 1 can also be transferred to a corresponding device in which the blocks in FIG. 1 represent corresponding steps of a method. In general, the idea on which the present invention is based can be implemented in integrated circuits, chip cards, SIM cards or wired circuits. Implementation in combined hardware and software is also conceivable.

LIST OF REFERENCE NUMBERS

10 circuit

12 device for performing an algorithm 14 input

16 output

18 control device

50 DES circuit

52 circuit part 54 control unit

56 input registers

58 result register

60 DES module

62 multiplexers 64 multiplexers

66 additional registers

68 entrance

69 multiplexers

70 output 72 counter

Claims

claims

1. Circuit for performing a calculation on useful input data in order to obtain useful output data with

means (12, 52) for performing an algorithm with one or more algorithm steps; and

a control device (18; 54) for controlling the device (12, 52) for performing such that the same before one

Execution of the algorithm with the user input data in order to obtain the useful output data and / or after the execution of the algorithm carries out one or more algorithm steps.

2. Circuit according to claim 1, in which all algorithm steps are based on the same arithmetic operation, and in which the device (52) for performing has the following features:

a result register (58);

an additional register (66);

an arithmetic unit (60) for performing the arithmetic operation; and

a switchover unit (64) for connecting an output of the computing unit (60) to either the result register (58) or the additional register (66),

the control unit (54) being adapted to control the means for performing such that the output of the arithmetic unit (60) is connected to the result register (58) when the execution of the algorithm is complete, and that the output of the arithmetic unit (60) while performing the one or more algorithm steps after the Execution of the algorithm is connected to the additional register (66).

3. A circuit according to claim 1 or 2, wherein the means (52) for performing further comprises an input register (56) for

Storage of the useful input data while performing the algorithm steps before performing the algorithm.

4. A circuit according to claim 3, wherein the device (52) further comprises the following features:

a random register for storing a random number; and

a further switching unit (62) for connecting an input of the computing unit (60) to the input register (56) or the random register (66),

the control unit (54) being adapted such that it controls the means (52) for carrying out such that, when the algorithm steps are started before the algorithm is carried out, the input of the computing unit (60) with the random register and at the start of the execution the algorithm, the input of the computing unit (60) is connected to the input register (56).

5. Circuit according to one of claims 1 to 4, wherein the control unit has a counter (72) for incrementing a counter value per performed algorithm step when performing the algorithm steps before and / or after the execution of the algorithm, the control unit (54) being adapted to abort the execution of the algorithm steps when the counter value has reached a predetermined comparison value.

6. The circuit of claim 5, wherein the counter (72) is adapted such that the counter value is gray-coded.

7. A circuit as claimed in claim 5 or 6, wherein the counter (72) is adapted to increment in a synchronous case according to a clock which further starts the execution of each algorithm step, both before and / or after the execution of the actual algorithm as well as that of the algorithm, or is adapted in such a way that it increments in an asynchronous case as soon as an algorithm step in the execution of the algorithm steps or an algorithm step in the execution of the algorithm has ended.

8. A circuit according to claim 5 or 6, further comprising means for initializing the counter value to a random value before each calculation by the circuit.

9. Circuit according to one of claims 1 to 4, in which the control unit (54) has a device for detecting the past period of time for performing the algorithm steps before and / after performing the algorithm, the control unit (54) being adapted to abort the execution of the algorithm steps when the detected time period has reached a predetermined time value.

10. Circuit according to one of claims 1 to 9, wherein the device (52) for performing self-clocking, and an execution time of the device (52) for performing depends on the useful input data.

11. Circuit according to one of claims 1 to 10, wherein the algorithm steps are rounds of a DES or AES algorithm or modular multiplications of an RSA or an ECC algorithm.

12. Circuit according to one of claims 1 to 11, wherein the algorithm a predetermined sequence of algorithm steps and the control unit (54) is adapted in such a way that the means (52) for performing when performing the algorithm steps before performing the algorithm and when performing the algorithm steps after performing the algorithm performs the algorithm steps according to the predetermined sequence ,

13. Method for performing a calculation on useful input data in order to obtain useful output data with

Performing an algorithm with one or more algorithm steps; and

Controlling the implementation in such a way that one or more algorithm steps are carried out before the algorithm is carried out with the user input data in order to obtain the useful output data and / or after the algorithm is carried out.