WO2003016205A3 - Mems and method of manufacturing mems - Google Patents

Mems and method of manufacturing mems Download PDF

Info

Publication number
WO2003016205A3
WO2003016205A3 PCT/US2002/026090 US0226090W WO03016205A3 WO 2003016205 A3 WO2003016205 A3 WO 2003016205A3 US 0226090 W US0226090 W US 0226090W WO 03016205 A3 WO03016205 A3 WO 03016205A3
Authority
WO
WIPO (PCT)
Prior art keywords
mems
manufacturing
vertically integrated
systems
facilitated
Prior art date
Application number
PCT/US2002/026090
Other languages
French (fr)
Other versions
WO2003016205A2 (en
Inventor
Sadeg M Faris
Original Assignee
Reveo Inc
Sadeg M Faris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Reveo Inc, Sadeg M Faris filed Critical Reveo Inc
Priority to AU2002327469A priority Critical patent/AU2002327469A1/en
Priority to EP02763461A priority patent/EP1417152A2/en
Priority to JP2003521140A priority patent/JP2005500172A/en
Publication of WO2003016205A2 publication Critical patent/WO2003016205A2/en
Publication of WO2003016205A3 publication Critical patent/WO2003016205A3/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The present invention relates to micro electro-mechanical systems (MEMS) and production methods thereof, and more particularly to vertically integrated MEMS systems. Manufacturing of MEMS and vertically integrated MEMS is facilitated by forming, preferably on a wafer level, plural MEMS on a MEMS layer selectively bonded to a substrate, and removing the MEMS layer intact.
PCT/US2002/026090 2001-08-15 2002-08-15 Mems and method of manufacturing mems WO2003016205A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2002327469A AU2002327469A1 (en) 2001-08-15 2002-08-15 Mems and method of manufacturing mems
EP02763461A EP1417152A2 (en) 2001-08-15 2002-08-15 Mems and method of manufacturing mems
JP2003521140A JP2005500172A (en) 2001-08-15 2002-08-15 MEMS and MEMS manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31265901P 2001-08-15 2001-08-15
US60/312,659 2001-08-15

Publications (2)

Publication Number Publication Date
WO2003016205A2 WO2003016205A2 (en) 2003-02-27
WO2003016205A3 true WO2003016205A3 (en) 2004-02-12

Family

ID=23212437

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/026090 WO2003016205A2 (en) 2001-08-15 2002-08-15 Mems and method of manufacturing mems

Country Status (5)

Country Link
EP (1) EP1417152A2 (en)
JP (1) JP2005500172A (en)
AU (1) AU2002327469A1 (en)
TW (1) TW553891B (en)
WO (1) WO2003016205A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4867792B2 (en) * 2007-05-24 2012-02-01 パナソニック電工株式会社 Wafer level package structure and sensor device
DE102007048604A1 (en) * 2007-10-10 2009-04-16 Robert Bosch Gmbh Composite of at least two semiconductor substrates and manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764950A (en) * 1972-07-17 1973-10-09 Fairchild Camera Instr Co Methods for making semiconductor pressure transducers and the resulting structures
FR2771852A1 (en) * 1997-12-02 1999-06-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF A MICROSTRUCTURE, FORMED ON AN INITIAL SUBSTRATE, TO A FINAL SUBSTRATE
EP0938129A1 (en) * 1998-02-18 1999-08-25 Canon Kabushiki Kaisha Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764950A (en) * 1972-07-17 1973-10-09 Fairchild Camera Instr Co Methods for making semiconductor pressure transducers and the resulting structures
FR2771852A1 (en) * 1997-12-02 1999-06-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF A MICROSTRUCTURE, FORMED ON AN INITIAL SUBSTRATE, TO A FINAL SUBSTRATE
EP0938129A1 (en) * 1998-02-18 1999-08-25 Canon Kabushiki Kaisha Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GUI C ET AL: "SELECTIVE WAFER BONDING BY SURFACE ROUGHNESS CONTROL", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 148, no. 4, 2001, pages g225 - g228, XP001090843, ISSN: 0013-4651 *

Also Published As

Publication number Publication date
JP2005500172A (en) 2005-01-06
TW553891B (en) 2003-09-21
AU2002327469A1 (en) 2003-03-03
EP1417152A2 (en) 2004-05-12
WO2003016205A2 (en) 2003-02-27

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