WO2002091578A2

WO2002091578A2 - Phase-locked loop system

Info

Publication number: WO2002091578A2
Application number: PCT/CA2002/000570
Authority: WO
Inventors: Masoud Karimi Ghartemani
Original assignee: Masoud Karimi Ghartemani
Priority date: 2001-05-09
Filing date: 2002-04-22
Publication date: 2002-11-14
Also published as: WO2002091578A3; AU2002252890A1; CA2346136A1

Abstract

A new structure for phase-locked loop (PLL) system is disclosed. As with conventional PLLs, the present invention consists of phase detection, loop filter and voltage-controlled oscillator units. An alternative phase detection structure, inspired by concepts from adaptive filtering and dynamical systems theory, is presented which substantially enhances the performance of the loop in terms of stability and dynamic performance. Presented phase detection scheme obviates the need for sophisticated loop filters, so much so that a first order filter suffices for most applications. In addition to the normal function of a PLL, the present system directly generates estimates of the amplitude, phase and frequency of the input signal. This feature extends the range of applications of the system beyond well-known applications of PLL in various disciplines of electrical engineering.

Description

ENHANCED PHASE-LOCKED LOOP (PLL) SYSTEM

TECHNICAL FIELD

The present invention relates to phase-locked loop (PLL) systems and circuits, and in particular, to an enhanced phase-locked loop structure which exhibits global stability within an indefinitely wide dynamic range of operational amplitude, phase and frequency, the values of which axe directly estimated by the system. The improvement to the structure of the conventional PLL systems is achieved by means of introducing a phase detection (PD) scheme into the loop which, while ensuring the stability of the loop for any point of operation, simplifies the structure of the loop filter (LF) to the extent that a first order filter is sufficient for most of the applications in which PLLs are currently used. The range of applications of the present invention encompasses those in which conventional PLLs are employed such as filtering of electrical signals, demodulation in continuous- wave modulation systems, clock recovery in digital transmission systems as well as those in which detection and extraction of amplitude, phase and frequency of signals are desired such as phasor measurement in power systems.

BACKGROUND ART

Phase-locked loop is a fundamental concept widely used in diverse areas of electrical engineering such as communications, instrumentation, systems control, radar, and telemetry. The main idea of phase lock is the ability to generate a sinusoidal signal whose phase coherently follows that of the main component of the input signal. PLLs have been the subject of research for several decades. Enormous amount of theoretical and practical information is now available on this rather mature subject. Explosive developments in the area of electronic circuitry have had tremendous impact on the PLL technology. Inventions in PLL technology combined with advancement in integrated circuit (IC) technology have rendered PLL circuits important system components. Ex- amples of inventions in this area abound. To name a few, one is referred to the following United States of America patents: 6208182 Mar. 27, 2001 Marbot, et al.,

6104222 Aug. 15, 2000 Embree,

6049254 Apr. 11, 2000 Knapp, et al.,

6031428 Feb. 29, 2000 Hill,

5978426 Nov. 02, 1999 Glover, et al.,

5909474 Jun. 01, 1999 Yoshizawa.

Despite the abundance of theoretical information on PLL and its fascinating technological progress, the fundamental structure of PLL has remained almost unchanged since its introduction in 1930s. The phase difference between the input and output signals is measured using a phase detector and, having been passed through a loop filter, is used as the error signal driving a voltage controlled oscillator (VCO) which generates the output signal. The PD constitutes the main part of the PLL structure so much so that very often PLL is thought of as solely consisting of the PD, the existence of which presumes a closed loop. The PD may be implemented in digital or analog form, a crucial structural feature which is the turning point of ramification into digital and analog PLL technology.

The most intuitive structure for the PD is a multiplier, sometimes referred to as mixer or sinusoidal PD. The output signal of the loop filter which follows the PD, i.e. the error signal, is supposed to be a measure of the total phase difference between the two input signals of the PD. Ideally, such an error signal is proportional to, or at least a monotonic function of, the total phase difference between the two input signals of the

PD. The fundamental problem of conventional PLL -of which all the complex theory and practical shortcomings involving PLL are consequences- is that such an ideal has never been realized. Such a simple structure of PLL consisting mainly of a means of generating an error signal proportional to the total phase difference, which has remained the most obvious choice -and as if the only choice- ever since the phase lock concept was introduced, provides the most intuitive PLL structure; a simple and intuitive starting point which, by the very reason of its non-existence, was never accomplished. Such a concept of phase lock promised to result the simplest PLL, a promise which was never fulfilled and therefore hindered the development of any alternative method by its fascinating enticement.

Conventional PLLs, although possess an intuitive structure comprising conceptually easy to understand components, are well-known for having loop stability problems for input signals whose parameters such as amplitude, phase and frequency may undergo large variations. There has been reported no PLL structure which is proved, both theoretically and practically, to be capable of locking into the desired component of the input signal whose parameters, especially frequency, may vary in an indefinitely wide range of values.

DISCLOSURE OF INVENTION

The present invention offers a new structure for PLL based on an alternative method of phase detection. Unlike conventional PLL theory which despite its hypertrophy of mathematical proofs does not guarantee the desired performance of PLL in general, the desired performance of the present invention is theoretically proved in general. The loop filter in the introduced PLL has a very simple structure which nonetheless provides an easy yet powerful method of control and determination of the behavior of the loop. Everything is determined by the adjustment of a few parameters so that the need for sophisticated loop filters is obviated.

It is an object of the present invention to provide a phase-locked loop system which would obviate aforementioned shortcomings of conventional PLLs, namely those associated with loop stability problems and narrow range of admissible variations of the parameters of the input signal. This is accomplished through the introduction of a new structure for PLL in which the phase detection mechanism is substantially improved and the structure of the loop filter is significantly simplified.

According to one aspect of the invention, the intuitive phase detection unit is replaced by a rather non-intuitive phase detection mechanism, the structure of which comprises simple arithmetic units easily realizable in the form of analog and digital circuitry, or alternatively, if the implementation is done in software form, in the form of computa- tional procedures.

Advantageously, the need for complex loop filters, conventionally employed to control and improve the operation of the loop, is obviated to the extent that a simple gain unit, or equivalently a P-controUer, or alternatively a first order filter, or more specifically a Pi-controller, may be employed to provide almost any desired performance. This feature drastically reduces the structural complexity and simplifies the design procedure.

Accordingly, the first embodiment of the invention employs a simple gain unit, a P- controller, as the loop filter and shall hereinafter be referred to as P-type PLL. The second embodiment of the invention employs a Pi-controller as the loop filter and shall hereinafter be referred to as Pi-type PLL. All other embodiments of the invention employing higher order filters as the loop filter shall be called higher order PLLs.

Advantageously, the performance of the loop in terms of speed of convergence and admissible error is fully controlled by means of the adjustment of a few parameters. This provides the designer with an easy yet powerful means of determination of the behavior of the system for different applications.

It is another object of the present invention to extend the functionality of the conventional PLL systems from capability of locking to the phase (and a limited range of frequency) of the input signal to capability of locking to amplitude, phase and frequency of the input signal, thereby providing an amplitude-phase-frequency-locked loop system.

It is also another object of the present invention to furnish the PLL system with means of direct estimation of the values of amplitude, phase and frequency of the desired component of the input signal instantly and with high speed and precision.

According to an aspect of the present invention, two controlling parameters in the case of the first embodiment of the invention, i.e. P-type PLL, provide full control over the speed/error trade-off in the estimated values of the amplitude and phase of the desired component of the input signal.

According to another aspect of the present invention, three controlling parameters in the case of the second embodiment of the invention, i.e. Pi-type PLL, provide full control over the speed/error trade-off in the estimated values of the amplitude, phase and frequency of the desired component of the input signal.

It is yet another object of the present invention to equip the PLL system with means of providing a sinusoidal signal synchronized with the desired component of the input signal having the same amplitude, phase and frequency as that of such a desired component of the input signal which moreover follows the variations in the characteristics of such a desired component over time while being insensitive to external disturbances and environmentally imposed noise.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings fike reference numbers denote like components, brief description of each of which is herewith given.

Figure 1 shows a general structural block diagram of the PLL system,

Figure 2 shows the block diagram of one possible embodiment of the phase detection scheme wherein an amplitude adjustment unit described in Figure 3 is employed, Figure 3 shows the structure of the amplitude adjustment unit used in the preferred phase detection unit of Figure 2, Figure 4 shows one possible structure of the loop filter of Figure 1 employing which results the first embodiment of the present invention, namely P-type PLL, Figure 5 shows another possible structure of the loop filter of Figure 1 employing which results the second embodiment of the present invention, namely Pi-type PLL, Figure 6 shows the block diagram of another possible embodiment of the phase detec- tion scheme,

Figure 7 illustrates, by way of example, the performance of the first embodiment of the present PLL with respect to a pure sinusoidal input signal, Figure 8 illustrates, by way of example, the performance of the first embodiment of the present PLL with respect to a step change in the amplitude of the sinusoidal input signal,

Figure 9 illustrates, by way of example, the performance of the first embodiment of the present PLL with respect to a step change in the phase angle of the sinusoidal input signal,

Figure 10 illustrates, by way of example, the performance of the present PLL with respect to a step change in the frequency of the sinusoidal input signal. The performance of the first and the second embodiments of the invention are shown separately through two separate graphs,

Figure 11 illustrates, by way of example, the performance of the first embodiment of the present PLL with respect to noise immunity, and finally

Figure 12 shows, by way of example, typical jitter transfer functions of P-type and Pi-type PLL systems.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to the accompanying drawings and in particular with reference to Figure 1, the enhanced phase-locked loop (PLL) system of the invention, like most conventional PLL systems, comprises a phase detection (PD) scheme 10, a loop filter (LF) 20, and a voltage-controlled oscillator (VCO) 30.

The input signal usually has a strong component at a certain frequency. The VCO 30 is commonly set to oscillate at such a frequency, thereby providing a sinusoidal output signal, the phase of which is intended to be coherent with that of the main component of the input signal.

Phase detection unit is probably the most important and at the same time the most problematic component of conventional PLLs. Very often, a multiplication unit is employed to act as a phase detector. The output signal of such a unit is usually composed of two signals whose phases are the sum and difference between the phases of the two input signals. In conventional PLLs, it is hoped that the summation term would have a frequency much higher than that of the difference and would be easily filtered out and that the difference between the phases is so small that a linear approximation is valid. In short, in conventional PLLs, it is expected that the phase detection unit and the subsequent filtering yield a signal proportional to the total phase difference between the two input signals. This is a valid expectation if the loop is already operating at or near lock frequency which, of course, is not a case to be taken as granted. Herein lies the root of all the complexity of conventional PLLs; the output signal of a multiplication unit is expected to be other that what it really is, an expectation which is valid only under the ideal condition of loop being already in its lock-in range.

The main novelty in the structure of the present PLL as depicted in Figure 1 is in the introduction of a new phase detection scheme 20 which is shown in more detail in Figure 2. The usual multiplication, or the like, process in most conventional PLLs is replaced by a subtraction 12 and a multiplication 14. More precisely, rather than multiplying the input signal by the output of the VCO to generate a signal whose phase is hopefully the difference between the phases of these two signals as is normally done in a lot of conventional PLLs, a refined variant of the VCO signal, the one coming from the amplitude adjustment unit 16, is subtracted from the input signal, using subtraction unit 12, to produce an intermediary signal. This intermediary signal is then multiplied by the output signal of the VCO 30 by multiplication unit 14 the same way as the input signal is multiplied by the output signal of the VCO in conventional PLLs with the only difference that here the output signal is not expected to be something other than what it is. Such is the case with all other arithmetics involved with the present structure: all units have defined duties realizable under all conditions.

The refinement of the output signal of the VCO 30 involved in phase detection scheme

10 of Figure 2 is performed by the amplitude adjustment unit 16. Figure 3 shows the amplitude adjustment unit 16 in detail. It is observed that both the intermediary signal, which is the output signal of the subtraction unit 12, and the output signal of the VCO 30 are used for the amplitude adjustment. The signal generated by the VCO

30 is first shifted -usually by 90°- by a phase shifter 162. Such a phase-shifted signal is then multiplied by the intermediary signal in the multiplication unit 164, the output of which is amplified and integrated by a gain/integration unit 166. The output signal of the gain/integration unit 166, when multiplied by the output signal of the phase-shifter 162 in the multiplication unit 168, generates the refined variant of the output signal of the VCO used in the phase detection unit 10.

The function of the amplitude adjustment unit 16 is basically the adjustment of the level of the output signal of the VCO 30 so that it follows the amplitude of the main component of the input signal. Its function may be termed amplitude-locking in a parallelism with the function of the rest of the present structure which should then be termed phase-locking. The speed of amplitude tracking is mostly controlled by the value of the coefficient K in the gain/integration unit 166: large values of K force the loop to track the variations in the amplitude more rapidly. There is, however, a tradeoff between speed and the error incurred in the estimated value of the amplitude. To improve such a trade-off, one can insert a low pass filter at the input or output of the gain/ integration unit 166, or in general within this unit, to smooth out the estimated value of the amplitude while not introducing significant delay into the loop. It may be clear by now that the intermediary signal thus generated is in fact the error between the input signal and the final amplitude- adjusted output signal.

Phase detection mechanism in the present structure is smart enough to leave the loop filter 20 as simple as a constant gain or at most a first order filter for most practical applications. It is most convenient to think of the loop filter 20 as a simple P- or Pi-controller as depicted in Figures 4 and 5.

In the loop filter structure of Figure 4, a simple gain (amplification) unit 22 provides the filtering process. Accordingly, the PLL structure of Figure 1 employing the loop filter 20 of Figure 4, i.e. a P-controller, constitutes the first embodiment of the present invention referred to as P-type PLL throughout this disclosure.

In the loop filter structure of Figure 5, a Pl-controller provides the filtering process. The input signal in passed through a gain unit 28 with the gain of Kp and is added to the output signal of the gain/integration unit 24, having a gain of Ki, by means of a summation unit 26 to generate the output signal. Accordingly, the PLL structure of Figure 1 employing the loop filter 20 of Figure 5, i.e. a Pi-controller, constitutes the second embodiment of the present invention referred to as Pi-type PLL throughout this disclosure.

Of course, one can use more sophisticated filters if one wills or if any application demands it, but it has been observed that a simple P- or Pi-controller provides sufficiently satisfactory results for the majority of the problems encountered. Any such embodiments of the PLL structure of Figure 1 that employ higher order loop filters are referred to as higher order PLL throughout this disclosure.

The value of Kp in the case of P-type PLL and the values of Kp and Kj in the case of Pi-type PLL primarily determine the performance of the present PLL in tracking the phase (and frequency in case of Pi-type PLL) of the main component of the input signal.

The structure of the PLL of the present invention is theoretically based on finding the best sinusoidal fit within the input signal. Equivalent to this is finding the best projection of the input signal on two orthogonal sinusoids, in which case an alternative structure for the PD 10 is deduced. Figure 6 shows such an embodiment for the PD 10. Although this alternative arrangement of the PD 10 is deducible from that of Figures 2 and 3, it presents a structurally different embodiment and is hence worthy of consideration.

With reference to Figure 6, a subtraction unit 102 provides an intermediate signal E 128 which is in fact the error between the input and the output signals. This intermediate signal is amplified by a gain K_a 104, which controls the rate of tracking in respect of amplitude convergence, and is an input signal to two multiplication units 106 and 116. The output signals of the two multiplication units 106 and 116, when integrated by integration units 108 and 118, provide two other intermediate signals S 130 and T 132 which are some measures of the energy of the input signal on two quadrature sinusoids. The intermediate signal S 130 is used as an input signal to the multiplication units 110 and 122. Likewise, the intermediate signal T 132 is used as an input signal to the multiplication units 120 and 112. Two further operations, the summation 114 and subtraction 126, conclude all the necessary operations needed in this embodiment. As before, a phase shifter 124 provides a phase-shifted variant of the output signal of the VCO 30 needed within the structure of the PD 10. In this structure, the controlling parameter in respect of frequency tracking is the value of Kι in the loop filter 20 of Figure 5. The value of Kp in the loop filter 20 of Figure 5 may be assumed to be zero in this configuration without any loss in the performance. The PLL of the present invention, when it employs the phase detection scheme presented in Figure 6, shall be called quadrature- type or Q-type PLL.

As with conventional PLLs, a frequency divider unit may be incorporated within the loop in order to move the frequency of operation of the VCO up to a harmonic of the main component of the input reference signal. Such a frequency divider unit, inserted within the feedback loop at the output of the VCO 30, will then convert the output frequency of a VCO operating at a higher frequency than that of the main component of the reference signal back to the operating frequency of the loop.

INDUSTRIAL APPLICABILITY

The embodiments of the present invention easily provide all the necessary information about the main component of the input signal locking to which is desired. The amplitude-adjusted output signal of the VCO, i.e. the output signal of the amplitude adjustment unit 16 of Figure 3, is the synthesized output signal which is locked to the desired component of the input signal. The output signal of the gain/integrator block 166 of the amplitude adjustment unit 16 of Figure 3 is the estimated amplitude of such a synthesized output signal. The input signal of the VCO 30, or the output signal of the loop filter 20, is the time-derivative of the total phase. An integrator may be added to provide the total phase if needed. Finally, in case Pi-controller is used as the loop filter, the output signal of the gain/integrator unit 24 of Figure 5 is the frequency in rad/s. Therefore, in the present invention, in addition to the fact that the synthesized output signal is in amplitude/phase/frequency lock with the desired component of its input signal, the values of amplitude, phase and frequency of the synthesized component are directly available, a fact which renders the structure an amplitude/phase/frequency estimator PLL.

The present structure of PLL may seem rather unusual and totally non-intuitive. This is true, however, it is shown that replacement of some very intuitive phase detection scheme by such a non-obvious structure resolves almost all the problems associated with conventional PLLs. One multiplication, usual with conventional PLLs, is replaced by three multiplications 14, 164, 168, one subtraction 12, and one gain/ integration 166. With today's available technology of electronic circuitry, these extra units add practically no complexity. Moreover, the structure of the loop filter may remain as simple as a P or PI controller which substantially reduces the overall complexity of the system. In exchange, a structure of PLL is achieved which works almost ideally under any condition. There is no pull-in or lock-in range involved; no complex circuitry is needed to bring the PLL to its pull-in or lock-in range; the PLL works in a range of theoretically infinitely large, a statement which is mathematically proved once and forever with no reservation. One more feature of this PLL is that the output signal is locked in both phase (and frequency) and in amplitude. Moreover, unlike conventional PLLs which provide only the synthesized output signal, the introduced PLL directly provides the estimates of the amplitude and phase (and frequency) of the desired component of the input signal in addition to the synthesized output signal. One further feature of the present PLL is its immunity to the noise which may be present in its input signal. From this aspect, the structure is very robust with respect to external conditions which may be manifested as the degree of pollution in the input signal such as white noise, harmonic distortion, disturbances, etc. It is also very robust with respect to its internal structure; small variations of the internal parameters such as K, Kp and Kι are tolerated without tangible effect on the performance of the loop.

A number of graphs are presented to aid the evaluation of the performance of the present PLL. The input signal u(t) is composed of a single sinusoidal signal «ι(t) =

A sin(ωt+θ) in most cases. The output signal y(i) is the sinusoidal signal synthesized by the VCO 30 meant to coherently follow uχ{t). The parameters K, K_P and Kj determine the speed of the PLL in tracking amplitude, phase and frequency of the input signal. In all of the graphs, the time scale is normalized so as to provide unbiased data.

Figure 7 shows, by way of example, the performance of the present PLL in its most basic mode of operation. The loop filter is taken to be a simple constant gain K_P, thus reducing the structure to its simplest form, P-type PLL. P-type PLL is meant to find the constant value of the phase of the input signal and to produce a signal whose constant phase is equal to that of the input signal. In such an embodiment of the present PLL, the frequency is more or less known and is almost fixed; the VCO is set to initially oscillate at such a frequency; small drifts from this nominal frequency are tolerated by the loop without incurring much error. If the frequency happens to be changing with time, the filter has to be a Pl-controller, thus presenting a Pi-type PLL. If the frequency of the input signal is more or less fixed and known, Pi-type PLL behaves the same way as P-type PLL does.

P-type PLL is a phase-locked loop, phase here meaning the constant phase, or equivalently the total phase provided frequency is known and almost fixed. The phase of the output signal is not simply coherent with that of the input signal, it is equal to that. Similarly, the amplitude of the output signal is equal to that of the input signal. In Fig- ure 7, the phase of the input signal is taken to be a random number between 0° to 180° and the signal is taken to be of unit amplitude. Parameters K and Kp determine the speed of the loop in catching the amplitude and phase, almost respectively. The loop generates a precise copy of its input signal; therefore, the difference between the input and output signals approaches zero in a certain number of cycles which is controllable by the values of the parameters. It is noteworthy that in conventional PLLs, such an error signal does not approach zero for two reasons: 1) the phases are not equal, but their difference is ideally a constant, and 2) the amplitudes need not be equal. The bottom graph in Figure 7 shows the variations of the phase of the synthesized output signal in more clarity.

Figure 8 shows the performance of the present PLL when a step change in amplitude of the input signal occurs. It is observed that the structure is sufficiently robust to adapt itself to the new value of the amplitude.

As was mentioned earlier, P-type PLL (and with all the more reason Pi-type PLL, of course) is meant to track the variations of the phase under more or less fixed frequency condition. Figure 9 shows the performance of the present PLL in locking to the phase of the input signal if it happens to undergo a step change.

Performance of P-type PLL is sufficiently satisfactory when the frequency of the input signal is known and fixed. However, if the frequency happens to be changing with time, it loses its accuracy and a steady state error will be introduced. The top graph in Figure 10 shows such a scenario; the frequency of the input signal undergoes a step change. The phase of the output signal is not equal to that of the input signal although it is more or less coherent with it.

Pi-type PLL may be used to eliminate the steady state error due to the step change in the frequency by employing a Pi-controller in its loop filter. This type of PLL is a more general case than P-type PLL (it reduces to P-type by letting Kj = 0) and is capable of locking the phase of its output signal to that of the input signal even if the frequency undergoes changes with time. The bottom graph in Figure 10 shows the performance of Pi-type PLL when the frequency undergoes a step change.

In cases where the frequency is constantly changing with time (such as a ramp or a sine function), the Pi-type PLL may lose its feature of generating zero-delayed output signal. However, it has been observed that it more or less preserves the phase coherence. The degree of coherence is controllable by the values of parameters.

The introduced PLL is very immune to the undesired pollution which may be present in its input signal. Figure 11 shows this feature. In this figure, the pollution is modeled by a white Gaussian noise which has reduced the signal to noise ratio (SNR) of the input signal to 20 dB. It acts similar to an adaptive notch filter. It is observed that the output signal is ten times cleaner than the input signal.

One of the representative characteristics of PLL is its jitter transfer function. It is a measure of phase lock feature of the loop and is roughly defined as the normalized value of the magnitude of time- arying phase of the output signal as a function of frequency of time- variations of the phase of the input signal. Figure 12 shows examples of jitter function of the PLL structure of the present invention. Of course, the shape of graphs are dependent upon, and are controlled by, settings of the parameters K, Kp and Ki.

In all the examples presented in this disclosure, P-type and Pi-type PLLs are used. Given the fact that Q-type PLL is a derivation from the same concept governing P-type and Pi-type PLLs, it goes without saying that similar results may be obtained using the structure presented by Q-type PLL. For the sake of brevity no such examples are presented here.

Claims

WHAT IS CLAIMED IS:

1. A phase-locked loop system comprising: a phase detector for generating a first control signal representing a function of the phase difference between a first input signal and a second input signal, said first input signal being an external input signal, locking to a component of which is sought, and said second input signal being an internal signal, phase of which is locked to the phase of said component of said first input signal; a loop filter coupled to said phase detector for generating a second control signal based on said first control signal; and a voltage-controlled oscillator coupled to said loop filter for generating said second input signal of said phase detector based on said second control signal, wherein: said first input signal of said phase detector is an input reference signal; and said second control signal is supplied to said voltage-controlled oscillator to control a free-running frequency of said voltage-controlled oscillator in order to adjust the phase and frequency of said second input signal of said phase detector to those of said component of said input reference signal.

2. A phase-locked loop system as defined in claim 1 wherein said phase detector comprises: a subtraction unit for generating an intermediary signal representing the difference between said input reference signal and a refined variant of the output signal of said voltage-controlled oscillator; a first multiplication unit for generating said first control signal representing the product of said intermediary signal and the output signal of said voltage-controlled oscillator; and an amplitude adjustment unit, wherein: said intermediary signal is the totality of the error incurred in the locking process plus the sum of all undesired components present in said input reference signal; and said refined variant of the output signal of said voltage-controlled oscillator is generated by said amplitude adjustment unit and is in lock with said component of said input reference signal in respects of amplitude, phase and frequency.

3. A phase-locked loop system as defined in claim 2 wherein said amplitude adjustment unit comprises: a phase shifter for generating a phase-shifted variant of the output signal of said voltage- controlled oscillator; a second multiplication unit for generating a third control signal representing the product of said intermediary signal and said phase shifted variant of the output signal of said voltage-controlled oscillator; a first gain/integration unit for generating a fourth control signal based on said third control signal; and a third multiplication unit for generating said refined variant of the output signal of said voltage-controlled oscillator, wherein: said fourth control signal is the estimated value of the amplitude of said component of said input reference signal; and the value of the gain of said first gain/integration unit is a positive number which primarily determines the amplitude tracking speed of the phase-locked loop defined in accordance with claim 1.

4. A phase-locked loop system as defined in claim 3 further comprising a low pass filter within said first gain/integration unit which further refines said fourth control signal to provide an improved amplitude tracking speed versus accuracy trade-off.

5. A phase-locked loop system as defined in claim 1 wherein said loop filter comprises a first constant gain unit, wherein: the value of said first constant gain is a positive number which primarily determines the constant-phase tracking speed of phase-locked loop defined in accordance with claim 1; and the output signal of said loop filter is the estimated value of the time-derivative of the total phase of said component of said input reference signal.

6. A phase-locked loop system as defined in claim 1 wherein said loop filter comprises: a second gain/integration unit for generating a fifth control signal based on said first control signal; a second constant gain unit; and a summation unit generating said second control signal representing the sum of said fifth control signal and the output signal of said second constant gain unit, wherein: the values of gain of said second gain/integration unit and said second constant gain are positive numbers which primarily determine the phase and frequency tracking speed of phase-locked loop defined in accordance with claim 1; said fifth control signal is the estimated value of the frequency of said component of said input reference signal; and the output signal of said loop filter is the estimated value of the time-derivative of the total phase of said component of said input reference signal.

7. A phase-locked loop system as defined in claim 1 wherein said loop filter is a filter of order 2 or higher, the output signal of said loop filter being the estimated value of the time-derivative of the total phase of said component of said input reference signal.

8. A phase-locked loop system as defined in claim 1 further comprising an integration unit generating an auxiliary signal based on the output signal of said loop filter wherein said auxiliary signal is the estimated value of the total phase of said component of said input reference signal.

9. A phase-locked loop system as defined in claim 1 wherein said phase detector comprises: a subtraction unit for generating an intermediate signal representing the difference between said input reference signal and a desired output signal; a third constant gain unit; a subtraction unit for generating said first control signal; and a means of generating said desired output signal, wherein: said intermediate signal is the totality of the error incurred in the locking process plus the sum of all undesired components present in said input reference signal; said desired output signal is in lock with said component of said input reference signal in respects of amplitude, phase and frequency; and the value of the gain of said third constant gain is a positive number which primarily determines the amplitude tracking speed of the phase-locked loop defined in accordance with claim 1.

10. A phase-locked loop system as defined in claim 1 further comprising a frequency divider coupled to said voltage-controlled oscillator to scale the frequency of said second input signal of said phase detector based on said second control signal.