WO2002080095A2 - Circuits for pre-charging global resources in all the free neurons of an artifical neural network - Google Patents
Circuits for pre-charging global resources in all the free neurons of an artifical neural network Download PDFInfo
- Publication number
- WO2002080095A2 WO2002080095A2 PCT/EP2002/002883 EP0202883W WO02080095A2 WO 2002080095 A2 WO2002080095 A2 WO 2002080095A2 EP 0202883 W EP0202883 W EP 0202883W WO 02080095 A2 WO02080095 A2 WO 02080095A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- free
- neuron
- global
- neurons
- ann
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Definitions
- the present invention relates to , artificial neural networks (ANNs) and more particularly to circuits for pre-charging global resources such as the category, global context/norm, MaxIF/MinlF and the like, in corresponding registers of all the free neurons of the ANN during the learning and recognition (or classification) phases .
- the present invention also encompasses improved neurons modified accordingly and ANNS resulting therefrom.
- a ZISC ANN integrated in a silicon chip includes means to receive input pattern components and global resources from a host computer (or controller) or the user and means to store them, control logic means coupled to the host computer/user to timely perform the different processing steps that are necessary for a proper ANN operation, a plurality of ZISC neurons and finally a number of buses to connect said means with each neuron of said plurality and to interconnect neurons between them.
- global resources it is meant the category, the MaxIF/MinlF, and the context/norm using the terminology adopted in the aforementioned US patents, but other parameters could be used as well. Note that MaxIF and MinlF are the maximum and the minimum values of the AIF (Actual Influence
- each ZISC neuron contains a
- Weight memory (a RAM) to store the components of an input pattern as a prototype that is required in both the learning and recognition phases, a Category register to store the category assigned to the prototype, the Context/Norm register to store the global context/norm, the AIF register to store any intermediate value between MaxIF and MinlF as a result of the AIF reduction process and finally the Distance register.
- a ZISC neuron said global resources mentioned above thus become local resources.
- daisy chain circuit indicates the state of each neuron: first free or engaged and its role is to structure the ANN as a chain of neurons working in parallel.
- ANNs built with standard ZISC neurons only the input pattern components are pre-charged in the Weight memory of the first free (or "ready to learn") neuron via a dedicated bus during the learning phase. If the input pattern is learned, this first free neuron is then declared as being engaged (or committed) and the said dedicated registers in this neuron are loaded with global resources (category, global context, ... ) to create the local resources mentioned above.
- the Category register is loaded with the category emitted by the host computer/user via the Cat bus.
- the Context/Norm register and the AIF register are updated via two buses: the Context/Norm bus and the MaxIF/MinlF bus respectively.
- the AIF Register is loaded via the MaxIF/MinlF bus. Note that the distance is not loaded in the Distance register during the learning phase because the distance is only evaluated during the recognition phase.
- Fig. 1 schematically shows the architecture of a ZISC ANN and the basic data transmission principles to apply the input pattern components and the global resources to the standard ZISC neurons such as disclosed in US patent 5,621,863 including the pre-charge and the daisy chain features mentioned above.
- a simplified ANN referenced 10 including a plurality of ZISC neurons 11-1 to 11-n and some global resources that are common to all the neurons, i.e. data that must be simultaneously applied to all the neurons of the ANN.
- the global resource is either stored in a register (e.g. the Context register), or sent by the host computer/user (e.g. the category) before being transmitted to the neurons.
- a register e.g. the Context register
- the registers lodged in each neuron that are mentioned herein have not been shown in Fig. 1.
- Each standard ZISC neuron, e.g. 11-1 incorporates a daisy chain circuit, e.g. 12-1, to distinguish its state as indicated above.
- the Comp bus 13 transports the input pattern components to pre-charge them in the first free neuron.
- a category is assigned to it via the Cat bus 14.
- the MaxIF which is required in each neuron during the learning is stored in the AIF register via the MaxIF/MinlF bus 15.
- MinlF which is required in a very few cases is made available in each neuron whenever necessary thanks to multiplexer 18 depending upon a control signal (not shown) generated by the control logic circuit 19.
- each neuron must know the global context/norm value (this value can be changed at any time) which is usually stored in the global Context/Norm register.
- Context/Norm bus 16 is used to that end to apply this common value to all neurons 11-1 to 11-n for local storage thereof, but it is also used for comparison purposes to compare the global context value and the local context value . If the global context matches the local context, the neuron is said "Selected", i.e. it is allowed to participate to the recognition of input patterns.
- Add/Ctl bus 17 interconnects the Control logic circuit 19 with each of said plurality of neurons. It transports the necessary addresses and control signals under host computer/user supervision. Still considering Fig.
- DCI represents the state of the previous neuron in the chain
- DCO represents the state of the neuron in consideration.
- the notations used to designate the different elements shown in Fig. 1 are substantially the same as the notations used in the aforementioned US patents or can be easily derived therefrom.
- a ZISC ANN may include a very large number of standard ZISC neurons (up to 1000 and even more) , the complexity of the interconnect network can dramatically increase, as a result of the length increase of the buses 13-17. In turn, it is required to design either a few very big drivers (or a great number of small drivers) to supply the high current levels that are needed. Besides the room necessary to integrate such big drivers in the silicon chip, there is also a not negligible risk of failures in making so important network of electric wires at the silicon chip surface.
- Global resources (category, MaxIF/MinlF, context/norm, ... ) are applied on a single bus common for all global resources, referred to as the Data bus, via a selector, which is under supervision of the control logic circuit of the ANN.
- the Data bus is connected in parallel to said dedicated registers in all neurons.
- Each dedicated register is controlled by its own Write Enable (WE) signal.
- WE Write Enable
- the WE signal is generated by a pre-charge circuit comprised of an address decoder connected to said control logic circuit via an address/control bus, referred to as the Add/Ctl bus, and an AND gate which receives the output of said address decoder on a first input and a FREE signal generated by a daisy chain circuit on the other input.
- the role of the FREE signal is to indicate whether the neuron is free or not.
- an identifier typically an address
- the selector applies the updated value on the Data bus and simultaneously, the control logic applies this address (or an address related thereto) on the Add/Ctl bus to identify which global resource is being sent to all neurons .
- the WE signal enables only the corresponding dedicated register of all the free neurons to load said updated global resource therein as a local resource.
- the method and circuits of the present invention allows to maintain an exact and permanent correspondence between global resources and corresponding local resources, it is no longer necessary to load the global resources at each learning of a neuron, since they are already pre-loaded. Therefore, the proposed solution allows to reduce the number of input buses (in the present case only two buses are now necessary instead of the 5 buses previously used in the standard ZISC ANN) without increasing the number of clock cycles
- Fig. 1 schematically shows the architecture of a conventional ANN constructed with standard ZISC neurons to emphasize the role of the four input buses that are necessary to distribute the input pattern components and the different global resources to all the neurons of the ANN.
- Fig. 2 shows the architecture of the ANN that now only requires one bus and a selector to distribute the input pattern components and the different global resources to all the neurons of the ANN according to the present invention.
- Figs. 3A, 3B and 3C show the contents of two global registers and corresponding local registers for four neurons of an ANN respectively after reset, learning and MaxIF updating.
- Figs . 4A and 4B show the data flowchart for two global resources, MaxIF and context respectively, to illustrate the method of the present invention.
- Fig. 5 shows the innovative daisy chain circuit placed in each improved ZISC neuron which is adapted to generate a signal indicating whether the neuron is free or not according to the present invention.
- Fig. 6 shows the innovative pre-charge circuit placed in each neuron for pre-charging one global resource in the corresponding dedicated register of all the improved ZISC neurons of the ANN that are free according to the present invention.
- Figs. 7A and 7B respectively show a more detailed construction of the pre-charge circuit of Fig. 6 when it is adapted to process the MaxIF and the global context.
- Fig. 8 shows a more detailed construction of the pre-charge circuit of Fig. 6 when it is adapted to process both the MaxIF and the global context in a single circuit.
- each standard ZISC neuron which receives each of said global resources as an input signal applies said updated global resource on a single data bus that is thus adapted to transport all said global resources and the input pattern components upon control logic circuit supervision.
- the control logic circuit applies a specific address on the Add/Ctl bus 17 to pre-charge the updated global resource in the corresponding dedicated register of all the free neurons of the ANN for local storage.
- Each neuron includes an innovative pre-charge circuit, the main element of which is a specific address decoder and a new daisy chain circuit that is now adapted to generate a signal to identify all the free neurons in the ANN. Note that an address decoder already exists in each standard ZISC neuron, but it has been implemented for a different purpose, for instance, to address the local AIF register when a determined neuron must be accessed.
- the innovative pre-charge and daisy chain circuits of the present invention that are placed in each improved ZISC neuron thus allows to load a global resource in all the free neurons as soon as it is updated.
- a global resource can be modified at any time, for all the free neurons of the ANN, there will be a permanent and exact correspondence between each of the global resources and its corresponding local resource stored in a dedicated register.
- the pre-charge of the input pattern components in the first free improved ZISC neuron is concerned, there is no significant change with respect to the standard ZISC neuron, except that there is no longer a specific Comp bus to transport them, but said single data bus will be used instead.
- FIG. 2 illustrates this new approach.
- Fig. 2 there is shown the architecture referenced 20 of an ANN built with improved ZISC neurons now referenced 11 '-1 to 11 '-n.
- each global resource (category, MaxIF/MinlF, context/norm) and the input pattern components are applied to a selector referenced 18 ' .
- the updated global resource is sent on a common bus, labeled Data bus and referenced 13', via selector 18 ' under supervision of the control logic circuit 19.
- Each neuron e.g.
- 11 '-1 is provided with an innovative daisy chain circuit, e.g. 12 ' -1 that is capable to generate a FREE signal indicating whether the neuron is free or not and a pre-charge circuit, e.g. 21-1, adapted to enable the loading of the global resource that is present on the Data bus 13 ' .
- control logic circuit 19 It is the role of control logic circuit 19 to apply the adequate Address on the Add/Ctl bus 17 to perform said loading of the global resource in the corresponding register of all the improved ZISC neurons that are free where it becomes a local resource.
- the ADDRESS related to a determined global resource e.g.
- MaxIF that was sent by the host computer was only used to load this global resource in its corresponding global register (if any) , e.g. the MaxIF global register.
- this ADDRESS will be exploited by the control logic circuit 19, which in turn emits an address derived therefrom, referred to as the Address, used to load this global resource in the AIF register of all the neurons of the ANN that are free.
- this Address permits to identify the nature of the global resource that is present on the Data bus 13' (remind that it is designed to transport all the global resources) .
- Figs. 3A, 3B and 3C respectively show the content of two global registers containing global resources : MaxIF and global context for the first four improved ZISC neurons 11 ' -1 to 11 '-4 (for the sake of simplicity) after reset, learning an input pattern and a MaxIF update operation.
- Fig. 3A there is shown a partial configuration of ANN 20 after the reset operation.
- Global resource registers are set to the default values, for example MaxIF is set to 1000 and the global context is set to 0.
- the reset operation comprises several steps using the Data bus 13 ' to load said values into the corresponding local registers of said four free neurons, i.e. the AIF register and the Context/Norm register, referred to hereinbelow as the CXT register for the sake of simplicity.
- Fig. 3B shows the status of the Fig. 3A configuration after a learning phase so that some neurons have been engaged, in this case, two neurons.
- the FREE signal is set to 0 while for the two free neurons 11 '-3 and 11 '-4 the FREE signal is still set to 1.
- all the neurons have their AIF set to 1000 except neuron 11 '-2 for which it is assumed that its AIF has been reduced to 800 during a reduction process (internal) . Note that, during the learning phase, none clock cycle is required to transmit the AIF and the global context values because they were already loaded after the reset operation.
- Fig. 3C shows the Fig. 3B configuration after an update of the MaxIF value to 50.
- the content of the local AIF register in the two free neurons 11 '-3 and 11 '-4 is updated. Because, this change from 1000 to 50 occured during the update operation of the global resource, no extra time was required.
- Fig. 4A shows the flow chart referenced 22 for an update of the MaxIF value. This flow chart explains how to maintain an exact correspondence (mirror effect) between the MaxIF value (a global resource) and the content of the AIF register (a local resource) in all the free neurons.
- a test is made in block 23 to determine if the global resource is MaxIF based upon the ADDRESS (assigned to each global resource by the host computer as mentioned above) .
- this MaxIF value is stored in the MaxIF register as a global resource (block 24) and the MaxIF value is made available to all the neurons of the ANN through a single bus, the Data bus 13' (which according to the present invention transports all the global resources) and the Address is applied on the Add/Ctl bus 17 (block 25) . Then, the following process is started for each neuron. In each neuron, the Address is tested in block 26, if this Address does not match with a MaxIF update, it is not needed to also update the content of the local resource (AIF register) . On the contrary, if this address corresponds to a MaxIF update, the local value must be updated to have the desired mirror effect between the global and local resources, only if the neuron is free. Therefore, the state of the neuron is tested in block 27 and if found free, the content of the AIF register is updated with MaxIF in block 28.
- Fig. 4B shows the process flow chart 29 for an update of the global context. Likewise, this flow chart explains how to maintain an exact correspondence (mirror effect) between the global context resource and the contents of the local Context registers in all the free neurons.
- a test is made in block 30 to determine if the global resource is the global context based upon the ADDRESS. If yes, this global context value is stored in the global Context register as a global resource (block 31) and the global context is made available to all the neurons of the ANN through Data bus 13 ' and the Address is applied on the Add/Ctl bus 17 (block 32). Then the following process is started for each neuron.
- the Address present on the Add/Ctl bus 17 is tested in block 33, if this address does not match with a global context update, it is not needed to update the content of the local resource (Context register) . On the contrary, if this address corresponds to a global context update, the local value must be updated to have the desired mirror effect between the local and global resources, only if the neuron is free. Therefore, the state of the neuron is tested in block 34 and if found free, the content of the Context register is updated with the global context in block 35. However, because it is necessary for engaged neurons to compare the content of the local Context (CXT) register with the content of the global Context register in order to set the flag "Selected", needed in the control logic circuit, a comparison in made in block 36.
- CXT local Context
- Fig. 5 shows the innovative daisy chain circuit placed in each improved ZISC neuron according to the present invention which is now adapted to generate a signal (FREE) indicating whether the neuron is free or not.
- the FREE signal is thus different from the RS signal generated by the daisy chain circuit placed in the standard ZISC neuron which only flags the first free neuron in the chain.
- the innovative daisy chain circuit 12' is still serially connected between the two adjacent daisy chain circuits of the previous and next improved ZISC neurons, so that all the neurons of the ANN form a chain.
- the daisy chain circuit 12' is basically identical to circuit 600 described in the aforementioned US patent 5,710,869. It is built around a 1-bit register 37 controlled by a store enable signal (ST) which is active at initialization or during the learning phase when a new neuron is engaged.
- ST store enable signal
- the DCI signal is applied to the first input of a two-way AND gate 38 whose other input receives the RESET_ signal.
- the output of AND gate 38 is connected to the input of register 37.
- circuit 12' still includes a control logic block referenced 40 which consists of a 2-way XOR and 2-way AND gates referenced 41 and 42 to generate the RS and CO signals respectively.
- Gate 41 performs the XORing of signals DCI and DCO and gate 42 performs the ANDing of signals DCO and NS (NS is high for a selected neuron) .
- the novelty consists in the addition of inverter 43 in block 40 which is connected to the output of register 37 and generates the FREE signal which is essential to implement the present invention.
- the operation of daisy chain circuit 12 ' is thus substantially the same as circuit 600.
- the following table illustrates the different neuron states as a function of the DCI/DCO signal combinations.
- FIG. 6 schematically shows the partial architecture referenced 44 of an ANN built with improved ZISC neurons.
- the global resources are grouped in a block 45 shown in dotted line, usually stored in registers, the outputs of which are connected to selector 18' (see Fig. 2).
- Fig. 6 further shows a local dedicated register 46 and a block 47 comprised of the innovative pre-charge and daisy chain circuits of the present invention referenced 21 and 12' respectively (see Fig. 2) .
- the role of pre-charge circuit 21 is to enable the global resource present on the Data bus 13 ' (which transports all the global resources without distinction) to be loaded into the local register 46.
- Pre-charge circuit 21 is essential in that it generates a signal WE (stands for Write Enable) synchronized with the global resource update that allows or not to load the global resource in the local register 46.
- Pre-charge circuit 21 consists of an address decoder 49 which decodes the Address (present on the Add/Ctl bus 17) attached to each global resource and of a 2-way AND gate 50. Decoder 49 is connected to the control logic circuit 19 via the Add/Ctl bus 17. Its output is connected to a first input of AND gate 50, the other input receives the FREE signal from the daisy chain circuit 12 ' . When the address decoder 49 recognizes an Address on the Add/Ctl bus 17 matching the global resource present on Data bus 13 ' , the signal output by decoder 49 is active, e.g.
- the innovative pre-charge circuit 21 schematically shown in Fig. 6 has been designed to maintain the desired exact and permanent correspondence between global resources and local resources, each time a global resource is updated. According to the present invention, as soon as a global resource is updated by the host computer/user, its value is loaded in the corresponding local register in all the free neurons of the ANN.
- Figs . 7A and 7B respectively show a more detailed construction of the pre-charge circuit of Fig. 6 when adapted to process the MaxIF and the global context .
- Fig. 7A basically implements the flow chart of Fig. 4A in hardware.
- the architecture shown in FIG. 7A is derived from the partial architecture referenced 44 shown in Fig. 6 but is more particularly adapted to process the MaxIF.
- the partial architecture of the ANN now referenced 51 includes a few changes with respect to the Fig. 6 architecture to take into account the specificity of the AIF reduction process.
- the pre-charge circuit 21 is the same and its output signal is ORed in a 2-way OR gate 53 with the signal which results of ANDing the CO and RA signals in 2-way AND gate 54.
- the CO signal is high when the neuron is engaged (committed) and the RA signal is high when the AIF reduction process is active.
- the data that can be stored in local register 55 is either the data present on the Data bus 13 ' or the distance stored in the Distance register 56 via multiplexor 57 (under neuron control logic supervision) . Therefore, in this case, the WE signal which is output from OR gate 53 allows to store either data in the local AIF register 55.
- Fig. 7B basically implements the flow chart of Fig. 4B in hardware.
- the architecture shown in FIG. 7B is derived from the partial architecture referenced 44 shown in Fig. 6 but is more particularly adapted to process the global context.
- the partial architecture of the ANN now referenced 58 includes a few changes with respect to the Fig. 6 architecture to take into account the specificity of a comparison which is required in this case.
- the pre-charge circuit 21 is the same and its output signal WE is directly transmitted to the local register, in this case the context/norm (CXT) register 60.
- CXT context/norm
- the decoded signal that is output from Address decoder 49 is ANDed with the CO signal in 2-way AND gate 61 and the signal which is output therefrom controls a 1-bit register 62 which stores a "flag" to indicate if the neuron is "Selected” or not.
- the global resource present on Data bus 13' and the content of the CXT register 60 are compared in compare circuit 63.
- the result of the comparison (which depends upon there is a match or not) is stored as the flag bit in register 62. This flag bit is high thus only for engaged neurons when the Address is a global context address.
- Fig. 8 is directly derived from the partial architectures referenced 51 and 58 shown in Figs. 7A and 7B respectively but is more particularly adapted to process both the MaxIF and the global context using a single pre-charge circuit.
- the partial architecture of the ANN now referenced 64 is provided with a block 65 which is characterized by a single address decoder circuit 66 that combines both decoder 49' (MaxIF address) and 49" (global context address)).
- decoder 49' MaxIF address
- 49" global context address
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Multi Processors (AREA)
- Character Discrimination (AREA)
- Computer And Data Communications (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002578242A JP2004531811A (en) | 2001-03-30 | 2002-02-25 | Circuit for precharging global resources in all free neurons of an artificial neural network |
AU2002304860A AU2002304860A1 (en) | 2001-03-30 | 2002-02-25 | Circuits for pre-charging global resources in all the free neurons of an artifical neural network |
EP02732490A EP1405262A2 (en) | 2001-03-30 | 2002-02-25 | Circuits for pre-charging global resources in all the free neurons of an artificial neural network |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01480027.0 | 2001-03-30 | ||
EP01480027 | 2001-03-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002080095A2 true WO2002080095A2 (en) | 2002-10-10 |
WO2002080095A3 WO2002080095A3 (en) | 2004-01-29 |
Family
ID=8183386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/002883 WO2002080095A2 (en) | 2001-03-30 | 2002-02-25 | Circuits for pre-charging global resources in all the free neurons of an artifical neural network |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1405262A2 (en) |
JP (1) | JP2004531811A (en) |
AU (1) | AU2002304860A1 (en) |
WO (1) | WO2002080095A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108268946A (en) * | 2016-12-31 | 2018-07-10 | 上海兆芯集成电路有限公司 | The neural network unit of circulator with array-width sectional |
CN110764444A (en) * | 2019-10-10 | 2020-02-07 | 苏州浪潮智能科技有限公司 | Control system, switch, and method for controlling execution device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0378115A2 (en) * | 1989-01-06 | 1990-07-18 | Hitachi, Ltd. | Neural computer |
US5201029A (en) * | 1988-10-24 | 1993-04-06 | U.S. Philips Corporation | Digital data processing apparatus using daisy chain control |
US5285524A (en) * | 1990-12-24 | 1994-02-08 | Eastman Kodak Company | Neural network with daisy chain control |
US5621863A (en) * | 1994-07-28 | 1997-04-15 | International Business Machines Corporation | Neuron circuit |
US5649069A (en) * | 1992-02-26 | 1997-07-15 | U.S. Philips Corporation | Neural net having a neural processor with distributed synaptic cells |
-
2002
- 2002-02-25 EP EP02732490A patent/EP1405262A2/en not_active Withdrawn
- 2002-02-25 AU AU2002304860A patent/AU2002304860A1/en not_active Abandoned
- 2002-02-25 WO PCT/EP2002/002883 patent/WO2002080095A2/en not_active Application Discontinuation
- 2002-02-25 JP JP2002578242A patent/JP2004531811A/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5201029A (en) * | 1988-10-24 | 1993-04-06 | U.S. Philips Corporation | Digital data processing apparatus using daisy chain control |
EP0378115A2 (en) * | 1989-01-06 | 1990-07-18 | Hitachi, Ltd. | Neural computer |
US5285524A (en) * | 1990-12-24 | 1994-02-08 | Eastman Kodak Company | Neural network with daisy chain control |
US5649069A (en) * | 1992-02-26 | 1997-07-15 | U.S. Philips Corporation | Neural net having a neural processor with distributed synaptic cells |
US5621863A (en) * | 1994-07-28 | 1997-04-15 | International Business Machines Corporation | Neuron circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108268946A (en) * | 2016-12-31 | 2018-07-10 | 上海兆芯集成电路有限公司 | The neural network unit of circulator with array-width sectional |
CN110764444A (en) * | 2019-10-10 | 2020-02-07 | 苏州浪潮智能科技有限公司 | Control system, switch, and method for controlling execution device |
US11650950B2 (en) | 2019-10-10 | 2023-05-16 | Inspur Suzhou Intelligent Technology Co., Ltd. | Control system, switch, and method for controlling execution device |
Also Published As
Publication number | Publication date |
---|---|
WO2002080095A3 (en) | 2004-01-29 |
JP2004531811A (en) | 2004-10-14 |
EP1405262A2 (en) | 2004-04-07 |
AU2002304860A1 (en) | 2002-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5204938A (en) | Method of implementing a neural network on a digital computer | |
US10909452B2 (en) | Methods and systems for power management in a pattern recognition processing system | |
US5751987A (en) | Distributed processing memory chip with embedded logic having both data memory and broadcast memory | |
US10949743B2 (en) | Method and system for implementing reinforcement learning agent using reinforcement learning processor | |
US5325510A (en) | Multiprocessor system and architecture with a computation system for minimizing duplicate read requests | |
JP3407265B2 (en) | Neuron circuit | |
EP0694855B1 (en) | Search/sort circuit for neural networks | |
EP0694856B1 (en) | Daisy chain circuit for serial connection of neuron circuits | |
JP3798451B2 (en) | Pre-load circuit | |
US10789182B2 (en) | System and method for individual addressing | |
US6523018B1 (en) | Neural chip architecture and neural networks incorporated therein | |
JP2005500621A (en) | Switch / network adapter port for cluster computers using a series of multi-adaptive processors in dual inline memory module format | |
WO1994003860A1 (en) | Massively parallel computer including auxiliary vector processor | |
JPH04507027A (en) | PLAN - Pyramid learning architecture/neurocomputer | |
US20230176999A1 (en) | Devices for time division multiplexing of state machine engine signals | |
JPS6250856B2 (en) | ||
US5907693A (en) | Autonomously cycling data processing architecture | |
WO2002080095A2 (en) | Circuits for pre-charging global resources in all the free neurons of an artifical neural network | |
US4733393A (en) | Test method and apparatus for cellular array processor chip | |
EP0223849A1 (en) | Super-computer system architectures. | |
KR20020006586A (en) | Method and circuits for associating a norm to each component of an input pattern presented to a neural network | |
JPH06325011A (en) | Neurocomputer | |
JPH06139222A (en) | Neuro computer | |
JPH0820946B2 (en) | Programmable controller |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2002578242 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002732490 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWP | Wipo information: published in national office |
Ref document number: 2002732490 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2002732490 Country of ref document: EP |