WO2002045146A1 - Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same - Google Patents

Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same Download PDF

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Publication number
WO2002045146A1
WO2002045146A1 PCT/KR2001/000473 KR0100473W WO0245146A1 WO 2002045146 A1 WO2002045146 A1 WO 2002045146A1 KR 0100473 W KR0100473 W KR 0100473W WO 0245146 A1 WO0245146 A1 WO 0245146A1
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WO
WIPO (PCT)
Prior art keywords
silicon substrate
layer
porous silicon
substrate
silicon layer
Prior art date
Application number
PCT/KR2001/000473
Other languages
French (fr)
Inventor
Choong-Mo Nam
Original Assignee
Telephus, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2000-0072012A external-priority patent/KR100405194B1/en
Priority claimed from KR10-2001-0001140A external-priority patent/KR100466224B1/en
Application filed by Telephus, Inc. filed Critical Telephus, Inc.
Priority to AU2001248861A priority Critical patent/AU2001248861A1/en
Publication of WO2002045146A1 publication Critical patent/WO2002045146A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Definitions

  • the silicon substrate typically has an insulating layer formed thereon by chemical vapor deposition (CVD), or an oxidized porous silicon layer formed by anodization, and a passivation element is provided on the insulating layer or the oxidized porous silicon layer before arranging chips.
  • CVD chemical vapor deposition
  • the oxidized porous silicon layer has high thermal conductivity and a low specific dielectric coefficient relative to dielectric substances such as polyimide, and a low dielectric loss as an oxidized silicon layer. Therefore, preferred is a method for forming an oxidized porous silicon layer on the silicon substrate.
  • this method not only has difficulty in obtaining a desired pattern because the porous silicon layer 3 is formed deep underneath the photoresist 2 as illustrated in FIG. 1 b, but also causes damage to the oxidized porous silicon layer 4 which is poor in chemical resistance during the step of removing the photoresist 2 used as a mask.
  • the photoresist 20 is removed using a chemical substance such as acetone, methanol, etc. without damage to the silicon substrate 10, which has a high chemical resistance.

Abstract

Disclosed is a fabrication method of a selectively oxidized porous silicon layer that includes the steps of: forming a defined photoresist pattern on a P-type silicon substrate; doping an N-type impurity in the silicon substrate by ion implantation using the photoresist pattern as a mask; removing the photoresist pattern; anodizing the silicon substrate to selectively form a porous silicon layer on the surface of the silicon substrate other than at the N-type impurity-doped region; and oxidizing the porous silicon layer into an oxidized porous silicon layer, thereby providing the selectively oxidized porous silicon layer of high quality, precisely formed and without damage, by ion implantation.

Description

Fabrication Method of Selectively Oxidized Porous Silicon (SOPS) Layer and Multi-chip Package Using the Same
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a fabrication method of an oxidized porous silicon layer, and a multi-chip package using the same.
(b) Description of the Related Art
It has become common to use a silicon substrate as a substrate for a multi-chip package, because the silicon substrate has advantages over alumina substrates in regard to inexpensiveness and high thermal conductivity, it allows direct formation of an active device such as a transistor or IC, and it can be readily put to practical use owing to great progress of semiconductor fabrication technology using the silicon substrate. However, the silicon substrate forms a semiconductor of poor insulation characteristics and thus is hardly used in the ultrahigh frequency band.
For use as a substrate for multi-chip packages, the silicon substrate typically has an insulating layer formed thereon by chemical vapor deposition (CVD), or an oxidized porous silicon layer formed by anodization, and a passivation element is provided on the insulating layer or the oxidized porous silicon layer before arranging chips. In particular, the oxidized porous silicon layer has high thermal conductivity and a low specific dielectric coefficient relative to dielectric substances such as polyimide, and a low dielectric loss as an oxidized silicon layer. Therefore, preferred is a method for forming an oxidized porous silicon layer on the silicon substrate.
However, when the oxidized porous silicon layer is formed on the entire surface of the silicon substrate, there is a problem in dissipating heat generated from the chips. In an attempt to overcome this problem, a method has been proposed for forming an oxidized porous silicon layer selectively on a part of the silicon substrate, to provide a direct electrical connection between the silicon substrate having a high thermal conductivity and a chip.
For example, a fabrication method of a selectively oxidized porous silicon layer using a photoresist is disclosed in Korean Patent Application No. 1996-
035061 , which will be described below with reference to FIGS. 1 a, 1 b and 1 c. FIGS. 1 a, 1 b and 1 c are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to prior art.
First, as shown in FIG. 1 a, a photoresist 2 is applied on a silicon substrate 1 and then subjected to exposure and development to form a desired photoresist pattern.
As shown in FIG. 1 b, the photoresist 2 is used as a mask in anodizing the silicon substrate 1 to form a porous silicon layer 3 on a part of the silicon substrate 1 that is not covered with the photoresist 2. The photoresist 2 is then removed. Subsequently, as shown in FIG. 1 c, the porous silicon layer 3 is oxidized to form an oxidized porous silicon layer 4.
However, this method not only has difficulty in obtaining a desired pattern because the porous silicon layer 3 is formed deep underneath the photoresist 2 as illustrated in FIG. 1 b, but also causes damage to the oxidized porous silicon layer 4 which is poor in chemical resistance during the step of removing the photoresist 2 used as a mask.
Another example of a fabrication method of a selectively oxidized porous silicon layer is disclosed in Korea Patent Application No. 1994-26395, which will be described below with reference to FIG. 2. FIG. 2 is a cross-sectional view of an MMIC (Monolithic Microwave
IC) substrate having a porous silicon substrate layer selectively formed thereon according to prior art.
Referring to FIG. 2, a porous silicon layer or an oxidized porous silicon layer 100 having good insulation characteristics is formed on a silicon substrate while a silicon layer 150 to be an active region remains intact, thus completely isolating the active region (silicon layer) 150. An insulating layer 230, removable if necessary, is used as a protective layer to prevent the surface of the PSL (Porous Silicon Layer) or OPSL (Oxidized Porous Silicon Layer) 100 being exposed. On the insulating layer 230 are formed a transmission line 170, a passivation element 190, etc. A plane electrode 16 is formed underneath the PSL or OPSL 100 in order to apply a reference voltage to the circuitry.
This substrate has the oxidized porous silicon layer 100 formed deep underneath an impurity-doped region so as to completely isolate the active region 150. Unfortunately, using the substrate for a multi-chip package still involves a problem in dissipating heat generated from the chips, when the oxidized porous silicon layer 100 is formed underneath the active region 150.
Therefore, a photoetching step is additionally required in forming the pattern of the insulating layer exclusively covering the active region 150 in order to prevent the active region 150 from being damaged during the anodization of the silicon substrate. This increases the complexity of the process as well as the production cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above problems and to provide a fabrication method of a selectively oxidized porous silicon layer in an elaborate pattern.
It is another object of the present invention to provide a multi-chip package obtained by using a selectively oxidized porous silicon layer of high quality without damage.
To achieve the above objects, the present invention involves formation of a doped region on a silicon substrate and anodization of the silicon substrate.
More specifically, there is provided a fabrication method of a selectively oxidized porous silicon layer, including the steps of: (a) forming a photoresist pattern on a silicon substrate; (b) doping an impurity in the silicon substrate by ion implantation using the photoresist pattern as a mask; (c) removing the photoresist pattern; (d) anodizing the silicon substrate; and (e) oxidizing the silicon substrate.
Preferably, the silicon substrate is a P-type substrate and the impurity doped in the step (b) is an N-type impurity.
This method can be used to fabricate a multi-chip package including: a silicon substrate; an impurity-doped region formed in a defined pattern on the surface of the silicon substrate; and an oxidized porous silicon layer formed on a portion of the silicon substrate other than at the impurity-doped region.
Preferably, the silicon substrate is a P-type substrate and the impurity-doped region has an N-type impurity. The multi-chip package may further include a bumper formed on the silicon substrate, and a flip chip disposed on the bumper. Alternatively, the multi-chip package may further include: a metal coating electrode formed on the silicon substrate; an electric device formed on the silicon substrate, and including at least one of a passive device and an active device; a bare chip formed on the metal coating electrode; and a bonding wire for connecting the bare chip to the electric device formed on the silicon substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention:
FIGS. 1 a, 1 b and 1 c are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to prior art;
FIG. 2 is a cross-sectional view of an MMIC substrate having a porous silicon substrate layer selectively formed thereon according to prior art;
FIGS. 3a to 3e are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to a first embodiment of the present invention; FIGS. 4a to 4h are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to a second embodiment of the present invention;
FIGS. 5a to 5i are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to a third embodiment of the present invention; and
FIGS. 6 and 7 are cross-sectional views of a flip-chip type multi-chip package and a wire-bonding type multi-chip package obtained using the oxidized porous silicon layer selectively formed according to the embodiments of the present invention, respectively.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the following detailed description, only the preferred embodiments of the invention have been shown and described, simply by way of illustration of the best modes contemplated by the inventor(s) of carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.
FIGS. 3a to 3e are sequential cross-sectional views illustrating a fabrication method of a thick selectively oxidized porous silicon layer according to a first embodiment of the present invention.
First, as shown in FIG. 3a, a photoresist 20 is applied on a P-type silicon substrate 10 and then subjected to exposure and development using a mask, thereby forming a desired pattern of the photoresist 20 that covers a portion to be an oxidized porous silicon layer.
As shown in FIG. 3b, an N-type impurity, such as phosphor (P), is introduced into the exposed silicon substrate 10 not covered with the pattern of the photoresist 20 by ion implantation to form an N-type well 11. The impurity concentration exceeds 5E13/cm3. As shown in FIG. 3c, the photoresist 20 is removed using a chemical substance such as acetone, methanol, etc. without damage to the silicon substrate 10, which has a high chemical resistance.
As shown in FIG. 3d, the silicon substrate 10 is anodized to form a porous silicon layer 30. Preferably, the porous silicon layer 30 is deposited to a thickness of more than about 20 μm in order to avoid a loss of the transmission line in the ultrahigh frequency band that may otherwise occur due to the reverse conducting characteristic of the silicon substrate.
Subsequently, as shown in FIG. 3e, the porous silicon layer 30 is converted to an oxidized porous silicon layer 31 by oxidation. A thin (about 1 ,500 A) oxide layer is also formed on a portion 11 having the N-type well formed therein. Here, the oxide layer hardly affects heat dissipation to the portion 11 because of its small thickness. Accordingly, the oxidized porous silicon layer 31 thus obtained has a pattern as defined by the pattern of the photoresist 20 as illustrated in FIG. 3a.
FIGS. 4a to 4h are sequential cross-sectional views illustrating a fabrication method of a thick selectively oxidized porous silicon layer according to a second embodiment of the present invention.
First, as shown in FIG. 4a, a P-type silicon substrate 10 is heated in a furnace to form an oxidized silicon layer 12 to a thickness of about 3,000 A on both sides of the silicon substrate 10. As shown in FIG. 4b, a photoresist 20 is applied on the upper oxidized silicon layer 12 and then subjected to exposure and development using a photomask of a defined pattern, thereby forming a desired pattern of the photoresist 20 that covers a portion to be an oxidized porous silicon layer. Subsequently, the oxidized silicon layer 12 is etched using the pattern of the photoresist 20 as an etching-blocking layer to expose the silicon substrate 10. Etching of the oxidized silicon layer 12 is conducted by RIE (Reactive Ion Etching).
As shown in FIG. 4c, the photoresist 20 is removed using a chemical substance such as acetone, methanol, etc. without damage to the silicon substrate 10, which has a high chemical resistance.
As shown in FIG. 4d, with the silicon substrate placed in a diffusion furnace, an N-type impurity, such as phosphor (P), is diffused into the exposed silicon substrate 10 not covered with the photoresist 20 by ion implantation to form an N-type well 11. Preferably, the impurity concentration exceeds 5E13/cm3. As shown in FIG. 4e, after removal of the oxidized silicon layer 12 from both sides of the silicon substrate 10 by etching, aluminum is deposited on the bottom surface of the silicon substrate 10 to form an anodized electrode 13. Here, the oxidized silicon layer 12 is etched using a hydrofluoric acid (HF) solution. As shown in FIG. 4f, the silicon substrate 10 is anodized to form a porous silicon layer 30. Preferably, the porous silicon layer 30 is deposited to a thickness of more than about 20 μm in order to avoid a loss of the transmission line in the ultrahigh frequency band that may otherwise occur due to the reverse conducting characteristic of the silicon substrate. Meanwhile, the portion 11 having the N-type well formed therein remains intact under anodization.
As shown in FIG. 4g, the anodized electrode 13 is removed by etching. Here, removal of the anodized electrode 13 is conducted using an etching solution prepared by mixing hydrofluoric acid (HF) and ultra pure water at a mixing ratio of 1 :10, because the anodized electrode 13 comprises aluminum.
Subsequently, as shown in FIG. 4h, the porous silicon layer 30 is oxidized into an oxidized porous silicon layer 31. A thin (about 1 ,500 A) oxide layer is also formed on a portion 11 having the N-type well formed therein. The oxide layer hardly affects heat dissipation to the portion 11 because of its small thickness. Accordingly, the oxidized porous silicon layer 31 thus obtained has a pattern as defined by the pattern of the photoresist 20 as illustrated in FIG. 4b.
As described above, the present invention provides a selectively oxidized porous silicon layer of an elaborate pattern on the silicon substrate without damage. Also, the present invention permits a device such as a transistor to be provided in the N-type well, formed together with the oxidized porous silicon layer, so that the silicon substrate can be used as a chip as well as a base for a package.
FIGS. 5a to 5i are sequential cross-sectional views illustrating a fabrication method of a selectively oxidized porous silicon layer according to a third embodiment of the present invention.
First, as shown in FIG. 5a, a silicon nitride layer 14 is deposited to a thickness of about 3,000 A on both sides of a P-type silicon substrate 10.
As shown in FIG. 5b, a photoresist 20 is applied on the upper silicon nitride layer 14 and then subjected to exposure and development using a photomask of a defined pattern, thereby forming a desired pattern of the photoresist 20 that exposes a portion to be an oxidized porous silicon layer. Subsequently, the exposed silicon nitride layer 14 is etched using the pattern of the photoresist 20 as an etching-blocking layer to expose the silicon substrate 10. Etching of the silicon nitride layer 14 is conducted by RIE.
As shown in FIG. 5c, the silicon nitride layer 14 is removed from the bottom surface of the silicon substrate 10 by etching.
As shown in FIG. 5d, the photoresist 20 is removed using a chemical substance such as acetone, methanol, etc. without damage to the silicon substrate 10, which has a high chemical resistance.
As shown in FIG. 5e, aluminum is deposited on the bottom surface of the silicon substrate 10 to form an anodized electrode 13.
Subsequently, as shown in FIG. 5f, the silicon substrate 10 is anodized to form a porous silicon layer 30 on an exposed portion not covered with the silicon nitride layer 14. Preferably, the porous silicon layer 30 is deposited to a thickness of more than about 20 μm in order to avoid a loss of the transmission line in the ultrahigh frequency band that may otherwise occur due to the reverse conducting characteristic of the silicon substrate. As shown in FIG. 5g, the anodized electrode 13 is removed by etching. Here, removal of the anodized electrode 13 is conducted using an etching solution prepared by mixing hydrofluoric acid (HF) and ultra pure water at a mixing ratio of 1 :10, because the anodized electrode 13 comprises aluminum.
As shown in FIG. 5h, the porous silicon layer 30 is oxidized into an oxidized porous silicon layer 31.
Finally, as shown in FIG. 5i, the remaining silicon nitride layer 14 is removed.
Accordingly, the present invention can selectively form an oxidized porous silicon layer on a silicon substrate without damage. FIGS. 6 and 7 are cross-sectional views of a flip-chip type multi-chip package and a wire-bonding type multi-chip package obtained using an oxidized porous silicon layer selectively formed according to the embodiments of the present invention, respectively.
First, referring to FIG. 6, an oxidized porous silicon layer 31 is selectively formed on the surface of a P-type silicon substrate 10, and a portion 11 of the silicon substrate 10 without the oxidized porous silicon layer 31 formed thereon is doped with an N-type impurity. The silicon substrate 10 remains intact underneath the oxidized porous silicon layer 30 and the portion 11 doped with the N-type impurity. On the silicon substrate 10 is mounted a flip chip 51 such as an optical or electric IC. The flip chip 51 has a connection to the silicon substrate 10 via I/O and heat transfer terminals 41 and 42 and solder bumpers 61 and 62, which are provided between the terminals. More specifically, the I/O terminal 41 and the solder bumper 61 are used to connect the wire formed on the oxidized porous silicon layer 30 to the wire of the flip chip 51 , while the heat transfer terminal 42 and the solder bumper 62 are to transfer the heat generated from the flip chip 51 to the silicon substrate 10.
This structure dissipates heat generated from the flip chip 51 to the N-type doped region 11 of the silicon substrate 10 having a very high thermal conductivity through the heat transfer terminal 42 and the solder bumper 62, and thereby facilitates heat dissipation to the bottom of the silicon substrate Referring to FIG. 7, a metal coating electrode 70 for mounting a bare chip is formed on the silicon substrate having the oxidized porous silicon layer 31 and the N-type doped region 11 formed thereon, and a bare chip 52 is mounted on the metal coating electrode 70. The bare chip 52 has an I/O terminal 40 connected, via a bonding wire 80, to a passive device 90 formed on the oxidized porous silicon layer 31 or to an active device formed in the N-type doped region 11.
This structure dissipates heat generated from the bare chip 52 to the N-type doped region 11 of the silicon substrate 10 having a very high thermal conductivity through the metal coating electrode 70, and thereby facilitates heat dissipation to the bottom of the silicon substrate 10.
According to the present invention, a selectively oxidized porous silicon layer of high quality can be precisely formed on a silicon substrate without damage.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

WHAT IS CLAIMED IS:
1 . A fabrication method of a selectively oxidized porous silicon layer comprising:
(a) forming a photoresist pattern on a silicon substrate; (b) doping an impurity in the silicon substrate by ion implantation using the photoresist pattern as a mask;
(c) removing the photoresist pattern;
(d) anodizing the silicon substrate; and
(e) oxidizing the silicon substrate.
2. The method as claimed in claim 1 , wherein the silicon substrate is a P-type substrate and the impurity doped in the step (b) is an N-type impurity.
3. A multi-chip package comprising: a silicon substrate; an impurity-doped region formed in a defined pattern on the surface of the silicon substrate; an oxidized porous silicon layer formed on a portion of the silicon substrate other than at the impurity-doped region.
4. The multi-chip package as claimed in claim 3, wherein the silicon substrate is a P-type substrate and the impurity-doped region is doped with an N-type impurity.
5. The multi-chip package as claimed in claim 4, further comprising: a bumper formed on the silicon substrate; and a flip chip disposed on the bumper.
6. The multi-chip package as claimed in claim 4, further comprising: a metal coating electrode formed on the silicon substrate; an electric device formed on the silicon substrate, and including at least one of a passive device and an active device; a bare chip formed on the metal coating electrode; and a bonding wire for connecting the bare chip to the electric device formed on the silicon substrate.
7. A fabrication method of a selectively oxidized porous silicon layer comprising:
(a) forming an oxide layer pattern on a silicon substrate; (b) diffusing impurity ions into the silicon substrate using the oxide layer pattern as a mask;
(c) removing the oxide layer pattern;
(d) anodizing the silicon substrate to form a porous silicon layer; and
(e) oxidizing the porous silicon layer.
8. The method as claimed in claim 7, wherein the silicon substrate is a P-type substrate and the impurity ions diffused in the step (b) are of an N- type impurity.
9. A fabrication method of a selectively oxidized porous silicon layer comprising:
(a) forming a nitride layer pattern on a silicon substrate;
(b) anodizing the silicon substrate using the nitride layer pattern as an anodization blocking layer to form a porous silicon layer; and (c) oxidizing the porous silicon layer.
10. The method as claimed in claim 9, wherein the silicon substrate is a P-type substrate and the impurity-doped region is doped with an N-type impurity.
11. The method as claimed in claim 10, wherein the step (a) comprises: depositing a silicon nitride layer on both sides of the silicon substrate; forming a photoresist pattern on the silicon nitride layer; and etching the silicon nitride layer using the photoresist pattern as an etching mask.
PCT/KR2001/000473 2000-11-30 2001-03-23 Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same WO2002045146A1 (en)

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KR2000-72012 2000-11-30
KR10-2000-0072012A KR100405194B1 (en) 2000-11-30 2000-11-30 A fabrication method of selectively oxidized porous silicon(SOPS) layer, a multi-chip package of using the same, and a semiconductor substrate
KR10-2001-0001140A KR100466224B1 (en) 2001-01-09 2001-01-09 Fabrication method of base substrate for mounting semiconductor chip
KR2001-1140 2001-01-09

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