WO2002035837A2 - D1 embedded programming interface - Google Patents

D1 embedded programming interface Download PDF

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Publication number
WO2002035837A2
WO2002035837A2 PCT/EP2001/011878 EP0111878W WO0235837A2 WO 2002035837 A2 WO2002035837 A2 WO 2002035837A2 EP 0111878 W EP0111878 W EP 0111878W WO 0235837 A2 WO0235837 A2 WO 0235837A2
Authority
WO
WIPO (PCT)
Prior art keywords
data
programming
video
predetermined interval
blanking interval
Prior art date
Application number
PCT/EP2001/011878
Other languages
French (fr)
Other versions
WO2002035837A3 (en
Inventor
Jens Rennert
Ralph Escherich
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2002538674A priority Critical patent/JP2004512779A/en
Priority to KR1020027007831A priority patent/KR20020065584A/en
Publication of WO2002035837A2 publication Critical patent/WO2002035837A2/en
Publication of WO2002035837A3 publication Critical patent/WO2002035837A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • H04N7/087—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only
    • H04N7/088—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital

Definitions

  • the invention generally relates to programming interfaces, and more particularly to an implementation of a Dl embedded programming interface.
  • a Dl interface is widely accepted in the digital video world to transfer digital video data between devices.
  • a conventional digital video device such as a digital video encoder typically has either a 8 or 10 bit digital video input interface for receiving digital video data.
  • most video devices need a programming interface for receiving programming data.
  • I 2 C Inter Integrated Circuit
  • two pins would be required for programming data.
  • 9 to 10 pins are typical. The resulting area increase in such a conventional video device is significant.
  • the present invention provides an implementation of a Dl embedded programming interface that allows savings of expensive programming pins by embedding programming data into digital video/graphics data.
  • the programming data are then sent, as normal VBI (vertical blanking interval) data, to a Dl receiving digital video/graphics device through a Dl interface.
  • VBI vertical blanking interval
  • the invention also provides a way to synchronize the programming events with the digital video/graphics stream easily and gives the flexibility of programming/reprograrnming a Dl receiving digital video device in real time.
  • a data formatter is provided to implement a Dl embedded programming interface.
  • the data formatter comprises a data formatting circuit that is configured to receive a video/graphics data stream and programming data and provide an output stream containing active video data and the programming data; and a controller, operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to embed the prograrnming data in a predetermined interval in the output stream.
  • the predetermined interval is between the active video data.
  • the predetermined interval is a vertical blanking interval and the programming data are provided as VBI data.
  • the predetermined interval is a horizontal blanking interval.
  • the predetermined interval includes a vertical blanking interval and a horizontal blanking interval.
  • a video/graphics processor is also provided.
  • the processor comprises a processing pipeline that is configured to receive video/graphics data, process the data and provide a video/graphics data stream and programming data; and a data formatter, operably coupled to the pipeline, that is configured in the same manner as the one described above.
  • FIG. 1 is a functional block diagram of an exemplary system suitable for implementing the present invention
  • FIG. 2 is a functional block diagram of a processor according to the present invention.
  • FIG. 3 shows the general arrangement and contents of an exemplary video frame of the output stream in FIG. 2;
  • FIG. 4 illustrates a VBI data stream in an output stream with programming data embedded, according the present invention
  • FIG. 5 shows a controller according to the present invention.
  • FIG. 1 shows a functional block diagram of an exemplary system suitable for implementing the present invention.
  • a digital video/graphics source 10 supplies digital video/graphics signals to a memory buffer 16.
  • the digital data are stored in memory buffer 16 in a standard format.
  • a video/graphics data processor 20 receives the digital data for processing.
  • Processor 20 transmits the processed data to a video/graphics encoder 26 in a predetermined format.
  • Encoder 26 then encodes the data and transmits them to a display device 30 for displaying.
  • FIG. 2 shows a functional block diagram of processor 20 according to the present invention.
  • Processor 20 includes a conventional video/graphics processing pipeline 36 and an output formatter 40.
  • pipeline 36 performs well-known functions, such as pixel formatting, color space conversion, transformation filtering and pixel mixing, etc.
  • Output formatter 40 includes a data formatting circuit 46, whfch may be a multiplexer and a controller 50 operably coupled to the formatting circuit.
  • Formatting circuit 46 receives a digital video/graphics data stream 52 and programming data 54, along with a data stream 58 containing SAV (start active video), EAV (end active video) and BLN (blanking) signals from pipeline 36 and provides a Dl like video output stream 64.
  • SAV start active video
  • EAV end active video
  • BLN bladenking
  • Controller 50 receives various conventional signals from pipeline 36, including Hblank (horizontal blanking), Vsync (vertical synchronization), Pclk (pixel clock) and Mclk (multiplexer clock). Controller 50 controls formatting circuit 46 to allow programming data 54 to be embedded in a vertical blanking interval (VBI) of output video/graphics stream 64, as VBI data. By embedding the programming data in the output video stream, the invention saves expensive programming pins and provides the capability to program/reprogram a digital video/graphics device in real time.
  • FIG. 3 shows the general arrangement and contents of an exemplary video frame 70 of output stream 64.
  • Video frame 70 includes active video portions 72 containing active video data, vertical blanking intervals (VBI) 74 and horizontal blanking intervals 76. .
  • Each VBI 74 contains various data, such as closed-caption (CC) data, teletext (TTX) data, etc.
  • the programming data are embedded in VBI 74, as VBI data. In this way, sending the programming data to a Dl receiving digital video/graphics device is just like sending another type of VBI data across a digital interface.
  • the programming data may also be embedded in horizontal blanking intervals 76 (which generally contain no data), in addition to VBI 74.
  • FIG. 4 illustrates a VBI data stream in output stream 64 with programming data embedded therein, according the present invention.
  • the programming data are sent as normal VBI data, which include ancillary data headers (ANC Header), byte and word counts, etc.
  • ANC Header ancillary data headers
  • the codes "FF FF 00" in the stream indicate the start of VBI programming data.
  • the IDI2 data byte contains the programming data type (e.g., CC, TTX) sent by the stream.
  • the lower 4 bits of IDI2 with llll indicate programming data.
  • Programming data are sent as address-data pairs, e.g., add, Dl, with the address being that of a register in a receiving device in which the data in the pair is to be stored.
  • FIG. 5 shows controller 50 according to the present invention.
  • Controller 50 comprises a line sequencer 96 and a component sequencer 98.
  • Line sequencer 96 is a state machine which keeps track of the basic elements of a video line. It is controlled by the synchronization signal H/V-Sync coining from pipeline 36. The state machine transitions through four states: HACT (horizontal active area), HBLS (horizontal blank start), HBL (hor- izontal blanking interval), HBLE (horizontal blanking end).
  • HACT horizontal active area
  • HBLS horizontal blank start
  • HBL hor- izontal blanking interval
  • HBLE horizontal blanking end
  • Component sequencer 98 is another state machine which is responsible for the generation of the proper output format, i.e., the proper multiplex order of the RGB or YUV and the insertion of the SAN and EAN information into the output data stream. Inputs into component sequencer 98 are the control information provided by line sequencer 96 and the output mode specified in a control register (not shown).

Abstract

The present invention provides an implementation of a D1 embedded programming interface that allows savings of expensive programming pins by embedding programming data into digital video/graphics data. The programming data are then sent, as normal VBI (vertical blanking interval) data, to a D1 receiving digital video/graphics device through a D1 interface. The invention also provides a way to synchronize the programming events with the digital video/graphics stream easily and gives the flexibility of programming/reprogramming a D1 receiving digital video/graphics device in real time. In the present invention, a data formatter is provided to implement a D1 embedded programming interface. According to the invention, the programming data may be embedded in a vertical blanking interval in an output stream. Alternatively, the programming data may be embedded in a horizontal blanking interval, or in both a vertical blanking interval and a horizontal blanking interval in the output stream.

Description

Dl embedded programming interface
BACKGROUND OF THE INVENTION
The invention generally relates to programming interfaces, and more particularly to an implementation of a Dl embedded programming interface.
A Dl interface is widely accepted in the digital video world to transfer digital video data between devices. A conventional digital video device, such as a digital video encoder typically has either a 8 or 10 bit digital video input interface for receiving digital video data. In addition, most video devices need a programming interface for receiving programming data. In the case of the Inter Integrated Circuit (I2C) bus interface, two pins would be required for programming data. In the case of a parallel interface, 9 to 10 pins are typical. The resulting area increase in such a conventional video device is significant.
Especially, at present, as manufacturing processes are becoming smaller and smaller, most video devices are no longer core limited, but are pad limited. Furthermore, in such a conventional video device, predictable and synchronized programming using a separate interface is highly complicated. Additionally, synchronizing programming events with real time events is nearly impossible for most conventional video devices, because bus and interface latencies are too high and hard to predict. Synchronization allows special video effects (e.g., teletext and closed caption applications) to be viewed.
Therefore, there is a need for an effective implementation of a programming interface that provides savings on the number of pins on a video/graphics device and allows transmission of programming data in real time and synchronization of the programming data to the data stream.
SUMMARY OF THE INVENTION
The present invention provides an implementation of a Dl embedded programming interface that allows savings of expensive programming pins by embedding programming data into digital video/graphics data. The programming data are then sent, as normal VBI (vertical blanking interval) data, to a Dl receiving digital video/graphics device through a Dl interface. The invention also provides a way to synchronize the programming events with the digital video/graphics stream easily and gives the flexibility of programming/reprograrnming a Dl receiving digital video device in real time.
According to the invention, a data formatter is provided to implement a Dl embedded programming interface. The data formatter comprises a data formatting circuit that is configured to receive a video/graphics data stream and programming data and provide an output stream containing active video data and the programming data; and a controller, operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to embed the prograrnming data in a predetermined interval in the output stream.
In one embodiment of the invention, the predetermined interval is between the active video data. Preferably, the predetermined interval is a vertical blanking interval and the programming data are provided as VBI data. In another embodiment of the invention, the predetermined interval is a horizontal blanking interval. In a further embodiment of the invention, the predetermined interval includes a vertical blanking interval and a horizontal blanking interval. According to the invention, a video/graphics processor is also provided. The processor comprises a processing pipeline that is configured to receive video/graphics data, process the data and provide a video/graphics data stream and programming data; and a data formatter, operably coupled to the pipeline, that is configured in the same manner as the one described above. Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:
FIG. 1 is a functional block diagram of an exemplary system suitable for implementing the present invention;
FIG. 2 is a functional block diagram of a processor according to the present invention;
FIG. 3 shows the general arrangement and contents of an exemplary video frame of the output stream in FIG. 2;
FIG. 4 illustrates a VBI data stream in an output stream with programming data embedded, according the present invention; and FIG. 5 shows a controller according to the present invention. Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows a functional block diagram of an exemplary system suitable for implementing the present invention. As illustrated in FIG. 1, a digital video/graphics source 10 supplies digital video/graphics signals to a memory buffer 16. The digital data are stored in memory buffer 16 in a standard format. Upon command, a video/graphics data processor 20 receives the digital data for processing. Processor 20 transmits the processed data to a video/graphics encoder 26 in a predetermined format. Encoder 26 then encodes the data and transmits them to a display device 30 for displaying.
FIG. 2 shows a functional block diagram of processor 20 according to the present invention. Processor 20 includes a conventional video/graphics processing pipeline 36 and an output formatter 40. As will be understood by those skilled in the art, pipeline 36 performs well-known functions, such as pixel formatting, color space conversion, transformation filtering and pixel mixing, etc. Output formatter 40 includes a data formatting circuit 46, whfch may be a multiplexer and a controller 50 operably coupled to the formatting circuit. Formatting circuit 46 receives a digital video/graphics data stream 52 and programming data 54, along with a data stream 58 containing SAV (start active video), EAV (end active video) and BLN (blanking) signals from pipeline 36 and provides a Dl like video output stream 64. Controller 50 receives various conventional signals from pipeline 36, including Hblank (horizontal blanking), Vsync (vertical synchronization), Pclk (pixel clock) and Mclk (multiplexer clock). Controller 50 controls formatting circuit 46 to allow programming data 54 to be embedded in a vertical blanking interval (VBI) of output video/graphics stream 64, as VBI data. By embedding the programming data in the output video stream, the invention saves expensive programming pins and provides the capability to program/reprogram a digital video/graphics device in real time. FIG. 3 shows the general arrangement and contents of an exemplary video frame 70 of output stream 64. Video frame 70 includes active video portions 72 containing active video data, vertical blanking intervals (VBI) 74 and horizontal blanking intervals 76. . Each VBI 74 contains various data, such as closed-caption (CC) data, teletext (TTX) data, etc. According to the invention, the programming data are embedded in VBI 74, as VBI data. In this way, sending the programming data to a Dl receiving digital video/graphics device is just like sending another type of VBI data across a digital interface. The programming data may also be embedded in horizontal blanking intervals 76 (which generally contain no data), in addition to VBI 74. FIG. 4 illustrates a VBI data stream in output stream 64 with programming data embedded therein, according the present invention. The programming data are sent as normal VBI data, which include ancillary data headers (ANC Header), byte and word counts, etc. The codes "FF FF 00" in the stream indicate the start of VBI programming data. The IDI2 data byte contains the programming data type (e.g., CC, TTX) sent by the stream. The lower 4 bits of IDI2 with llll indicate programming data. Programming data are sent as address-data pairs, e.g., add, Dl, with the address being that of a register in a receiving device in which the data in the pair is to be stored.
Therefore, this invention provides a way to synchronize programming events with the digital video/graphics stream easily. FIG. 5 shows controller 50 according to the present invention. Controller 50 comprises a line sequencer 96 and a component sequencer 98. Line sequencer 96 is a state machine which keeps track of the basic elements of a video line. It is controlled by the synchronization signal H/V-Sync coining from pipeline 36. The state machine transitions through four states: HACT (horizontal active area), HBLS (horizontal blank start), HBL (hor- izontal blanking interval), HBLE (horizontal blanking end). Depending on the current state of line sequencer 96, different control information is sent to component sequencer 98. Component sequencer 98 is another state machine which is responsible for the generation of the proper output format, i.e., the proper multiplex order of the RGB or YUV and the insertion of the SAN and EAN information into the output data stream. Inputs into component sequencer 98 are the control information provided by line sequencer 96 and the output mode specified in a control register (not shown).
While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and scope of the appended claims.

Claims

CLAIMS:
1. A data formatter (40), comprising: a data formatting circuit (46) that is configured to receive a video/graphics data stream and programming data and provide an output stream containing active video data and the programming data; and a controller (50), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to embed the programming data in a predetermined interval in the output stream.
2. The formatter of claim 1, wherein the predetermined interval is between the active video data.
3. The formatter of claim 1, wherein the predetermined interval is a vertical blanking interval (NBI) and the programming data are provided as NBI data.
4. The formatter of claim 1, wherein the predetermined interval is a horizontal blanking interval.
5. The formatter of claim 1, wherein the predetermined interval includes a vertical blanking interval (VBI) and a horizontal blanking interval.
6. The formatter of claim 1, wherein the programming data include address-data pairs.
7. The formatter of claim 1, wherein the data formatting circuit includes a multiplexer.
8. A video/graphics processor (20), comprising: a processing pipeline (36) that is configured to receive video/graphics data, process the data and provide a video/graphics data stream and programming data; and a data formatter (40), operably coupled to the pipeline, that comprises: a data formatting circuit (46) that is configured to receive the video/graphics data stream and the programming data and provide an output stream containing active video data and the programming data, and a controller (50), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to embed the programming data in a predetermined interval in the output stream.
9. The processor of claim 8, wherein the predetermined interval is between the active video data.
10. The processor of claim 8, wherein the predetermined interval is a vertical blanking interval (VBI) and the programming data are provided as VBI data.
11. The processor of claim 8, wherein the predetermined interval is a horizontal blanking interval.
12. The processor of claim 8, wherein the predetermined interval includes a vertical blanking interval (NBI) and a horizontal blanking interval.
13. The processor of claim 8, wherein the programming data include address-data pairs.
14. The processor of claim 8, wherein the data formatting circuit includes a multiplexer.
15. A method, comprising the steps of: receiving programming data and a video/graphics data stream containing active video data; embedding the programming data in a predetermined interval in an output stream containing the active video data; and providing the output stream.
16. The method of claim 15, wherein the predetermined interval is between the active video data.
17. The method of claim 15, wherein the predetermined interval is a vertical blanking interval (NBI) and the programming data are provided as NBI data.
18. The method of claim 15, wherein the predetermined interval is a horizontal blanking interval.
19. The method of claim 15, wherein the predetermined interval includes a vertical blanking interval (NBI) and a horizontal blanking interval.
20. The method of claim 15, wherein the programming data include address-data pairs.
PCT/EP2001/011878 2000-10-20 2001-10-12 D1 embedded programming interface WO2002035837A2 (en)

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JP2002538674A JP2004512779A (en) 2000-10-20 2001-10-12 D1 embedded programming interface
KR1020027007831A KR20020065584A (en) 2000-10-20 2001-10-12 D1 embedded programming interface

Applications Claiming Priority (2)

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US69334500A 2000-10-20 2000-10-20
US09/693,345 2000-10-20

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CN102714745A (en) * 2010-02-10 2012-10-03 松下电器产业株式会社 Digital video signal output device and display device, and digital video signal output method and reception method
KR101877775B1 (en) * 2012-11-26 2018-07-13 삼성전자주식회사 Method and apparatus for allocation a interfearence cancellation code for coordinated communication between base stations in a radio communication system

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714745A (en) * 2010-02-10 2012-10-03 松下电器产业株式会社 Digital video signal output device and display device, and digital video signal output method and reception method
EP2536154A1 (en) * 2010-02-10 2012-12-19 Panasonic Corporation Digital video signal output device and display device, and digital video signal output method and reception method
EP2536154A4 (en) * 2010-02-10 2014-04-16 Panasonic Corp Digital video signal output device and display device, and digital video signal output method and reception method
CN102714745B (en) * 2010-02-10 2015-06-17 松下电器产业株式会社 Digital video signal output device and display device, and digital video signal output method and reception method
US9319658B2 (en) 2010-02-10 2016-04-19 Panasonic Intellectual Property Management Co., Ltd. Digital video signal output device and display device, and digital video signal output method and reception method
KR101877775B1 (en) * 2012-11-26 2018-07-13 삼성전자주식회사 Method and apparatus for allocation a interfearence cancellation code for coordinated communication between base stations in a radio communication system

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JP2004512779A (en) 2004-04-22
KR20020065584A (en) 2002-08-13
WO2002035837A3 (en) 2002-08-01

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