WO2002025701A2 - Body-tied silicon on insulator semiconductor device structure and method therefor - Google Patents

Body-tied silicon on insulator semiconductor device structure and method therefor

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Publication number
WO2002025701A2
WO2002025701A2 PCT/US2001/027704 US0127704W WO0225701A2 WO 2002025701 A2 WO2002025701 A2 WO 2002025701A2 US 0127704 W US0127704 W US 0127704W WO 0225701 A2 WO0225701 A2 WO 0225701A2
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WO
WIPO (PCT)
Prior art keywords
semiconductor
region
area
layer
device structure
Prior art date
Application number
PCT/US2001/027704
Other languages
French (fr)
Other versions
WO2002025701A3 (en
Inventor
Byoung W. Min
Michael A. Mendicino
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to AU2001288845A priority Critical patent/AU2001288845A1/en
Publication of WO2002025701A2 publication Critical patent/WO2002025701A2/en
Publication of WO2002025701A3 publication Critical patent/WO2002025701A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the invention related generally to semiconductor devices and more particularly to a body-tied silicon on insulator semiconductor device structure and method therefore.
  • SOI Silicon on insulator
  • floating body coupling can provide advantages for some portion of the circuit built using SOI technology, in some cases a known body potential for specific devices is desired. As such, knowledge of the potential of the body in a body-tied silicon on insulator device ensures that the switching characteristics of the device are reproducible and predictable regardless of the previous state of the device.
  • T- and H-gate transistor structures In order to allow for body-tied devices within SOI circuits, some device structures have been developed that provide a means for tying the active region of individual devices to a known potential. Examples include T- and H-gate transistor structures, where the active region is extended beyond the gate structure to provide a means for supplying the desired potential to the active region.
  • the T- and H-gate structures have a significant amount of added gate capacitance, and are also problematic in terms of process control issues. As a result of the additional gate capacitance, significant reduction of device speed can occur when T- and H-gate structures are used.
  • a uniform biasing potential may be applied to all of the devices in a well by linking the bodies of these devices underneath the field oxide.
  • this does ensure that the potential within the bodies of the transistors is known, it does not allow devices that have known body potential to coexist with floating body devices.
  • floating body devices are desirable for some portions of the circuit
  • body-tied devices are desirable for other portions of the circuit
  • such techniques are hindered by undesirable limitations.
  • some of the isolation advantages provided by SOI technology are forfeited. For example, some of the advantages in terms of avoiding latch-up and leakage are diminished.
  • FIG. 1 includes an illustration of a cross-sectional view of a silicon on insulator (SOI) substrate in accordance with a particular embodiment of the present invention
  • FIG. 2 includes an illustration of a cross-sectional view of the SOI substrate
  • FIG. 3 includes an illustration of a cross-sectional view of the SOI substrate following etching operations associated with forming a partial trench isolation region in accordance with a particular embodiment of the present invention
  • FIG. 4 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 3 during an implant operation that forms a conductive body contact region in accordance with a particular embodiment of the present invention
  • FIG. 5 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 4 after additional patterning operations performed in accordance with a particular embodiment of the present invention
  • FIG. 6 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 5 following etching operations that define full trench isolation regions in accordance with a particular embodiment of the present invention
  • FIG. 7 includes an illustration of a cross-sectional view of the
  • FIG. 8 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 7 following selective removal of portions of the field oxide and a nitride layer associated with previous patterning and deposition steps in accordance with a particular embodiment of the present invention
  • FIG. 9 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 8 during an implantation operation associated with well doping in accordance with a particular embodiment of the present invention
  • FIG. 10 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 9 following gate definition performed in accordance with a particular embodiment of the present invention
  • FIG. 11 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 10 during an implantation operation associated with source/drain region and gate doping in accordance with a particular embodiment of the present invention
  • FIG. 12 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 11 during an implantation operation associated with complementary device source/drain region doping as well as conductive body contact doping enhancement in accordance with a particular embodiment of the present invention
  • FIG. 13 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 12 following additional steps associated with device and interconnect formation in accordance with a particular embodiment of the present invention
  • FIG. 14 includes an illustration of a top-down perspective of the SOI device formed based on the steps illustrated in FIGs. 1 - 13;
  • FIG. 15 includes an illustration of an alternate cross-sectional view of the SOI device of FIG. 14.
  • the present invention provides a silicon on insulator (SOI) device structure and method therefore, where the SOI device structure utilizes a conductive path under a partial trench isolation region to connect a conductive area with the body region of the device such that the desired potential within the body region can be achieved.
  • SOI silicon on insulator
  • This is accomplished by patterning the silicon on insulator (SOI) substrate and etching away the portion of the substrate within which the partial trench isolation is to be formed. Following the etching operation, an implant step dopes the remaining portion of the silicon film underlying the partial trench isolation region to achieve the desired conductivity.
  • Full trench isolation regions are then patterned and formed, where the full trench isolation regions ensure isolation between devices on the SOI substrate.
  • FIG. 1 illustrates a cross-sectional view of an SOI substrate that is made up of a number of layers.
  • the SOI substrate includes an underlying substrate layer 102, where the underlying substrate layer 102 may be silicon, sapphire, or other materials that provide adequate mechanical support for the overlying insulating and semiconducting layers. Silicon may be a preferable material for the underlying substrate layer 102 due to its desirable thermal and reactive characteristics.
  • An insulating layer 104 is formed on the underlying substrate layer 102. This may be accomplished by implanting oxygen or nitrogen ions within a semiconductive base material (i.e., a P-type monocrystalline silicon wafer) at an energy and a range of approximately 100 - 200 KeV to a dose of at least 1 x 10 1a ions per square centimeter and usually on the order of 1 x 10 18 ions per square centimeter. Heat is typically applied to the semiconductor base material during implantation to maintain crystallinity. The substrate is then annealed at a temperature in a range of approximately 1000° - 1200° Celsius for a time within a range of approximately 1 - 5 hours. These steps form the buried insulator layer 104 and a semiconductor layer 106, which may be a monocrystalline layer, having a thickness less than approximately 2500 ⁇ and more typically in the range of approximately 500 - 150 ⁇ A.
  • a semiconductive base material i.e., a P-type monocrystalline silicon wafer
  • the substrate of FIG. 1 may be formed by conventional wafer - wafer bonding techniques.
  • the semiconductor layer 106 is formed over a sapphire substrate or a substrate of another insulating material that is also capable of providing adequate mechanical support to the overlying silicon layer within which the device formation occurs.
  • FIG. 2 illustrates a cross-sectional view of the SOI substrate of FIG. 1 after additional processing.
  • a nitride layer 208 is deposited overlying the semiconductor layer 106, which may be a silicon layer. Such deposition may be performed using low pressure chemical vapor deposition (LPCVD) or other deposition techniques.
  • Nitride layer 208 acts as an anti-reflective coating (ARC), a chemical mechanical polishing (CMP) stopping layer, and as a hard mask which can be used in association with a soft mask, such as photoresist, to achieve desired etching characteristics with respect to the underlying semiconductor layer 106.
  • the nitride layer 208 is typically formed to a thickness of approximately 500 - 2000A.
  • a stress relief oxide layer may be formed overlying the semiconductor layer 106 prior to formation of the nitride layer 208.
  • the stress relief layer may be formed of thermally or chemically grown silicon oxide, where the thickness of this stress relief layer may be on the order of 100 - 20 ⁇ A.
  • a photo-resist layer 210 is formed overlying the nitride layer 208, where the photo-resist layer is patterned by conventional lithography techniques to define the desired location for the partial trench isolation region.
  • the photo-resist layer is patterned by conventional lithography techniques to define the desired location for the partial trench isolation region.
  • the masking layer associated with patterning the photo-resist layer 210 for partial trench isolation region definition may be such that the density of patterned area associated with partial trenches is relatively low.
  • FIG. 3 illustrates a cross-sectional view of the SOI substrate of FIG. 2 following selective etching operations associated with forming the region in which the partial trench isolation region is to reside.
  • etching operations may be accomplished by reactive ion etching (RIE), wet etching, or other anisotropic etching techniques.
  • the reactive ion etch may include a first stage during which a portion of the nitride layer 208 is removed followed by a second stage during which the desired portion of the silicon layer 106 is removed.
  • the first and second stages may differ in the particular chemistries utilized such that the desired layers are etched efficiently.
  • the etching operations are controlled such that a limited portion of the silicon layer underlying the patterned region is removed. As such, a semiconductor portion of the semiconductor layer 106 is left intact. In an embodiment where the silicon layer 106 is approximately 1000A, it may be desirable to remove approximately 50 ⁇ A of the silicon layer 106.
  • the partial trench isolation regions may be formed by performing localized oxidation of silicon (LOCOS) to create silicon oxide in the region where the partial trench is to be located. Because the silicon oxide is non-conductive, these silicon oxide regions can serve as the partial trench isolation regions that are desired within the device.
  • LOCOS localized oxidation of silicon
  • FIG. 4 illustrates the SOI substrate of FIG. 3 during an implantation step.
  • the figures correspond to the formation of a body-tied N-channel device, or N-metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET N-metal oxide semiconductor field effect transistor
  • the body of the NMOS transistor is P-type.
  • the region underlying the partial trench is heavily P-doped (P+).
  • P+ P-doped
  • the doping operation illustrated in FIG. 4 is targeted at providing a highly conductive region underlying the partial trench.
  • the conductivity of the underlying region 220 of semiconductive material may be achieved through the P-well doping associated with the NMOS device.
  • FIG. 5 illustrates the SOI substrate of FIG. 4 following deposition and patterning of an additional layer of photo-resist 230 associated with formation of full trench isolation regions.
  • Such full trench isolation regions provide desired isolation between individual devices or groups of devices that may be tied to a common body bias.
  • FIG. 6 illustrates the SOI substrate of FIG. 5 following removal of the portions of the nitride layer 208 and the semiconductor layer 106 in regions corresponding to full trench isolation regions. It should be noted that the complete removal of the semiconductor layer 106 occurs in the full trench isolation regions as opposed to the partial removal of this layer in the partial trench isolation regions. Complete removal of the semiconductor layer 106 in the full trench isolation regions exposes the underlying insulating layer 104 in these areas.
  • Etching of the desired portion of the nitride layer 208 and the semiconductor layer 106 to form the full trench isolation regions can be achieved by a reactive ion etch operation.
  • a reactive ion etch may include the use of selective or non-selective chemistries. Because the reactive ion etch may damage the exposed sidewalls of the semiconductor layer 106, additional oxidation and thermal treatment may be used to recover the desired high quality crystalline structure and associated electrical properties along the sidewalls.
  • FIG. 7 illustrates the SOI substrate of FIG. 6 following removal of the photo-resist 230 and formation of field oxide 240, which is an insulating material, which is at least as deep as semiconductor layer 106 so that there is insulator extending from the top surface of semiconductor layer 106 to insulator layer 104.
  • the field oxide formation may be accomplished by a blanket deposition of field oxide using a variety of techniques including high density plasma (HDP) deposition , LPCVD, and the like.
  • HDP high density plasma
  • FIG. 8 illustrates a cross-sectional view of the SOI substrate of
  • FIG. 7 following removal of the undesired portions of the field oxide 240 and the complete removal of remaining portions of the nitride layer 208.
  • the undesirable portions of the field oxide 240 may be removed by CMP operations, whereas the nitride layer 208 is removed using wet chemical etching.
  • the wet chemical etching used to remove the nitride layer 208 may include the use of phosphoric acid, which selectively removes the nitride with minimal erosion of neighboring materials.
  • the field oxide included in the partial trench isolation region 250 may either be formed through deposition and selective removal as described with respect to FIG. 7 or through the localized oxidation of silicon (LOCOS) following definition of the region in which the partial trench isolation region is to reside (as shown in FIG. 3 above).
  • LOCOS localized oxidation of silicon
  • FIG. 9 illustrates a cross-sectional view of the SOI substrate of FIG. 8 during the implant operation associated with P-well doping.
  • CMOS complementary MOS
  • both NMOS and PMOS devices are created.
  • NMOS devices utilize P-wells to achieve the desired threshold voltages
  • PMOS devices utilize N-wells.
  • portions of the substrate are typically masked off while doping of the well associated with the complementary devices occurs.
  • the implantation operation occurring in FIG. 9 causes the remaining portions of the semiconductor layer 106 to become lightly P-doped to form the doped regions 320.
  • the photoresist regions 310 are included to mask off areas that are not to be doped.
  • the P- implant operation may be used to dope the conductive region 220.
  • concentration of the P- implant may not be as high as the concentration associated with the dedicated P+ implant described above with respect to FIG. 4. As such, conductivity of the underlying conductive region 220 may be reduced, but possibly still sufficient for certain practical applications.
  • FIG. 10 illustrates a cross-sectional view of the SOI substrate of
  • FIG. 9 following a number of processing steps associated with gate formation.
  • any stress relief layers included overlying the doped regions 320 are removed.
  • a gate dielectric layer 410 which may also be referred to as a gate insulator, is formed overlying the doped regions 320.
  • the gate dielectric layer 410 may be made up of silicon oxide, silicon oxynitride, or other desirable high-K (high dielectric constant) insulating materials.
  • the gate dielectric layer 410 may have a thickness that is less than 100A, and may typically be in a range of 20 - 8 ⁇ A. Note that in some embodiments, multiple gate dielectrics of varying thickness may be included on the same substrate.
  • a gate material layer 420 is formed. This may be accomplished by depositing a polycrystalline silicon (polysilicon) or amorphous silicon layer as the gate material layer 420.
  • the gate material layer 420 may be doped in-situ, such that doped material is initially deposited, or doped during a separate operation that occurs following deposition.
  • patterning steps which may include the use of a photo-resist layer 430, are used in conjunction with etching operations to selectively remove portions of the gate material layer 420 and the gate dielectric layer 410. As a result, the desired gate structure associated with the NMOS device is formed.
  • FIG. 11 illustrates a cross-sectional view of the SOI substrate of FIG. 10 during a subsequent implantation step.
  • Sidewall spacers 510 are formed adjacent to the gate electrode 520 by conformally depositing and anisotropically etching a layer including oxide, nitride, or the like.
  • Patterning which may include the use of a photo-resist layer 530 is then performed to facilitate an N+ implant operation.
  • the N+ implant serves to dope the source and drain regions for the NMOS device being formed. Formation of the source and drain regions produces a channel therebetween, where the channel may also be referred to as the body region 380 of the device.
  • Such an implant operation can also be used to dope the gate 520.
  • the channel is adjacent to the partial trench isolation region 250 at one end and adjacent to the full trench isolation region 240 at the other end.
  • the body region 380 of the NMOS device is bounded by the source and drain regions formed by the N+ implant, the full trench isolation region 240, the partial trench isolation region 250, the body contact region 220, the gate dielectric layer 410, and the insulating layer 104.
  • the body region 380 may be bounded on more than one side by partial trench isolation regions overlying a body contact region.
  • the structure that includes the partial trench isolation region 250 and the body contact region 220 could be repeated at the opposite end of the body region 380 such that the desired biasing voltage could be applied from either or both directions such that resistivity associated with the body contact regions is further reduced.
  • Complementary devices include a similar region to the doped region 320 illustrated in FIG. 11. However, in these complementary devices, it is desirable to make such doped regions heavily N+ doped because these regions serve as the contact regions. As such, the implant operation used to dope the source/drain and gate for the NMOS device can be used to dope the contact region of complementary devices.
  • FIG. 12 illustrates a cross-sectional view of the SOI substrate of FIG 11. during a subsequent implantation step.
  • a new photo-resist layer 620 is formed and patterned.
  • the patterning for the photo-resist layer 620 is associated with doping of the source/drain and gate portions of complementary devices as well as the conductive region 610, which physically contacts region 220. Region 610 and contacts 220 share a contiguous border. Making the conductive region 610 highly doped facilitates the biasing of the body region 380. In other words, making the conductive region 610 and the conductive body contact region 220 heavily doped ensures a low resistance path to body region 380 of the NMOS device.
  • FIG. 13 illustrates a cross-sectional view of the SOI substrate of FIG. 12 following subsequent processing steps associated with completion of the NMOS device and associated interconnect.
  • An interlevel dielectric (ILD) layer 730 is formed overlying the structure of FIG. 12. Subsequent planarization, patterning, and etching provide for a desirable ILD layer 730 that includes contact regions in which contacts 710 and 720, which may be metal, are formed. Note that formation of regions for additional contacts associated with the source and drain for the NMOS device (illustrated in FIG. 14) also occurs during such patterning and etching operations.
  • ILD interlevel dielectric
  • the contact 710 provides access to the gate electrode 520, where the contact 710 may be coupled to a portion of an overlying interconnect layer 750.
  • the contact 720 provides a means for coupling the overlying interconnect layer 750 to the conductive region 610 such that the proper bias can be applied to the body region 380.
  • Standard metalization steps are used to form the desired traces in the interconnect layer 750, where these traces are separated by a second ILD 740.
  • additional layers of interconnect can be added to allow for additional wiring capability for the circuit. Although many details of these layers and their deposition and patterning techniques are not described in detail herein, one of ordinary skill in the art appreciates that state of the art techniques (e.g. salicides, barrier layers, capping layers, etch stop layers, etc) may be relied upon in the formation of these layers.
  • FIG. 14 illustrates a top-down view of the semiconductor device formed using the various steps described with respect to FIGs. 1 - 13 above. Note that FIGs. 1 - 13 correspond to a cross-section of the device intersecting contacts 710 and 720 along an axis labeled with the large numeral 13.
  • FIG. 14 includes source and drain regions 810, which are preferably doped by the N+ implant operations associated with FIG. 11.
  • the contacts 820 provide connectivity to the source/drain regions 810, and interconnect layer portions 830 facilitate the provision of electrical signals to the source and drain regions 810.
  • the active portion of the device is generally surrounded by two types of isolation regions.
  • a first isolation region corresponding to the full trench isolation region 240 surrounds the majority of the active region, whereas a second isolation portion separates the active region from the conductive region 610.
  • the partial trench isolation region 250 overlies the body contact region 220, which allows the potential applied to the conductive region 610 to be transferred to the body region 380 of the device that underlies the gate electrode 520.
  • the potential that exists within the conductive region 610 is established by the contacts 720 which intercouple the conductive region 610 with a portion of the interconnect layer 750.
  • Another portion of the interconnect layer 750 is shown to be coupled to the gate electrode 520 via the contact 710. Note that in other embodiments of the invention, the contact 710 and the associated interconnect portion 750 may be positioned above the partial isolation region 250. In some embodiments of the invention, a similar partial field isolation region 250 may be positioned at the opposite side of the active region as compared with the partial field isolation region 250 illustrated in FIG. 14. In such embodiments, an additional conductive region and associated contacts and interconnect may be used to provide additional biasing capabilities for the body region of the device.
  • FIG. 15 illustrates a cross-sectional view of the device of FIG. 14 taken along a different cross-sectional axis (labeled with a large numeral 15 in FIG. 14).
  • the cross-sectional view of the device depicted in FIG. 15 does not differ from the cross-sectional view of a conventional floating body device.
  • the body region 380 which includes the channel region of the device, is positioned between the source and drain regions 810, overlying the insulating layer 104 and below the gate dielectric 410.
  • the full trench isolation regions 240 isolate the device on each side.
  • a single conductive region may be used to supply this bias to the multiple body regions for the multiple devices. This can be achieved by separating the body regions of these devices from the conductive region using partial trench isolation regions accompanied by underlying body contact regions.
  • the FIGs. and accompanying text describe the formation of an NMOS transistor.
  • similar procedures using dopant materials of opposing conductivity i.e. P+ doping for source/drain, N+ doping for the conductive body region, etc
  • P+ doping for source/drain, N+ doping for the conductive body region, etc can be used to form PMOS transistors that provide the biasing advantages for SOI devices without the added gate capacitance and other detrimental side effects associated with prior- art body-tied devices.

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Abstract

A silicon on insulator (SOI) device structure and method therefore in which the SOI device structure utilizes a conductive body contact region (220) under a partial trench isolation region (250) to connect a doped region (320), which is a conductive area, with the body region (380) of the device such that the desired potential within the body region (380) can be achieved. This is accomplished by patterning the silicon on insulator (SOI) substrate and etching away the portion of the substrate within which the partial trench isolation is to be formed. Following the etching operation, an implant step dopes the remaining portion of the silicon film underlying the partial trench isolation region (250) to achieve the desired conductivity. Full trench isolation regions (240) are then patterned and formed. Subsequent formation of contacts (710, 720) and other layers of interconnect (750) complete formation of the SOI device.

Description

BODY-TIED SILICON ON INSULATOR SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
Field of the Invention
The invention related generally to semiconductor devices and more particularly to a body-tied silicon on insulator semiconductor device structure and method therefore.
Related Art
Silicon on insulator (SOI) technology has been developed to provide a number of advantages over bulk silicon device technologies. As is known, SOI provides improvements in speed and power consumption with respect to previous bulk silicon circuits. Some of the benefits of SOI technology are based on the reduced capacitance at various junctions within semiconductor devices, whereas additional benefits are derived from the floating body itself.
Because the speed with which a floating body device switches may be affected by the previous state of the device, when the device switching speed is important, such a variation in the speed with which the device switches may be undesirable. Therefore, although floating body coupling can provide advantages for some portion of the circuit built using SOI technology, in some cases a known body potential for specific devices is desired. As such, knowledge of the potential of the body in a body-tied silicon on insulator device ensures that the switching characteristics of the device are reproducible and predictable regardless of the previous state of the device.
In order to allow for body-tied devices within SOI circuits, some device structures have been developed that provide a means for tying the active region of individual devices to a known potential. Examples include T- and H-gate transistor structures, where the active region is extended beyond the gate structure to provide a means for supplying the desired potential to the active region. The T- and H-gate structures have a significant amount of added gate capacitance, and are also problematic in terms of process control issues. As a result of the additional gate capacitance, significant reduction of device speed can occur when T- and H-gate structures are used.
In other prior art techniques for controlling the potential within active regions in SOI devices, a uniform biasing potential may be applied to all of the devices in a well by linking the bodies of these devices underneath the field oxide. Although this does ensure that the potential within the bodies of the transistors is known, it does not allow devices that have known body potential to coexist with floating body devices. Thus, as floating body devices are desirable for some portions of the circuit, whereas body-tied devices are desirable for other portions of the circuit, such techniques are hindered by undesirable limitations. Furthermore, by linking the bodies of the transistors within the well structure, some of the isolation advantages provided by SOI technology are forfeited. For example, some of the advantages in terms of avoiding latch-up and leakage are diminished.
Therefore, a need exists for a body-tied SOI device that does not suffer from the adverse effects associated with increased gate capacitance and reduced isolation integrity, while providing adequate assurance as to active region potential such that the switching characteristics of the device are well understood.
Brief Description of the Drawings
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 includes an illustration of a cross-sectional view of a silicon on insulator (SOI) substrate in accordance with a particular embodiment of the present invention; FIG. 2 includes an illustration of a cross-sectional view of the
SOI substrate of FIG. 1 following additional steps associated with patterning in accordance with a particular embodiment of the present invention;
FIG. 3 includes an illustration of a cross-sectional view of the SOI substrate following etching operations associated with forming a partial trench isolation region in accordance with a particular embodiment of the present invention;
FIG. 4 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 3 during an implant operation that forms a conductive body contact region in accordance with a particular embodiment of the present invention;
FIG. 5 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 4 after additional patterning operations performed in accordance with a particular embodiment of the present invention;
FIG. 6 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 5 following etching operations that define full trench isolation regions in accordance with a particular embodiment of the present invention; FIG. 7 includes an illustration of a cross-sectional view of the
SOI substrate of FIG. 6 following deposition of field oxide in accordance with a particular embodiment of the present invention;
FIG. 8 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 7 following selective removal of portions of the field oxide and a nitride layer associated with previous patterning and deposition steps in accordance with a particular embodiment of the present invention;
FIG. 9 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 8 during an implantation operation associated with well doping in accordance with a particular embodiment of the present invention; FIG. 10 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 9 following gate definition performed in accordance with a particular embodiment of the present invention;
FIG. 11 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 10 during an implantation operation associated with source/drain region and gate doping in accordance with a particular embodiment of the present invention;
FIG. 12 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 11 during an implantation operation associated with complementary device source/drain region doping as well as conductive body contact doping enhancement in accordance with a particular embodiment of the present invention;
FIG. 13 includes an illustration of a cross-sectional view of the SOI substrate of FIG. 12 following additional steps associated with device and interconnect formation in accordance with a particular embodiment of the present invention;
FIG. 14 includes an illustration of a top-down perspective of the SOI device formed based on the steps illustrated in FIGs. 1 - 13; and
FIG. 15 includes an illustration of an alternate cross-sectional view of the SOI device of FIG. 14.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
BLANK UPON FILING
Detailed Description
Generally, the present invention provides a silicon on insulator (SOI) device structure and method therefore, where the SOI device structure utilizes a conductive path under a partial trench isolation region to connect a conductive area with the body region of the device such that the desired potential within the body region can be achieved. This is accomplished by patterning the silicon on insulator (SOI) substrate and etching away the portion of the substrate within which the partial trench isolation is to be formed. Following the etching operation, an implant step dopes the remaining portion of the silicon film underlying the partial trench isolation region to achieve the desired conductivity. Full trench isolation regions are then patterned and formed, where the full trench isolation regions ensure isolation between devices on the SOI substrate. Subsequent masking and implantation steps are then used to achieve the desired doping within both the conductive area and the body region of the device. Following gate formation, additional implantation and masking operations are used to create the source and drain regions for the device. Subsequent formation of contacts and other layers of interconnect complete formation of the SOI device.
The invention can be better understood with reference to FIGs 1 - 15. FIG. 1 illustrates a cross-sectional view of an SOI substrate that is made up of a number of layers. The SOI substrate includes an underlying substrate layer 102, where the underlying substrate layer 102 may be silicon, sapphire, or other materials that provide adequate mechanical support for the overlying insulating and semiconducting layers. Silicon may be a preferable material for the underlying substrate layer 102 due to its desirable thermal and reactive characteristics.
An insulating layer 104 is formed on the underlying substrate layer 102. This may be accomplished by implanting oxygen or nitrogen ions within a semiconductive base material (i.e., a P-type monocrystalline silicon wafer) at an energy and a range of approximately 100 - 200 KeV to a dose of at least 1 x 101a ions per square centimeter and usually on the order of 1 x 1018 ions per square centimeter. Heat is typically applied to the semiconductor base material during implantation to maintain crystallinity. The substrate is then annealed at a temperature in a range of approximately 1000° - 1200° Celsius for a time within a range of approximately 1 - 5 hours. These steps form the buried insulator layer 104 and a semiconductor layer 106, which may be a monocrystalline layer, having a thickness less than approximately 2500Λ and more typically in the range of approximately 500 - 150θA.
In an alternate embodiment, the substrate of FIG. 1 may be formed by conventional wafer - wafer bonding techniques. In still an alternate embodiment, the semiconductor layer 106 is formed over a sapphire substrate or a substrate of another insulating material that is also capable of providing adequate mechanical support to the overlying silicon layer within which the device formation occurs.
FIG. 2 illustrates a cross-sectional view of the SOI substrate of FIG. 1 after additional processing. A nitride layer 208 is deposited overlying the semiconductor layer 106, which may be a silicon layer. Such deposition may be performed using low pressure chemical vapor deposition (LPCVD) or other deposition techniques. Nitride layer 208 acts as an anti-reflective coating (ARC), a chemical mechanical polishing (CMP) stopping layer, and as a hard mask which can be used in association with a soft mask, such as photoresist, to achieve desired etching characteristics with respect to the underlying semiconductor layer 106. In order to function in this capacity, the nitride layer 208 is typically formed to a thickness of approximately 500 - 2000A. In order to facilitate the formation of the nitride layer 208 overlying the semiconductor layer 106, a stress relief oxide layer may be formed overlying the semiconductor layer 106 prior to formation of the nitride layer 208. The stress relief layer may be formed of thermally or chemically grown silicon oxide, where the thickness of this stress relief layer may be on the order of 100 - 20θA.
A photo-resist layer 210 is formed overlying the nitride layer 208, where the photo-resist layer is patterned by conventional lithography techniques to define the desired location for the partial trench isolation region. In a typical SOI circuit, it may only be desirable to include a limited number of body-tied devices. For example, the percentage of devices on the circuit that are a body-tied device as opposed to a floating-body device may be on the order of 5 - 10%. In other embodiments, even fewer body-tied devices may be required. As such, the masking layer associated with patterning the photo-resist layer 210 for partial trench isolation region definition may be such that the density of patterned area associated with partial trenches is relatively low.
FIG. 3 illustrates a cross-sectional view of the SOI substrate of FIG. 2 following selective etching operations associated with forming the region in which the partial trench isolation region is to reside. Such etching operations may be accomplished by reactive ion etching (RIE), wet etching, or other anisotropic etching techniques. The reactive ion etch may include a first stage during which a portion of the nitride layer 208 is removed followed by a second stage during which the desired portion of the silicon layer 106 is removed. The first and second stages may differ in the particular chemistries utilized such that the desired layers are etched efficiently. The etching operations are controlled such that a limited portion of the silicon layer underlying the patterned region is removed. As such, a semiconductor portion of the semiconductor layer 106 is left intact. In an embodiment where the silicon layer 106 is approximately 1000A, it may be desirable to remove approximately 50θA of the silicon layer 106.
In other embodiments, the partial trench isolation regions may be formed by performing localized oxidation of silicon (LOCOS) to create silicon oxide in the region where the partial trench is to be located. Because the silicon oxide is non-conductive, these silicon oxide regions can serve as the partial trench isolation regions that are desired within the device.
FIG. 4 illustrates the SOI substrate of FIG. 3 during an implantation step. Note that the figures correspond to the formation of a body-tied N-channel device, or N-metal oxide semiconductor field effect transistor (MOSFET). As such, the body of the NMOS transistor is P-type. In order to provide a conductive path to the P- type body, the region underlying the partial trench is heavily P-doped (P+). Note that the doping operation illustrated in FIG. 4 is targeted at providing a highly conductive region underlying the partial trench. In other embodiments, the conductivity of the underlying region 220 of semiconductive material may be achieved through the P-well doping associated with the NMOS device.
FIG. 5 illustrates the SOI substrate of FIG. 4 following deposition and patterning of an additional layer of photo-resist 230 associated with formation of full trench isolation regions. Such full trench isolation regions provide desired isolation between individual devices or groups of devices that may be tied to a common body bias.
FIG. 6 illustrates the SOI substrate of FIG. 5 following removal of the portions of the nitride layer 208 and the semiconductor layer 106 in regions corresponding to full trench isolation regions. It should be noted that the complete removal of the semiconductor layer 106 occurs in the full trench isolation regions as opposed to the partial removal of this layer in the partial trench isolation regions. Complete removal of the semiconductor layer 106 in the full trench isolation regions exposes the underlying insulating layer 104 in these areas.
Etching of the desired portion of the nitride layer 208 and the semiconductor layer 106 to form the full trench isolation regions can be achieved by a reactive ion etch operation. Such a reactive ion etch may include the use of selective or non-selective chemistries. Because the reactive ion etch may damage the exposed sidewalls of the semiconductor layer 106, additional oxidation and thermal treatment may be used to recover the desired high quality crystalline structure and associated electrical properties along the sidewalls.
FIG. 7 illustrates the SOI substrate of FIG. 6 following removal of the photo-resist 230 and formation of field oxide 240, which is an insulating material, which is at least as deep as semiconductor layer 106 so that there is insulator extending from the top surface of semiconductor layer 106 to insulator layer 104. The field oxide formation may be accomplished by a blanket deposition of field oxide using a variety of techniques including high density plasma (HDP) deposition , LPCVD, and the like.
FIG. 8 illustrates a cross-sectional view of the SOI substrate of
FIG. 7 following removal of the undesired portions of the field oxide 240 and the complete removal of remaining portions of the nitride layer 208. The undesirable portions of the field oxide 240 may be removed by CMP operations, whereas the nitride layer 208 is removed using wet chemical etching. The wet chemical etching used to remove the nitride layer 208 may include the use of phosphoric acid, which selectively removes the nitride with minimal erosion of neighboring materials.
As described above, the field oxide included in the partial trench isolation region 250 may either be formed through deposition and selective removal as described with respect to FIG. 7 or through the localized oxidation of silicon (LOCOS) following definition of the region in which the partial trench isolation region is to reside (as shown in FIG. 3 above).
FIG. 9 illustrates a cross-sectional view of the SOI substrate of FIG. 8 during the implant operation associated with P-well doping. Note that in a complementary MOS (CMOS) process, both NMOS and PMOS devices are created. NMOS devices utilize P-wells to achieve the desired threshold voltages, whereas PMOS devices utilize N-wells. As such , portions of the substrate are typically masked off while doping of the well associated with the complementary devices occurs. Because the figures illustrate the formation of an NMOS device, the implantation operation occurring in FIG. 9 causes the remaining portions of the semiconductor layer 106 to become lightly P-doped to form the doped regions 320. The photoresist regions 310 are included to mask off areas that are not to be doped.
As mentioned earlier, if a processing step is not included for the exclusive doping of the conductive body contact region 220 underlying the partial trench isolation region 250, the P- implant operation may be used to dope the conductive region 220. Note that the concentration of the P- implant may not be as high as the concentration associated with the dedicated P+ implant described above with respect to FIG. 4. As such, conductivity of the underlying conductive region 220 may be reduced, but possibly still sufficient for certain practical applications.
FIG. 10 illustrates a cross-sectional view of the SOI substrate of
FIG. 9 following a number of processing steps associated with gate formation. Prior to the processing steps associated with gate formation, any stress relief layers included overlying the doped regions 320 are removed. Following removal of any stress relief layers, a gate dielectric layer 410, which may also be referred to as a gate insulator, is formed overlying the doped regions 320. The gate dielectric layer 410 may be made up of silicon oxide, silicon oxynitride, or other desirable high-K (high dielectric constant) insulating materials. The gate dielectric layer 410 may have a thickness that is less than 100A, and may typically be in a range of 20 - 8θA. Note that in some embodiments, multiple gate dielectrics of varying thickness may be included on the same substrate.
Following formation of the gate dielectric layer 410, a gate material layer 420 is formed. This may be accomplished by depositing a polycrystalline silicon (polysilicon) or amorphous silicon layer as the gate material layer 420. The gate material layer 420 may be doped in-situ, such that doped material is initially deposited, or doped during a separate operation that occurs following deposition. Following deposition of the gate material layer 420, patterning steps, which may include the use of a photo-resist layer 430, are used in conjunction with etching operations to selectively remove portions of the gate material layer 420 and the gate dielectric layer 410. As a result, the desired gate structure associated with the NMOS device is formed.
FIG. 11 illustrates a cross-sectional view of the SOI substrate of FIG. 10 during a subsequent implantation step. Sidewall spacers 510 are formed adjacent to the gate electrode 520 by conformally depositing and anisotropically etching a layer including oxide, nitride, or the like. Patterning, which may include the use of a photo-resist layer 530 is then performed to facilitate an N+ implant operation. The N+ implant serves to dope the source and drain regions for the NMOS device being formed. Formation of the source and drain regions produces a channel therebetween, where the channel may also be referred to as the body region 380 of the device. Such an implant operation can also be used to dope the gate 520. In some embodiments, such as that illustrated in the FIGs., the channel is adjacent to the partial trench isolation region 250 at one end and adjacent to the full trench isolation region 240 at the other end.
Thus, the body region 380 of the NMOS device is bounded by the source and drain regions formed by the N+ implant, the full trench isolation region 240, the partial trench isolation region 250, the body contact region 220, the gate dielectric layer 410, and the insulating layer 104. In other embodiments of the present invention, the body region 380 may be bounded on more than one side by partial trench isolation regions overlying a body contact region. The structure that includes the partial trench isolation region 250 and the body contact region 220 could be repeated at the opposite end of the body region 380 such that the desired biasing voltage could be applied from either or both directions such that resistivity associated with the body contact regions is further reduced. A further benefit of such an embodiment may be in that it provides additional advantages and robustness with respect to misalignments during photo-lithographic operations. Complementary devices (PMOS devices) include a similar region to the doped region 320 illustrated in FIG. 11. However, in these complementary devices, it is desirable to make such doped regions heavily N+ doped because these regions serve as the contact regions. As such, the implant operation used to dope the source/drain and gate for the NMOS device can be used to dope the contact region of complementary devices.
FIG. 12 illustrates a cross-sectional view of the SOI substrate of FIG 11. during a subsequent implantation step. Following removal of the photo-resist layer 530, a new photo-resist layer 620 is formed and patterned. The patterning for the photo-resist layer 620 is associated with doping of the source/drain and gate portions of complementary devices as well as the conductive region 610, which physically contacts region 220. Region 610 and contacts 220 share a contiguous border. Making the conductive region 610 highly doped facilitates the biasing of the body region 380. In other words, making the conductive region 610 and the conductive body contact region 220 heavily doped ensures a low resistance path to body region 380 of the NMOS device.
FIG. 13 illustrates a cross-sectional view of the SOI substrate of FIG. 12 following subsequent processing steps associated with completion of the NMOS device and associated interconnect. An interlevel dielectric (ILD) layer 730 is formed overlying the structure of FIG. 12. Subsequent planarization, patterning, and etching provide for a desirable ILD layer 730 that includes contact regions in which contacts 710 and 720, which may be metal, are formed. Note that formation of regions for additional contacts associated with the source and drain for the NMOS device (illustrated in FIG. 14) also occurs during such patterning and etching operations.
The contact 710 provides access to the gate electrode 520, where the contact 710 may be coupled to a portion of an overlying interconnect layer 750. Similarly, the contact 720 provides a means for coupling the overlying interconnect layer 750 to the conductive region 610 such that the proper bias can be applied to the body region 380. Standard metalization steps are used to form the desired traces in the interconnect layer 750, where these traces are separated by a second ILD 740. As is apparent to one of ordinary skill in the art, additional layers of interconnect can be added to allow for additional wiring capability for the circuit. Although many details of these layers and their deposition and patterning techniques are not described in detail herein, one of ordinary skill in the art appreciates that state of the art techniques (e.g. salicides, barrier layers, capping layers, etch stop layers, etc) may be relied upon in the formation of these layers.
FIG. 14 illustrates a top-down view of the semiconductor device formed using the various steps described with respect to FIGs. 1 - 13 above. Note that FIGs. 1 - 13 correspond to a cross-section of the device intersecting contacts 710 and 720 along an axis labeled with the large numeral 13. Features included in the top-down view of FIG. 14 not illustrated in the prior figures include source and drain regions 810, which are preferably doped by the N+ implant operations associated with FIG. 11. The contacts 820 provide connectivity to the source/drain regions 810, and interconnect layer portions 830 facilitate the provision of electrical signals to the source and drain regions 810.
The active portion of the device is generally surrounded by two types of isolation regions. A first isolation region, corresponding to the full trench isolation region 240 surrounds the majority of the active region, whereas a second isolation portion separates the active region from the conductive region 610. The partial trench isolation region 250 overlies the body contact region 220, which allows the potential applied to the conductive region 610 to be transferred to the body region 380 of the device that underlies the gate electrode 520. The potential that exists within the conductive region 610 is established by the contacts 720 which intercouple the conductive region 610 with a portion of the interconnect layer 750.
Another portion of the interconnect layer 750 is shown to be coupled to the gate electrode 520 via the contact 710. Note that in other embodiments of the invention, the contact 710 and the associated interconnect portion 750 may be positioned above the partial isolation region 250. In some embodiments of the invention, a similar partial field isolation region 250 may be positioned at the opposite side of the active region as compared with the partial field isolation region 250 illustrated in FIG. 14. In such embodiments, an additional conductive region and associated contacts and interconnect may be used to provide additional biasing capabilities for the body region of the device.
FIG. 15 illustrates a cross-sectional view of the device of FIG. 14 taken along a different cross-sectional axis (labeled with a large numeral 15 in FIG. 14). The cross-sectional view of the device depicted in FIG. 15 does not differ from the cross-sectional view of a conventional floating body device. As is shown, the body region 380, which includes the channel region of the device, is positioned between the source and drain regions 810, overlying the insulating layer 104 and below the gate dielectric 410. The full trench isolation regions 240 isolate the device on each side.
If a number of devices can operate with the same body region bias, a single conductive region may be used to supply this bias to the multiple body regions for the multiple devices. This can be achieved by separating the body regions of these devices from the conductive region using partial trench isolation regions accompanied by underlying body contact regions. The FIGs. and accompanying text describe the formation of an NMOS transistor. As is apparent to one of ordinary skill in the art, similar procedures using dopant materials of opposing conductivity (i.e. P+ doping for source/drain, N+ doping for the conductive body region, etc) can be used to form PMOS transistors that provide the biasing advantages for SOI devices without the added gate capacitance and other detrimental side effects associated with prior- art body-tied devices.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments.
However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A semiconductor device structure comprising: a transistor having a channel of a first conductivity type formed in a semiconductor layer, the semiconductor layer being over an insulating layer and having a top surface; a first insulator adjacent to the transistor extending from the top surface through the semiconductor layer to the insulating layer; and a second insulator adjacent to the transistor in the semiconductor layer extending from the top surface only partially through the semiconductor layer so as to leave a first portion of semiconductor material below the second insulator, the first portion being of the first conductivity type.
2. The semiconductor device structure of claim 1 , wherein the first portion is heavily doped.
3. The semiconductor device structure of claim 1 , further comprising a heavily doped region of the first conductivity type in the semiconductor layer extending from the top surface to physically contact the first portion.
4. A semiconductor device structure, comprising;. an insulating layer; a semiconductor layer having a top surface and overlying the insulating layer; an active region in the semiconductor layer; an isolation region surrounding the active region, wherein the isolation region comprises: a first isolation portion having a first insulator extending from the top surface through the semiconductor layer to the insulating layer; and a second isolation portion having a second insulator extending between the top surface and a first semiconductor portion of semiconductor material below the second insulator.
5. The semiconductor device structure of claim 4, wherein the active region comprises: a source region adjacent to the first isolation portion; a drain region adjacent to the first isolation portion; and a channel region adjacent to the second isolation portion.
6. The semiconductor device structure of claim 5, wherein the channel region has a first end and a second end, the first end being adjacent to the second isolation region and the second end being adjacent to the first isolation region.
7. The semiconductor device structure of claim 6, wherein the channel region and the first semiconductor portion have a first conductivity type.
8. The semiconductor device structure of claim 7, wherein the first conductivity type is P-type.
9. The semiconductor device structure of claim 7, wherein the first conductivity type is N-type.
10. The semiconductor device structure of claim 6, wherein the first semiconductor portion is heavily doped.
11. The semiconductor device structure of claim 4, wherein the first semiconductor portion is a first conductivity type, the active region has first and second regions of a second conductivity type and a third region of the first conductivity type, and the third region physically contacts the first semiconductor portion of semiconductor material.
12. The semiconductor device structure of claim 11 , wherein the third region comprises a channel.
13. The semiconductor device structure of claim 12, wherein the first semiconductor portion is heavily doped.
14. A method of making a semiconductor device, comprising: providing a substrate having a semiconductor layer having a top surface and overlying an insulating layer; selectively etching into a first area in the semiconductor layer to remove the semiconductor layer in the first area to expose the insulating layer in the first area; selectively etching into a second area in the semiconductor layer to remove a portion of the semiconductor layer in the second area and to leave a first semiconductor portion of the semiconductor layer in the second area; doping the first semiconductor portion to leave the first semiconductor portion heavily doped to a first conductivity type; depositing an insulating material in the first and second areas on the insulating layer and the first semiconductor portion, respectively; forming a gate insulator over the semiconductor layer in a third area bounded at least in part by the first area and the second area; forming a gate over the gate insulator; and forming a source and drain in the third area to leave a channel therebetween, the channel being adjacent to the second area.
15. The method of claim 14, wherein the source and drain are a second conductivity type and the channel is the first conductivity type.
16. The method of claim 14, wherein the first conductivity type is P- type.
17. The method of claim 14, wherein the first conductivity type is N- type.
18. The method of claim 14, further comprising doping the semiconductor layer to the first conductivity type at a fourth area having a border which is contiguous with a border of the second area.
19. The method of claim 18, further comprising forming a first metal contact at the fourth area.
20. The method of claim 19, wherein the channel has a first end and a second end, the first end being adjacent to the second area, and the second end being adjacent to the first area.
21. The method of claim 20, wherein the gate extends over the second area, and further comprising forming a second metal contact to the gate over the second area.
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