WO2002021697A1

WO2002021697A1 - Fractional-n frequency synthesiser

Info

Publication number: WO2002021697A1
Application number: PCT/GB2001/003972
Authority: WO
Inventors: Taoufik Bourdi; Markku Henriksson; Assaad Borjak; Izzet Kale
Original assignee: Nokia Corporation
Priority date: 2000-09-05
Filing date: 2001-09-05
Publication date: 2002-03-14
Also published as: GB0021800D0; AU2001284267A1

Abstract

There is disclosed a method of determining a value for a divider of a frequency synthesiser. The method includes the steps of: determining the necessary divider ratio to obtain the desired frequency from the reference frequency, and generating a fraction value of the divider ratio; generating n coefficients in dependence on the fraction value, the n coefficients being generated in an nth order accumulator; and determing an offset value associated with the fraction in dependence on the n coefficients. The step of determining the offset value is preferably determined by formula (I). Where C¿k? is the k?th¿ coefficient, Nacc is the order of the accumulators used in the step of generating the coefficients, and α¿r? is a coefficient taken from Pascal's triangle. Circuitry for implementing the method is also disclosed.

Description

FRACTIONAL-N FREQUENCY SYNTHESISER

Field of the Invention

The present invention relates to a fractional-N synthesiser, and particularly but not exclusively to such a synthesiser for use in elements of a telecommunications network.

Background to the Invention

Synthesisers are used to generate signals of a given frequency. This frequency signal is often mixed with a receive signal to down-convert the received signal to a lower frequency, or mixed with a signal to be transmitted to convert the signal to a higher frequency, in telecommunication applications such as wireless applications.

Such frequency synthesisers are usually based on a phase locked loop (PLL) structure. The PLL includes an integer divider in the feedback loop. Conventional integer-divider based PLL' s have synthesised output frequencies with a step equal to the sampling frequency of. the phase detector (PFD) of the loop. An increase in the sampling frequency of the phase detector introduces advantages by increasing the loop bandwidth and reducing the integer divider ratio. As a result, a reduction in the settling time of the loop and an improvement in the phase noise profile of the loop is achieved. Such advantages can be achieved with fractional-N PLL' s when the feedback divider is a fractional divider, i.e. a fractional-N divider.

However, the fractional-N method is impractical since it introduces fractional spurs and hence some additional compensation methods are needed to suppress those spurs.

Referring to Figure 1, there is shown a known PLL frequency- hopping synthesiser employing delta-sigma modulation for controlling an integer divider. By a combination of over sampling techniques and noise shaping circuitry utilising delta-sigma modulators, the problem of cyclic errors (i.e. fractional spurs) is reduced.

Referring to Figure 1, a crystal oscillator 112 generates a reference frequency F_REF on line 114. The reference F_REF forms an input to phase detector 113. The phase detector 113 compares the reference frequency F_REF with a feedback -frequency FFEEDB_ACK provided on a line 122. The phase detector 113 generates an error signal on line 116 based on the comparison.

The error signal is filtered by a low pass filter 114 and provided on a line 119 to a voltage controlled oscillator

(VCO) 116. Thus the output of the low pass filter 114 is a voltage signal suitable for controlling the VCO 116. The VCO 116 provides a signal on line 120 having an output frequency F₀uτ- The output frequency F₀uτ provided by the VCO 116 is determined by the value of the filtered error signal.

The output frequency of the VCO 116, as well as forming a signal to be used elsewhere, is also fed back to a divider 118. The divider 118 is a multi-modulus divider which toggles between several integer ratios. The toggling of the divider 118 is controlled by control signals on line 124 from a delta- sigma modulator 110. The delta-sigma modulator 110 additionally receives the reference signal having frequency F_REF on line 114, which provides the clock signal for the delta-sigma modulator 110.

The output frequency F₀oτ is always much greater than the reference frequency F_REF. An ideal divider ratio for the divider 118 is determined in dependence on the ratio of the reference frequency F_REF to the desired output frequency F₀oτ- In practice, this divider ratio will comprise a fraction and an integer. In order to ensure that the average divider ratio corresponds to the ideal divider ratio, the integer value in the divider 118 is switched between integer values calculated by the delta-sigma modulator 110. These values will vary above and below the integer value of the ideal divider ratio. By controlling the toggling between the values in the divider 118, it is possible to ensure that the mean or average value applied to the VCO 116 will be such that it is the current multiple (both integer and fraction) of the reference frequency F_REF.

'l

The delta-sigma modulator, or logic block, 110 generates a stream of bit values, which control the integer values of the divider 118. The delta-sigma modulator 110 has a channel select input 126, which controls the bit pattern output by the delta-sigma modulator 110. A different bit pattern is output by the delta-sigma modulator 110 according to the ratio under which the divider 118 operates. Thus a different pattern is output for example if the output frequency is 5.5 times the reference frequency, as compared to when the output frequency is 5.25 times the reference frequency. The output of the divider 118 is a signal having a frequency F₀uτ divided by the average of the integer values in the divider, taking into account the relative frequencies of those values. This value is the feedback frequency F_FEEDBAC on line 122.

Referring now to Figure 2, there is illustrated the structure of a typical fourth order delta-sigma MASH modulator. A MASH structure is shown, rather than a single bit high order delta- sigma modulator, because MASH structures are unconditionally stable . As the delta-sigma MASH modulator of Figure 2 is a fourth order modulator, the structure employs four accumulators 200ι to 200₄. Any delta-sigma MASH modulator will have a number of accumulators corresponding to the number of the order of the modulator.

Each accumulator 200 receives a first input on a respective line 202 and a second input on a respective line 204. Each accumulator generates an output on a respective line 208. Each output 208 forms an input to a respective delay element 206, which each generate the respective second input 204. The first input 202]_. of the first accumulator 200χ is the divider fractional value, appropriately scaled on line 127. For example, if the ideal divider ratio is 0.2, then the value on line 127 will be a binary representation of the value 0.2, scaled to an appropriate value based on the number of bits available in the system. The first input 202₂ to 202₄ of the second to fourth accumulators is the respective output 208ι to 2O8₃ of the preceding accumulator.

Each accumulator 200 has a respective further output 212

The further output 212₄ of the final accumulator forms an input to a delay element 216₃ and a summer 214₃. The summer 214₃ receives on a line 220₃ the output of the summer 216₃. The summer 214₃ generates on an output line 218₃ the difference between its two inputs, and provides such as an input to a summer 210₃. The summer 210₃ is the third of three summers having a first input connected to the further output of the respective three accumulators. Each of the summers 210χ to 2IO₃ receives a second input on a respective line 218χ to 218₃ from a summer 214ι to 214₃. The summers 214ι and 214₂ receive inputs on first lines 220ι and 220₂ from respected delay elements 216ι and 216₃ and second inputs on lines 220ι and 220₂ from the summers 210₂ and 210₃. The inputs to the delay elements 216χ and 216₂ are provided by the respective outputs of the summers 210₂ and 210₃ on lines 220χ and 220₂. The summer 210ι generates at its output the control signal 124 to the divider 118.

Each of the accumulators 200 shown in Figure 2 represents a first order modulator having the modified model shown in Figure 3.

A delta-sigma modulator model of one of the accumulators 200 of Figure 2 is shown in Figure 3a. An input K on line 312 forms a first input to a summer 302, the second input being provided by the output of the accumulator on line 320. The output of the summer 302 is provided on line 314 as a first input to a further summer 304. The further summer 304 provides an output on line 316 to a delay element 306 which in turn generates an output on line 318 which forms the second input to the summer 304. The output on line 318 forms an input to a block 308 including a summer 310 which receives a second input on line 322 a signal e [n] . The output of the summer 310 is the output of the accumulator on line 320, which is represented by the signal b[n].

Referring to Figure 3b there is shown a modified modulator model of the model shown in Figure 3a. The modified modulator model includes the summers 302, 304 and 310 as in Figure 3a. However, the delay element 306 is removed such that the output of the summer 304 directly forms the input 318 to the summer 310. In addition the signal on line 318 forms an input to a delay element 326 the output of which forms the second input to the summer 304. The output of the modified modulator model on line 320 forms an input to a further delay element 328, the output of which forms the second input to the summer 302.

Referring once again to Figure 2, it can be seen that the four accumulators 200ι to 2OO₄ generate four respective coefficient values Ci to C₄ on lines 212χ to 212₄. The four accumulators

200χ to 2OO4 and their respective delay elements 206 to 206₄ are generally designated by reference numeral 250, and can be considered to be a coefficient generator block. The remainder of the functional blocks of Figure 2, generally designated by reference numeral 252, process the coefficient values Ci to C₄ to generate on the output line 124 an output value which represents the amount by which the integer value of the divider should be varied. For example, and as will be discussed in further detail hereinbelow with reference to the present invention, for a fourth order accumulator the value on line 124 may vary between -7 and +8.

As can be seen from Figure 3b, the modified modulator model has no delay in the forward path. The input K on line 312 is the required fraction scaled by the size of the accumulator.

The structure shown in Figures 2 and 3 is not very efficient from an implementation point of view, especially if the order of the modulator is increased. Increasing the order of the modulator improves the in-band noise and thus reduces any frequency and phase errors. However, the hardware implementation of the structures shown in Figures 2 and 3 is complex and becomes more complex the higher the order. As the order increases, the modulator clock speed becomes reduced, and consequently the over-sampling properties of the delta- sigma modulator are affected. US Patent No. 4,965,531 and US Patent No. 5,038,117 both disclose examples of fractional-N frequency synthesisers including frequency dividers having selectable integer divide numbers which are periodically, temporarily altered to provide an average rational divide number for the frequency divider. The use of multi-modulus dividers in these patents reduces spurious frequencies and/or phase noise.

It is an object of the present invention to provide an improved technique for implementing a fractional-N divider whilst ensuring reduction of spurious frequencies .

Summary of the Invention

In accordance with a first aspect of the present invention there is provided a method of determining a value for a divider of a frequency synthesiser, including the steps of: determining the necessary divider ratio to obtain the desired frequency from the reference frequency, and generating a fraction value of the divider ratio; generating n coefficients in dependence on the fraction value, the n coefficients being generated in an n^th order accumulator; determining an offset value associated with the fraction in dependence on the n coefficients .

The step of determining the offset value may include applying the n coefficients in an algorithm.

The step of determining the offset value may be determined by:

Nacc

Σ Σ ⁽-ⁱ: r+l c._r.C_k(n-r+l)

K=l r=l Where C_k is the k^th coefficient, Nacc is the order of the accumulators used in the step of generating the coefficients, and o__r is a coefficient taken from Pascal's triangle.

The determining step may further generate an integer value of the divider ratio, the method further including the step of combining the offset value and the integer value to thereby generate the divider value.

The may further include the step of loading the divider value into the divider. The step of loading the divider value into the divider may include adapting the value in dependence on the characteristics of the divider.

The step of determining the necessary divider ratio may include receiving the value of the reference frequency and the value of the desired frequency, wherein the fraction value is determined by dividing the desired frequency value by the reference frequency value.

The method may further include the steps of determining the divider values for all possible integer values and all possible fraction values, and storing said divider values in a memory.

A storage location of the memory may be selected responsive to a particular integer value and fraction value, the stored divider values in said location being output under control of a counter. The method may include the step of cycling through the counter to access the stored divider values in a selected location as long as that location is selected.

The method may include the step of randomly selecting the start point in a selected location on each cycle.

The method may include the step of selecting a storage location of the memory responsive to a particular set of generated n coefficients .

The may include the step of selecting the storage location of the memory additionally responsive to the integer value of the divider ratio.

The frequency synthesiser may perform the steps of: comparing a feedback frequency generated by the divider to the reference frequency; generating a control signal corresponding to a phase difference therebetween; applying the control signal to a voltage controlled oscillator, the output of which comprises the synthesiser output; and dividing the synthesiser output by the determined divider value to thereby generate the feedback frequency.

In a further aspect the present invention provides a frequency synthesiser comprising: input means for receiving a reference frequency; output means for providing a desired output frequency; means for dividing the desired output frequency by a plurality of divider values; and control means for generating the divider values, wherein the divider values are generated by: determining the necessary divider ratio to obtain the desired frequency from the reference frequency, and generating a fraction value of the divider ratio; generating n coefficients in dependence on the fraction value, the n coefficients being generated in an n^th order accumulator; and determining an offset value associated with the fraction in dependence on the n coefficients .

The divider values may be generated by applying the relationship :

Nacc k

∑ ∑ (-l)^r+1.α_r.C_k(n-r+l) K=l r=l

where C_k is the k^th coefficient, Nacc is the order of the accumulators, and α_r is a coefficient taken from Pascal's triangle .

The divider values may be generated by further generating an integer value of the divider ratio, wherein the offset value and the integer value are combined to generate the divider value .

The control means may include a memory, wherein the divider values for all possible integer and fraction values are stored in the memory.

The storage location of the memory may be selected responsive to a particular integer value and fraction value, the control means including a counter for outputting the data stored at that location.

The counter may cyclically counts such that the stored data is cyclically output whilst the particular integer value and fraction value remain unchanged. There may be provid'ed means for randomly selecting the start point of the selected data on each cycle.

The control means may include an accumulator block for generating the plurality of coefficients.

A storage location of the memory may be selected responsive to a particular set of coefficient values.

The storage location of the memory may be selected further responsive to a particular integer value.

The memory may be a look-up table.

The control means may further include an accumulator block for generating the coefficients.

Thus the present invention provides an implementation of a fast noise shaping algorithm to control a programmable divider (counter) capable of operation both as GSM and DCS RF frequencies. The algorithm may be implemented fully or partially in hardware depending on application requirements, such as speed, phase coherency accuracy etc.

Brief Description of the Drawings For a better understanding of the present invention and to show how the invention may be carrier into effect, reference is now made by way of non-limiting example to the accompanying drawings in which:

Figure 1 shows a known synthesiser;

Figure 2 shows a known example of a delta-sigma modulator of the synthesiser of Figure 1; Figures 3a and 3b shown known models of the accumulator of the delta-sigma modulator shown in Figure 2;

Figure 4 shows a block diagram of an implementation of a fractional-N control technique in accordance with the invention; Figure 5 illustrates a first embodiment of an implementation of the invention;

Figure 6 illustrates a modulator model for use in the embodiment of Figure 5;

Figure 7 illustrates a second embodiment of an implementation of the present invention;

Figure 8 illustrates a third embodiment of the present invention;

Figure 9 shows a schematic view of a typical wireless cellular telecommunications network; and Figure 10 shows a base transceiver station incorporating the synthesiser of the invention.

Referring to Figure 4, there is shown a block diagram of a first embodiment of the present invention. Figure 4 illustrates a block 400 which provides integer divider values to the multi-modulus divider 118 of Figure 1. As in Figure 1, the divider receives the output signal having frequency F₀uτ on line 120 as an input, and generates the feedback signal having frequency F_FEEDBACK on line 122. In accordance with the present invention, the block 400 generates a signal on line 428 for controlling the value in the divider 118.

The block 400 comprises a ratio calculator 404, a mapping algorithm block 406, a fraction data processor 408, a combining block 412, and a divider interface block 410. The mapping algorithm block 406, and combining block 412 each receive an input clock signal comprising the reference signal on line 114 having a frequency of F_REF.

The block 400 receives on line 114 at an input the reference frequency F_REF, and on a line 402 a signal representing the required frequency input having a frequency of F_REQ. The reference frequency signal F_REF and the required frequency input signal F_REQ form inputs to the ratio calculator 404. Based on the required frequency input and the reference frequency the ratio calculator 404 is able to determine the divider ratio which is required to be applied in the divider 118. The calculated ratio will comprise an integer value and a fractional value. The ratio calculator 404 outputs the digital value corresponding to the integer on line 416, and outputs the digital value corresponding to the fraction on line 418.

The integer value on line 416 directly forms an input to the combining block 412. The fraction value on line 418 is provided to the fraction data processor 408 for further processing.

The digital fractional value on line 418 is scaled by the ratio calculator 404 according to the number of bits available on the lines 418. Thus if the signal line 418 is a 24 bit signal line, the fractional value is scaled by 2²⁴. Scaling the fractional value in this way may introduce errors in its representation, if the number of bits available is not sufficient for the fraction to be completely represented.

The fraction data processor 408 implements the same function as the block 250 of Figure 2, and consequently outputs a sequence of coefficients Ci to C_n on its output on lines 420, where n is the order of the fraction data processor. Thus for a fourth order implementation, four coefficients Ci to C₄ are output on line 420.

In accordance with the present invention, the mapping algorithm block uses the coefficients Ci to C_n presented on lines 420 to generate a value on line 422 representing an instantaneous offset value by which the integer value on line 416 should be varied in the divider 118. The mapping algorithm block uses the values Ci to C_n in the following algorithm:

Where :

Nacc k

Yout(n)= ∑ ∑ (-l)^r+1.α_r.C_k(n-r+l) K=l r=l

Nacc is the number of accumulators used within the modulator; and α_r are coefficients taken from Pascal's triangle.

Thus, a much more efficient technique for generating the instantaneous offset value than that previously known, and as represented by block 252 of Figure 2, is provided.

The mapping algorithm block 406 then outputs on lines 422 a digital value representing the value by which the integer value on line 416 should be offset, being the value Y_out(__) ■

The combining block 412 then combines the integer value on line 416 with the offset integer value on line 422. Thus if the offset value on line 422 is +3, then the combining block 412 increases the integer value on line 416 by 3. If the offset value on line 422 is -2, then the combining block 412 decreases the integer value 416 by a value of 2. The thus combined value is output by the combining block 412 on line 426 to the divide interface block 410.

The divider interface block 410 functions merely to format the integer value presented by the combining block 412 on digital lines 426. The value is formatted into a form suitable for loading into the divider 118, in dependence on the particular implementation of the divider.

The integer value generated by the combining block 412 is then loaded into the divider 118 by the divider interface block 410. The divider interface block 410 may process the value generated by the combining block in an appropriate manner to be loaded into the divider 118.

The block 400 is controlled by a clock signal at the reference frequency F_REF. Hence the divider value is updated on every cycle of the reference frequency F_REF.

Although in this preferred embodiment the coefficient values Ci to C_n are generated by the fraction data processor using the block 250 of Figure 2, other techniques for generating the coefficient values Ci to C_n may be used.

Referring now to Figure 5, there is shown an alternative implementation of the invention as illustrated by the block diagram of Figure 4. Figure 5 shows an implementation of the invention utilising a ROM or programmable ROM (PROM) . As is seen in Figure 5, the block 400 is replaced by a block 500 comprising a programmable ROM (PROM) . In addition a counter 510 for generating a count sequence is provided. The counter 510 receives the reference frequency F^_F on line 114. The frequency selection signals are provided on line 504 to the block 500, and one of such signals on line 506 is provided to the counter 510. The counter 510 generates count signals on line 508 to the block 500.

The frequency selection signals on line 504 preferably comprise the integer and fraction values for the required divider value. As will be described in further detail hereinbelow, the integer and fraction values function in this embodiment as addresses for accessing the contents of the PROM 500. These signals may also include a control signal indicated when a new required frequency input, and hence divider value, is generated. This control signal is then also provided on line 506 to the counter 510 to reset the counter to begin counting from zero.

In this embodiment, the PROM 500 is pre-loaded with all possible values on the line 428 of Figure 4 for all possible combinations of integer and fraction values. The current integer and fraction values, presented on lines 504, point to the location in the PROM where the calculated values for the given integer and fraction values are stored. The counter 510 then controls the memory to output the sequence of values stored at that location line 502 to the divider 118. Thus, in this embodiment it is necessary for all possible integer and fraction combination values to be simulated, and the associated results generated on line 428 stored.

" Figure 5 thus effectively illustrates a full software implementation of the present invention.

The size of the programmable ROM 500 of Figure 5 becomes very significant as the order of the delta-sigma modulator is increased in order to improve the noise shaping characteristics. That is, as the order of the delta-sigma modulator increases, the number of bits required to be stored in the programmable ROM increases, and consequently the number of bits provided on control line 502 to the divider 118 increase. A technique for keeping the output for controlling the divider on line 502 to a minimum, without the loss of modulator precision, is to use a delta-sigma bit concentrator of the same order as the accumulator 250 in order to reduce the multi bit output into a single bit.

An example of a known delta-sigma bit concentrator is shown in Figure 6. The use of the delta-sigma bit concentrator of Figure 6 enables the use of a dual modulus divider for implementing the divider 118. The delta-sigma bit concentrator of Figure 6 enables an efficient simulation of the values for storing in the PROM 500.

The delta-sigma data concentrator receives a multi-bit input on line 654 and outputs a corresponding single-bit output on line 650. The delta-sigma bit concentrator comprises three identical blocks 670_a to 670_c. Block 670_a comprises a summer 656_a which receives as a first input the multi-bit signal on line 654. A second summer 658_b receives as a first input the output of the summer 656_a. The output of the summer 658_a forms an input to a limiter 660_a which generates a first output of the block 670_a. A delay block 662_a receives an input from the output of the summer 658_a and generates as its output the second input to the summer 658_a. A delay block 664_a receives as its input the output of the limiter 660_a and generates as its output the second input to the summer 656_a. The input to the limiter 660_a forms a second output of the block 670_a. The blocks 670b and 670_c are similarly constructed. The first output of the block 670_a forms an input to a summer 666 and the input to a summer 618. The second output of the block 670_a forms a second input to the summer 666. The output of the summer 666 forms the input to the summer 656_b of the block 670b- The first output of the block 670_b forms an input to a summer 668 and an input to a summer 610. The second output of the block 670_b forms the second input to the summer 668. The output of the summer 668 forms the input to the summer 656_c of the block 670_c. The block 670_c has a single output, corresponding to the first outputs of the block 670_a and 670_b, which forms an input to a delay element 614 and a summer 608. The summer receives as its second input the output of the delay element 614. The output of the summer 608 forms the second input to the summer 610. The output of the summer 610 forms an input to a summer 616 and a delay block 612. The output of the delay block 612 forms the second input to the summer 616. The output of the summer 616 forms the second input to the summer 618. The output of the summer 618 forms an output on line 652 which can be considered to be an output of a first stage of the delta-sigma modulator. The output on line 652 forms an input to the second stage of the delta-sigma bit concentrator.

The signal on line 652 forms a first input to a summer 620. The output of the summer 620 forms the first input to the summer 622, and an input to a delay element 628 the output of which forms a second input to the summer 620. The output of the summer 622 forms an input to the summer 624 and input to a delay element 630, the output of which forms a second input to the summer 622. The output of the summer 624 forms an input to a summer 626 and a delay element 632, the output of which forms a second input to the summer 624. The output of the summer 620 forms an input to an alpha block 636, the output of which forms a first input to a summer 638. The second input to the summer 638 is provided by the output of the summer 622. The output of the summer 638 forms an input to a beta block 640, which provides at its output a second input to the summer 626. The output of the summer 626 forms an input to a limiter 634, the output of which forms the one-bit output on line 650 of the delta-sigma bit concentrator. In addition the output of the limiter 634 forms an input to a delay element 642, the output of which forms a negative input to the summer 618.

The alpha block 636 receives a control signal on line 646, and the beta block 640 receives a control signal on line 648. The alpha and beta blocks are scaling gain blocks used to make sure that the single loop modulator used as a concentrator is stable at all times. However, for different fractional inputs these blocks need to be tuned for optimum results and stability. Hence the control signals update these gain blocks when needed.

With the implementation illustrated with reference to Figures 5 and 6, the input bit stream and the corresponding output bit stream are captured from software floating point simulation and stored in a ROM or PROM. To control the divider 118, the bit sequence representing the required frequency is read from the ROM in a cyclic manner until a new frequency is selected. The bit stream is fed to the dual-modulus divider at the rate of the sampling frequency. Thus the counter 510 is clocked at the sampling frequency, and can be reset either when the count sequence is completed or when a new frequency is selected.

The embodiment of Figure 5 will now be further described with reference to a particular example. In this example, GSM frequencies in the range of 890 to 925 MHz, with 200 KHz channel spacing, are considered. This provides 175 different frequency divisions.

For each division with a minimum error of 10^"6, a stream of 2¹⁶ bits is captured. The first 10,000 bits representing the time required for the accumulator to settle are filtered out, to remove the error in the fractional division. This represents 55,536 samples for each of the 175 different divisions. Thus, for all divisions, a storage memory of 1.2 megabytes is required. In another example, 2.6 megabytes of memory would be required to cover all possible DCS frequencies.

From this example, it can be readily seen that the implementation of Figure 5 is expensive in terms of memory size required. Although such an implementation may be realistic in the foreseeable future, at the present time the size of the ROM is prohibitive for implementation on a single chip. However, if a complete ASIC implementation is not required, then the ROM could be implemented off-chip.

However, the implementation of- Figure 5 suffers from a further potential disadvantage in the cyclic behaviour of the count sequence in the counter block 510. This can be best understood by the following example. Using a sampling frequency of 208 MHz (which gives a clock period of 4.8ns), the number of samples stored in the memory for each fraction is 55,536. The duration for the bit stream sequence representing the fraction is T = (2¹⁶-10, 000) \208 MHz = 267 microseconds .

This means that the count sequence repeats three times within a GSM burst, which lasts for 577 microseconds. This results in the production of at least one spur at approximately 4 KHz. To solve this problem, it is proposed to introduce spur cancellation digital circuitry, using a start sequence randomise block as shown in the further embodiment of Figure 7. '

Referring to Figure 7, the implementation of Figure 5 is modified by the provision of a start sequence randomise block 700. The start sequence randomise block 700 receives a randomise reset signal on line 704 which is provided with the frequency selection signals 504. The start sequence randomise block 700 generates a control signal on line 702 to the counter 510.

The start sequence randomise block 700 ensures that there is no cyclic repetition of the bit sequence within the GSM burst. This is achieved by randomising the start sequence entry in the memory 500 each time a repetition occurs. Thus, whenever a particular set of values stored in the PROM is read out several times, each time the set of values is repeated the start sequence randomise block 700 acts to randomly select the starting point within the set of values .

In a further embodiment,- a hybrid implementation of the present invention is provided. In such a hybrid solution, the fraction data processor of Figure 4 may be implemented efficiently in hardware, and the mapping algorithm block 406, the combining block 412, and divider interface block 410 of Figure 4 may be implemented in either software or hardware form, or a combination of both depending upon the application requirements. The mapping algorithm block 406 is the fundamental part of the modulator .

Where high speed operation is required, together with phase coherency and accuracy, a software implementation of the mapping algorithm block 406 is preferable. In such a case, the output of the fraction data processor 408 can be used to control calculated, fixed algorithm coefficients that are stored in fast access memory locations.

Such an implementation is now described with reference to Figure 8. The block 400 of Figure 4 is modified to a block comprising the ratio calculator 404 of Figure 4, the fraction data processor with a forced preset 802, and a ROM look-up table 804. These elements are generally designated by block 800 in Figure 8.

As in Figure 4, the ratio calculator 404 generates, in dependence on the frequencies F_REF and F_REQ, the fraction and integer values for the divider of the phase locked loop.

Thus the fraction data processor generates the required fraction with suitable scaling on lines 806 which form an input to the ROM look-up table 804. As described with reference to Figure 8, the outputs on lines 806 is the coefficients Ci to C_n.

Depending on the values output, a pre-stored digital sequence in the memory or look-up table, representing a predetermined frequency or phase, is read out.

As in the ROM implementation described hereinabove, for each possible integer value the ROM look-up table 804 stores all possible values of the outputs on line 428 for different coefficient values Ci to C_n. Thus, a simulation is carried out to calculate all possible values, and then the values stored in the look-up table. The coefficients Ci to C_n on line 806, in combination with the integer value on line 416, point to the appropriate set of stored values in the look-up table, which are output on line 808.

During each hopping period, to guarantee phase coherency and fractional spurious suppression for any input division ratio, the fraction data processor may be forced to a preset phase state by a control signal (not shown) .

With this arrangement, a small amount of memory space is required. This can be illustrated for a third order noise shaping modulator. The output of the fraction data processor is a 6-bit word, as can be derived from equation 1. The 6-bit word on line 806 addresses a 3-bit entry in the memory table 804.

For the DCS frequency range, the memory requirement is 1,125 bits . The technique can be changed to adapt to any frequency band by simply reprogramming the memory.

The output of the control algorithm with respect of the accumulator control sequence is:

Where :

Nacc k Yout(n)= ∑ ∑ (-l)^r+1- _r.C_k(n-r+l)

K=l r=l Nacc is the number of accumulators used within the modulator; and α_r are coefficients taken from Pascal's triangle.

As an example, the algorithm for a 5^th order MASH modulator can be derived:

Yout(n) = C₁(n)+C₂(n)-C₂(n-l)+C3(n)-2C3(n-l)+C₃(n-2) +C₄(n)-3C₄(n-l)+3C₄(n-2)-C₄(n-3)+C₅(n)-4C₅(n-l) eqn. (2)

+6C₅ (n-2) -4C₅ (n-3) +C₅ (n-4 )

Lower order algorithms can be easily derived by removing the higher order terms from equation (2) . For example, the algorithm for a 3^rd order MASH modulator is :

Yout (n)=Cι(n)+C₂(n-l)+C₃ (n) -2C₃ (n-1) +C₃ (n-2) eqn. (3)

The algorithm for a 4^th order MASH modulator is:

Yout (n)=Cι (n)+C₂(n)-C₂ (n-1) +C₃(n)-2C₃ (n-1) +C₃ (n-2) eqn. (4) +C₄ (n) -3C₄ (n-1) +3C₄ (n-2) -C4 (n-3)

Using a derived equation from equation (1), a mapping algorithm can be implemented. This algorithm saves one bit in the implementation (from Nacc to Nacc-1 bits) and it is illustrated in the following example for a 4-accumulator modulator.

Taking the example of the 4^th order modulator, the maximum Yout (n) is equal to 8 and the minimum Yout(n) is equal to -7. To represent this Yout (n) using two's complement arithmetic, at a first glance, we require 5 bits in total, where 4 bits are to represent the numbers between 8 and -7 and the fifth bit is for the sign of a number. Looking closely at the boundary limits of the outputs, however, it is possible to use a 4-bit representation including the sign it. This is achieved by using the mapping algorithm illustrated in Table 1.

* Special mapping is required for this case.

Table 1 If a software implementation is chosen, the output of the fraction data processor 408 may be mapped directly to the divider 118 by means of a look-up table that stores the required sequence representing the division' values, as is illustrated in Figure 8.

Reference is now made to Figure 9, which shows a known cellular telecommunications network in which embodiments of the present invention may be used. The area covered by the network 201 is divided into a plurality of cells 203. Each cell 203 is served by a base transceiver station 207, which is arranged to transmit signals to, and receive signals from, terminals 209 located in the cell 203 associated with the respective base transceiver station 207. The terminals 209 may be mobile stations which are able to move between cells. In the GSM standard (global system for mobile communications) each base transceiver station is arranged to receive and transmit on a different number of frequencies. This is because the GSM standard using a time division multiple access technique. In the GSM standard, each channel has a bandwidth of 200 KHz.

Further reference is now made to Figure 10, which shows part of a typical base transceiver station 301. In Figure 10, only the receive part of the base transceiver station is shown. The base transceiver station 301 has an antenna 311, which is arranged to receive signals from mobile stations in the cell served by the base transceiver station 209. Depending on the construction of the base transceiver station, a receive part such as shown in Figure 10 may be provided for each channel

(or frequency) which is received by the base station 301 at the same time. Only received part is shown in Figure 10. It should be appreciated that more complex arrangements may be used in which a single receive part is able to receive all of the frequencies at the same time. The receive part has a first band pass filter 312 which is arranged to filter out signals which fall outside the receive band in which the available channels are located. The filtered output is input to a first low noise amplifier 315 which amplifies the received signals. The amplified signal is then passed through a second band pass filter 317 which filters out any noise, such as harmonics or the like introduced by the first amplifier 315. The output of the second band pass filter 317 is connected to a mixer 319 which receives the output of a voltage controlled oscillator. This voltage controlled oscillator may be the voltage controlled oscillator 116. The remainder of the synthesiser is the arrangement as shown in embodiments of Figures 1 to 8, which controls the frequency provided by the voltage controlled oscillator 116. The mixer 319 mixes the output of the voltage controlled oscillator 116 with the output of the second band pass filter 317 to provide a down converter signal. The down converter signal may be of the intermediate frequency or the base band frequency, depending on the construction of the receive part. The output of the mixer 319 is connected to the input of a third band pass filter 321 which acts as the intermediate frequency filter, providing narrow band filtering of the signal. The output of the band pass filter 321 is input to a second amplifier 323 which amplifies the signal. The amplified output of the second amplifier 323 is converted to a digital signal by an analogue digital converter 325.

It should be appreciated that the base transceiver stations will have a transmit part, similar to that shown in Figure 10. In particular, there will be up conversion of signals from the base band frequency either directly to the radio frequency or to the intermediate frequency. For either or both of those up conversions, the arrangements shown in Figures 1 to 8 in accordance with the present invention may be used to generate the mixing frequency which is input to the respective mixer.

In the GSM standard, frequency hopping is sometimes used. This means that the frequency of the channel which is used will change with time. The arrangements shown in Figures 4 to 8 when applied to the PLL structure of Figure 1 may be used to control the voltage controlled oscillator 116 such that the required reference frequency is provided for the channel which is used. In alternative embodiments of the present invention, the frequency of a channel may remain unchanged. Accordingly, the frequency provided by a given voltage controlled oscillator will be unchanged.

Embodiments of the present invention can be as flexible as required. For example, the programmable ROM 500 or the look- up table 804 may be arranged only to store the channels which the particular receive part and/or the base transceiver station are to provide. Instead, the ROM or the look-up table may store only the bit sequences for those channels which are to be transmitted.

It should be appreciated that if the frequency or frequencies which are to be provided changes, the required bit sequences can be simply downloaded to the ROM or look-up table. In some embodiments of the present invention, this can be done via the base station controller or even a mobile terminal.

Although in the above an algorithm for generating the bit sequences is stated and may be provided in association with a synthesiser, in the preferred embodiments of the present invention the ROM or other suitable memory has an entire bit sequence stored therein before any of the bit sequence is output to the divider.

The preferred embodiments use a stream of bits, output one at a time. In more complex arrangements, the output is not binary. In other embodiments of the invention, more than one bit may be output at a time.

The counter and memory of the various embodiments of the present invention may be replaced, in alternative embodiments of the invention, by a FIFO or by any other element able to provide a similar function. It should be appreciated that the synthesiser shown in embodiments of the present invention has a very broad application, and can be used to provide a control signal for a voltage controlled oscillator for any type of arrangement. Embodiments of the present invention are not limited to application in telecommunication systems, wireless or otherwise. Where embodiments of the present invention are used in telecommunication systems, it should be appreciated that their application is not limited to GSM systems . Embodiments of the present invention can be used with any other suitable standard including analogue standards, standards using time division multiple access, spread spectrum systems such as code division multiple access, frequency division multiple access and hybrids of any two or more of these systems .

The embodiments of the invention have been described as being used in the context of a base transceiver station. However, embodiments of the present invention can also be used in any other suitable receiver or transmitter such as a mobile station.

Claims

CLAIMS :

1. A method of determining a value for a divider of a frequency synthesiser, including the steps of: determining the necessary divider ratio to obtain the desired frequency from the reference frequency, and generating a fraction value of the divider ratio; generating n coefficients in dependence on the fraction value, the n coefficients being generated in an n^th order accumulator; determining an offset value associated with the fraction in dependence on the n coefficients.

2. The method of claim 1, wherein the step of determining the offset value includes applying the n coefficients in an algorithm.

3. The method of claim 1 or claim 2, wherein the step of determining the offset value is determined by:

Nacc k

∑ ∑ (-l)^r+1.c._r.C_k(n-r+l)

K=l r=l

Where C_k is the k^th coefficient, Nacc is the order of the accumulators used in the step of generating the coefficients, and c__r is a coefficient taken from Pascal's triangle.

4. The method of any one of claims 1 to 3, wherein the determining step further generates an integer value of the divider ratio, the method further including the step of combining the offset value and the integer value to thereby generate the divider value.

5. The method of claim 4, further including the step of loading the divider value into the divider.

6. The method of claim 5, wherein the step of loading the divider value into the divider includes adapting the value in dependence on the characteristics of the divider.

7. The method of any one of claims 1 to 6, wherein the step of determining the necessary divider ratio includes receiving the value of the reference frequency and the value of the desired frequency, wherein the fraction value is determined by dividing the desired frequency value by the reference frequency value.

8. The method of any one of claims 4 to 7, further including the steps of determining the divider values for all possible integer values and all possible fraction values, and storing said divider values in a memory.

9. The method of claim 8, wherein a storage location of the memory is selected responsive to a particular integer value and fraction value, the stored divider values in said location being output under control of a counter.

10. The method of claim 9, including the step of cycling through the counter to access the stored divider values in a selected location as long as that location is selected.

11. The method of claim 10, including the step of randomly selecting the start point in a selected location on each cycle.

12. The method of claim 8, including the step of selecting a storage location of the memory responsive to a particular set of generated n coefficients .

13. The method of claim 12, including the step of selecting the storage location of the memory additionally responsive to the integer value of the divider ratio.

14. The method of any preceding claim, wherein the frequency synthesiser performs the steps of: comparing a feedback frequency generated by the divider to the reference frequency; generating a control signal corresponding to a phase difference therebetween; applying the control signal to a voltage controlled oscillator, the output of which comprises the synthesiser output; and dividing the synthesiser output by the determined divider value to thereby generate the feedback frequency.

15. A frequency synthesiser comprising: input means for receiving a reference frequency; output means for providing a desired output frequency; means for dividing the desired output frequency by a plurality of divider values; and control means for generating the divider values, wherein the divider values are generated by: determining the necessary divider ratio to obtain the desired frequency from the reference frequency, and generating a fraction value of the divider ratio; generating n coefficients in dependence on the fraction value, the n coefficients being generated in an n^th order accumulator; and determining an offset value associated with the fraction in dependence on the n coefficients.

16. The frequency synthesiser of claim 15, wherein the divider values are generated by applying the relationship:

Nacc k

∑ ∑ (-l)^r+1.α_r.C_k(n-r+l)

K=l r=l

17. The frequency synthesiser of claim 15 or claim 16, wherein the divider values are generated by further generating an integer value of the divider ratio, wherein the offset value and the integer value are combined to generate the divider value.

18. The frequency synthesiser of claim 17, wherein the control means includes a memory, wherein the divider values for all possible integer and fraction values are stored in the memory .

19. The frequency synthesiser of claim 18, wherein a storage location of the memory is selected responsive to a particular integer value and fraction value, the control means including a counter for outputting the data stored at that location.

20. The frequency synthesiser of claim 19, wherein the counter cyclically counts such that the stored data is cyclically output whilst the particular integer value and fraction value remain unchanged.

21. The frequency synthesiser of claim 20, wherein there is provided means for randomly selecting the start point of the selected data on each cycle.

22. The frequency synthesiser of any one of claims 18 to 21, wherein the control means includes an accumulator block for generating the plurality of coefficients.

23. The frequency synthesiser of claim 18, wherein a storage location of the memory is selected responsive to a particular set of coefficient values .

24. The frequency synthesiser of claim 19, wherein the storage location of the memory is selected further responsive to a particular integer value.

25. The frequency synthesiser of claim 23 or claim 24, wherein the memory is a look-up table.

26^'. The frequency synthesiser of any one of claims 23 to 25, wherein the control means further includes an accumulator block for generating the coefficients .