WO2001097426A2

WO2001097426A2 - Apparatus and method for demultiplexing a time multiplexed signal

Info

Publication number: WO2001097426A2
Application number: PCT/US2001/040968
Authority: WO
Inventors: Michael J. Lagasse; Katherine L. Hall
Original assignee: Axe, Inc.
Priority date: 2000-06-15
Filing date: 2001-06-14
Publication date: 2001-12-20
Also published as: WO2001097426A3; EP1295423A2; AU2001267089A1

Abstract

An apparatus and method for demultiplexing a time-multiplexed signal are described. The time-multiplexed signal is a combination of component signals, each of which is modulated at a unique modulation frequency. The demultiplexer of the system includes an input interface over which the signal is received. One or more modulators receive the multiplexed signal and demultiplex the signal in stages. A plurality of receivers are used to detect clock and data from the component signals. Each of the receivers is tuned to a respective one of the modulation frequencies of the component signals. One or more of the receivers provides one or more feedback signals to a bias input and/or an RF input of one or more of the modulators. The feedback signals are used to adjust the modulators such that the power at the receiver at the associated modulation signal is maximized, thus causing the modulators to route each of the demultiplexed component signals to the appropriate receiver.

Description

APPARATUS AND METHOD FOR DEMULTIPLEXING A TIME MULTIPLEXED SIGNAL

Background of the Invention In many systems such as optical communication systems, it is desirable to transmit and receive streams of data at very high rates. For example, it may be required to forward data at 40 Gigabits per second (40Gb/s) or even faster. In some settings, such as receiving data streams, electro-optical hardware capable of directly processing data at such high rates is not available. Therefore, various techniques have been developed to accomplish transfer of data at the desired rate while allowing the actual hardware to function within its limitations.

For example, time-division multiplexing (TDM) has been used to combine multiple data streams at relatively slow data rates into a combined stream at a faster overall composite rate. In TDM processing, at the transmitting side, individual bits (or packets of bits) of the component data stream signals are interleaved in time, such as by alternating bit time windows. At the receiving side, by applying controlled timing to the composite signal, the individual component signals can be recovered. To illustrate, two individual lOGb/s signals can be combined into a single 20Gb/s signal by interleaving the bits of the two signals. The receiver can extract alternating bits from the received composite signal to recover the two component signals.

As the demand for faster data rates increases, techniques for multiplexing and demultiplexing data streams must improve in speed and efficiency.

Summary of the Invention The present invention is directed to an apparatus and method for improved demultiplexing of a time-multiplexed signal which permits very high data rates. The demultiplexing system of the invention includes an input interface over which a multiplexed signal, such as, for example, a TDM signal, can be received. The multiplexed signal is a combination of a plurality of component signals, each of which is modulated at a unique one of a plurality of modulation frequencies. In one embodiment, at least one modulator receives the multiplexed signal from the input interface and at least partially demultiplexes the signal into a pair of at least partially demultiplexed signals. The at least partially demultiplexed signals are routed toward a plurality of receivers. At least one receiver is adapted to detect signals at an associated respective one of said modulation frequencies. Each receiver provides a feedback signal indicative of an intensity of a received signal at its associated modulation frequency. The feedback signal is used to adjust a parameter of the modulator such that the component signal modulated at the associated modulation frequency can be recovered from the signal received by the receiver. The modulation signal applied to each component signal is a very low frequency signal relative to the data rate of the component signal. In one particular embodiment, the modulation frequency of one of the component signals is on the order of 10^"7 times the data rate of the component signal. For example, the data rate of each component signal can be 10 Gbits/sec. The modulation frequency can be in the kilohertz range. For example, in one particular exemplary embodiment described herein, the modulation frequencies for each of four lOGbits/sec component signals are 1.0 kHz, 1J kHz, 1.2 kHz and 1.3 kHz. In one embodiment, the modulation depth is below 100 percent. In one particular embodiment, the modulation depth is below 10 percent and can be, for example 1 percent or 2 percent. h one embodiment, the modulator is an electro-optical modulator and, in one particular embodiment, is a Y-fed balanced bridge intensity modulator. The modulator includes a bias input which adjusts the modulator output based on the applied bias voltage. The feedback signal from the receiver can be used to adjust the bias port of the modulator and/or the RF phase at an RF input port of the modulator. These adjustments are made such that signals having the modulation associated with the receiver are routed out of a first output of the modulator toward the receiver, and other signals are routed out of a second modulator output toward a different receiver. The demultiplexer of the invention can include multiple modulators configured to demultiplex the multiplexed signal in multiple stages. In one embodiment, the signal is demultiplexed in two stages. A first stage includes a single modulator which receives the multiplexed signal and at least partially demultiplexes the signal into a pair of partially demultiplexed signals to partially demultiplex the signal. For example, where the multiplexed signal is a 40Gb/s signal formed by multiplexing four 10 Gb/s signals, the first stage modulator can demultiplex the multiplexed signal into two 20 Gb/s signals. The partially demultiplexed signals are routed from the outputs of the first-stage modulator to a respective pair of second- stage modulators. Each of the second-stage modulators further demultiplexes its input signal into another pair of further demultiplexed signals. In the example above, each second-stage modulator demultiplexes its 20Gb/s input signal into a pair of 10 Gb/s demultiplexed signals. These demultiplexed signals generated by the second- stage modulators are forwarded to the receivers associated with their respective modulation frequencies.

Hence, in the system of the invention, the multiplexed signal is formed by applying a different modulation at a unique modulation frequency to each of a group of component signals and then combining the modulated component signals. The modulation applied to each component signal serves to uniquely identify the component signal. The demultiplexer includes multiple receivers, each of which is tuned to one of the modulation frequencies used to create the multiplexed signal. Feedback from one or more of the tuned receivers is used to set up the modulators to route the component signals to the appropriate receivers as they are recovered from the multiplexed signal by the modulators. hi one aspect of the invention, the system is set up or turned on in a very efficient fashion. First, a first turn-on or set-up signal is activated at one of the modulation frequencies. The signal is applied to the first-stage modulator which splits the signal and routes the split signals to the second-stage modulators which split the signals again. The second-stage modulators route the further split signals toward the receivers. The receiver that is tuned to the selected modulation frequency of the first turn-on signal provides a feedback signal which is used to adjust the first- stage and second-stage modulators associated with the receiver. The bias input signals and/or the RF phase at the RF inputs of the modulators are adjusted to maximize the intensity of the signal received by the receiver tuned to the turn-on signal modulation frequency. When this condition is achieved, the receiver is

"locked" to incoming signals at the associated modulation frequency. Both the associated first-stage and second-stage modulators route all of the energy at the modulation frequency out of a first output and route other signals out of the second output. This process is then repeated for another of the receivers. A second turn-on signal at another of the modulation frequencies is applied to the first-stage modulator. The signal at the second modulation frequency is routed out of the second output of the first-stage modulator toward the second-stage modulator, which splits the signal and routes the split signals toward the final two receivers. The one of the receivers that is tuned to the turn-on signal modulation frequency provides the feedback signal used to adjust the bias input and the RF phase input of the associated second-stage modulator. The bias input and RF phase of the RF input are adjusted by the feedback signal to maximize the intensity of the signal at the second modulation frequency at the associated second receiver. As a result, the second receiver is "locked" to the second modulation frequency. After the first two receivers are thus locked to the first two modulation frequencies, the remaining signals at the remaining modulation frequencies are routed automatically through the first and second modulator stages to their appropriate receivers.

Brief Description of the Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 contains a schematic block diagram of one embodiment of a demultiplexing system in accordance with the present invention.

FIG. 2 contains a schematic diagram illustrating one type of signal time multiplexing to which the present invention is applicable.

FIG. 3 contains a schematic flowchart which illustrates the logical flow of a turn-on procedure for the system of the invention in accordance with the invention.

Detailed Description of Preferred Embodiments of the Invention FIG. 1 is a schematic block diagram of one embodiment of a demultiplexing system 10 in accordance with the present invention. A time-multiplexed signal is received at an input interface 8. FIG. 2 is a schematic diagram which generally illustrates one form of time multiplexing which can be used to generate the time- multiplexed signal to which the invention is applicable. Referring to FIG. 2, a technique for multiplexing N channels or signals is illustrated. Multiplexing of the N bit streams is achieved by a delay technique. The laser 2 generates a periodic pulse train at the repetition rate equal to the single-channel bit rate B. In this illustration, the pulse train output is split into N branches, after amplification if necessary, and a modulator 5(1), 5(2), ..., 5(N) in each branch blocks the pulse for every 0 bit, creating N independent bit streams at the bit rate B.

Each of the individual signals in each branch is modulated at a different identifying modulation frequency by modulators 5(1), 5(2), ..., 5(N). Multiplexing of N bit streams is achieved by individually set delays 4(1), 4(2), ..., 4(N) in each branch. The modulated bit stream in the nth branch is delayed by an amount (n- 1)/(NB), where n=l,...,N. The outputs of all the branches are combined to form a composite signal. In one embodiment, the multiplexed signal is a combination of four (N=4) 10 Gb/s (B=10 Gb/s) signals. Hence, the composite signal bit rate is 40 Gb/s. Specifically, the time-multiplexed signal to which the present invention is applicable can be generated by a transmission and multiplexing system such as the one described in copending U. S. Patent Application serial number 09/566,303, filed on May 8, 2000, entitled, "Bit Interleaved Optical Multiplexer," of the same assignee as the assignee of the present application. The contents of that application are incorporated herein in their entirety by reference.

Referring again to FIG. 1, the multiplexed signal is routed from the input 8 to the input of a first electro-optical modulator 12. First and second outputs of the first modulator 12 are routed on lines 13 and 15, respectively, as shown to the inputs of a second modulator 14 and a third modulator 16, respectively. In one embodiment, each of the modulators is a Y-fed balanced bridge modulator, or the like, such as those manufactured and sold by JDS Uniphase Corporation. The first modulator 12 receives the multiplexed signal from the input 8 and partially demultipexes the signal into two partially demultiplexed signals. The first output signal from the modulator 12 is provided on line 13 as the input to a second modulator 14. The second output of the modulator 12 is provided on line 15 to the input of the third modulator 16. The modulator 14 further dmultipexes its received signal into two demultiplexed signals and routes its first and second demultiplexed outputs on lines 54 and 56 to receivers 18 and 20, respectively. Similarly, the modulator 16 further demultiplexes its input signal into two demultiplexed signals and routes its first and second demultiplexed output signals on lines 58 and 60 to the receivers 22 and 24, respectively. As described above, each component signal in the multiplexed signal is characterized by a unique modulation frequency which serves to identify and distinguish the component signal from the other component signals. This unique modulation is used by the system 10 to recover the component signals. To that end, each receiver 18, 20, 22 and 24 is tuned to a particular modulation frequency. To aid in description of the invention, the modulations will be referred to herein as A, B, C and D. Hence, receiver 18 is tuned to detect signals with modulation A, receiver 20 is tuned to detect signals with modulation B, receiver 22 is tuned to detect signals with modulation C, and receiver 24 is tuned to detect signals with modulation D.

In one embodiment, the modulation signal applied to each component signal is a very low frequency signal relative to the data rate of the component signal. In one particular embodiment, the modulation frequency of one of the component signals is on the order of 10^"7 times the data rate of the component signal. For example, the data rate of each component signal can be 10 Gbits/sec. The modulation frequency can be in the kilohertz range, hi one illustrative embodiment, the modulation frequencies of the component signals can be as follows: A=1.0kHz;

B=l .2kHz; C=l .3kHz; D=l .1kHz. It will be understood that these frequencies are chosen for illustration purposes only. Other frequencies may be chosen. Also, the modulation depth of the signal can be below 100 percent, hi one embodiment, the modulation depth is below 10 percent and can be, for example 1 percent or 2 percent. Each of the receivers 18, 20, 22 and 24 includes detection circuitry used to detect its respective associated subcarrier modulation to recover the data at its incoming component data rate, e.g., lOGb/s. The data is recovered from the signal, and a clock signal at the data rate is generated from the incoming data. As shown in FIG. 1, in the described embodiment, receiver 18 generates a clock signal from the recovered data stream, and feeds back the clock signal to a pair of phase shifters 30 and 32 on lines 42 and 44, respectively. A processor 26 uses a signal indicative of the intensity of the modulation A signal recieved at the receiver 18 to generate a phase control signal used to control the amount of phase shift in phase shifter 30 and provides the control signal to phase shifter 30 on line 48. The processor 26 also generates another phase control signal used to control the amount of phase shift in phase shifter 32 and provides the control signal to phase shifter 32 on line 52. These phase shifted signals are applied to the RF inputs of the modulators 12 and 14 to precisely control the delay of the signals through the modulators such that the component signals can be accurately recovered from the multiplexed composite signal. It should be noted that the frequency of the signal fed back to modulator 12. is doubled by frequency doubler 34 because the modulator 12 operates to generate the partially demultiplexed signals on lines 13 and 15 at twice the frequency at which the modulator 14 operates.

Receiver 24 also generates a feedback clock signal and provides the feedback signal to phase shifter 36. The processor 28 generates another phase control signal and applies the control signal via line 50 to phase shifter 36 to control the phase shift introduced into the feedback clock signal. Once again, this is done to control the timing of the demultiplexing process of the invention.

Receiver 18 also provides a feedback signal on line 38 which is indicative of the intensity of received signal having modulation A. The feedback signal is routed to the processor 26 which uses the feedback signal to generate the control signals used to adjust the bias input and the RF phase at the RF input of the modulator 14. The bias input control signal is routed to the bias input of the modulator 14 on line 49. The RF phase control signal is routed to the phase shifter 30 on line 48. The lOGb/sec clock signal recovered by the receiver 18 is routed on line 42 to the phase shifter 30. The control signal from the processor 26 on line 48 controls the phase shift of the clock signal introduced by the phase shifter 30. The phase shifted clock signal is applied to the RF input of the modulator 14. The bias input and RF inputs are adjusted to maximize the intensity of the modulation A signal at the receiver 18. As a result, all signal with modulation A received by the modulator 14 is routed via the first output of the modulator 14 on line 54 to receiver 18. The remaining signal is routed via the second Output of modulator 14 on line 56 to receiver 20. As will be described below, when the system 10 is operating, this remaining radiation will only be signal with modulation B. The processor 26 also generates control signals used to control the bias input and the RF input to the first modulator 12. The second bias control signal is applied to the bias input of modulator 12 via line 55, and the second phase control signal is applied to the phase shifter 32 via line 52. The phase shifter 32 adjusts the phase of the 10 Gb/sec clock signal recovered by the receiver 18 and applies the phase shifted clock signal through the frequency doubler 34 to the RF input of the modulator 12.

Again, the bias input and RF input to modulator 12 are adjusted to maximize the modulation A signal intensity at receiver 18. Because of the selection of modulation frequencies and the timing and positioning of the relevant component signals within the composite signal, modulator 12 routes signals with modulation A and B via its first output on line 13 to modulator 14. The remaining signals, i.e., signals with modulations C and D, are routed via the second output of modulator 12 on line 15 to the third modulator 16. Modulator 16 further demultiplexes its input signal into two demultiplexed output signals. Its first output provides signals with modulation D to receiver 24 on line 60. The second output provides signals with modulation C to receiver 22 on line 58.

Receiver 24 generates a feedback signal related to the intensity of received signal at modulation D and routes the feedback signal to a second processor 28 on line 40. In similar fashion to processor 26, the processor 28 generates a bias control signal on line 51 used to adjust the bias input of modulator 16 and a phase control signal on line 50 used to adjust the RF input of modulator 16. The phase control signal is applied to the phase shifter 36 to adjust the phase of the 10 Gb/sec clock signal recovered by receiver 24. The phase-shifted clock signal is applied to the RF input of modulator 16. The bias control signal and phase control signals are adjusted to maximize the intensity of the modulation D signal at receiver 24. When the intensity of modulation D signal at receiver 24 is maximized, all of the modulation D signal received by modulator 16 is routed via its first output on line 60 to receiver 24. The remaining signal, i.e., signal at modulation C, is routed via the second output on line 58 to receiver 22.

In summary, the first modulator 12 is set up via feedback control to partially demultiplex the incoming multiplexed signal into two partially demultiplexed signals. The first signal at the first output of the modulator 12 includes multiplexed signals of modulations A and B on line 13. The second signal at the second output of modulator 12 includes multiplexed signals of modulations C and D on line 15. The modulator 14 further demultiplexes the partially multiplexed signal on line 13 into two demultiplexed signals having modulations A and B. Likewise, modulator 16 further demultiplexes the signal on line 15 into two demultiplexed signals having modulations C and D. The completely demultiplexed signals are applied to their respective receivers by modulators 14 and 16.

In the illustrative example used above, the signal received at the input of the modulator 12 is a 40Gb/s signal, being the time-multiplexed composite of the four individual lOGb/s signals. The modulator 12 demultiplexes this composite signal into two 20Gb/s signals, each of which is applied to one of modulators 14 and 16. Each of the modulators 14 and 16 further demultiplexes its incoming 20Gb/s signal into a pair of lOGb/s signals to complete the demultiplexing of the multiplexed input signal. Thus, the demultiplexing of the input signal occurs in multiple stages, in this case, two stages.

It should be noted that in the foregoing description, processors 26 and 28 are described as being separate processors. However, it will be understood that the two processors 26 and 28 can actually be implemented in a single processor device. The demultiplexing system 10 of FIG. 1 can be turned on and locked up to the incoming multiplexed signal in an efficient fashion. FIG. 3 contains a schematic flowchart which illustrates the logical flow of a turn-on procedure for the system of the invention in accordance with the invention. Referring to FIG. 3, in a first step 200, a signal having only modulation A is turned on and applied to the input 8 of the system 10. Next, in step 202, the control signals generated by the processor 26 and applied to lines 48 and 49 are adjusted to adjust the RF and bias inputs, respectively, to the modulator 14. These signals are adjusted to maximize the power of the modulation A signal received at the receiver 18. When this power is maximized, modulator 14 is locked in the correct state. It will route all modulation A power to receiver 18 and other power to receiver 20.

Next, in step 204, the control signals generated by the processor 26 and applied to lines 52 and 55 are adjusted to adjust the RF and bias inputs, respectively, to the modulator 12. These signals are adjusted to further maximize the power of the modulation A signal received at the receiver 18. When this power is maximized, modulator 12 is locked in the correct state. It will route signals with power at modulation A and B on line 13 to modulator 14 and other signals to modulator 16 on line 15.

Next, in step 206, a signal with modulation D power is turned on and applied to the system input 8. Because modulator 12 is already locked in the correct state, this modulation D signal will automatically be routed to the modulator 16 on line 15. Next, in step 208, the control signals generated by the processor 28 and applied to lines 50 and 51 are adjusted to adjust the RF and bias inputs, respectively, to the modulator 16. These signals are adjusted to maximize the power of the modulation D signal received at receiver 24. When this power is maximized, modulator 16 is locked in the correct state. It will route signals with power at modulation D on line 60 and all other signals, e.g., signals with power at modulation C, to receiver 22.

Finally, in step 210, signals with modulations B and C are turned on and applied to system input 8. Because all of the modulators 12, 14 and 16 are set up and locked in their correct states, signals with these remaining two modulations are routed automatically to their respective appropriate receivers. That is, signals with modulation B are routed to receiver 20, and signals with modulation C are routed to receiver 22.

While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

What is claimed is:

Claims

1. A demultiplexer for demultiplexing a multiplexed signal, said multiplexed signal being a combination of a plurality of component signals, each component signal being characterized by a modulating signal having a respective modulation frequency, said demultiplexer comprising: an input interface over which the multiplexed signal can be received; at least one modulator for receiving the multiplexed signal from the input interface and generating therefrom at least one demultiplexed signal; a plurality of receivers, each of said receivers being adapted to detect signals at an associated respective one of said modulation frequencies and provide a feedback signal indicative of an intensity of a received signal at said associated modulation frequency, the feedback signal being used to adjust a parameter of the modulator such that the component signal characterized by the associated modulation frequency is recovered from the signal received by the receiver.

2. The demultiplexer of claim 1 wherein the at least one modulator generates a pair of demultiplexed signals from the multiplexed signal.

3. The demultiplexer of claim 1 wherein the parameter adjusted using the feedback signal is a modulator bias input parameter.

4. The demultiplexer of claim 1 wherein the parameter adjusted using the feedback signal is a modulator RF input parameter.

5. The demultiplexer of claim 1 wherein the modulator is an electro-optical modulator.

6. The demultiplexer of claim 1 wherein the modulator is a Y-fed balanced bridge intensity modulator.

7. The demultiplexer of claim 1 further comprising a plurality o modulators, said plurality of modulators being configured to demultiplex the multiplexed signal in stages.

8. The demultiplexer of claim 7 wherein: a first modulator forms a first stage in which the multiplexed signal is at least partially demultiplexed into a pair of partially demultiplexed signals; and the partially demultiplexed signals are routed to a second stage in which the partially demultiplexed signals are further demultiplexed to recover the component signals.

9. The demultiplexer of claim 8 wherein the second stage comprises a plurality of modulators, each modulator receiving one of the partially demultiplexed signals and further demultiplexing the received one of the partially demultiplexed signals to obtain a pair of the component signals.

10. The demultiplexer of claim 1 wherein the modulating signal has a modulation depth below about 10 percent.

11. The demultiplexer of claim 1 wherein the modulation frequency of each component signal is much lower than a data rate of the component signal.

12. A method of demultiplexing a multiplexed signal, said multiplexed signal being a combination of a plurality of component signals, each component signal being characterized by a modulating signal having a respective modulation frequency, said method comprising: receiving the multiplexed signal; providing the multiplexed signal to at least one modulator to generate from the multiplexed signal at least one demultiplexed signal; providing a plurality of receivers, each of said receivers being adapted to detect signals at an associated respective one of said modulation frequencies within one of the demultiplexed signals and to provide a feedback signal indicative of an intensity of a received signal at said associated modulation frequency, the feedback signal being used to adjust a parameter of the modulator such that the component signal characterized by the associated modulation frequency is recovered from the signal received by the receiver..

13. The method of claim 12 wherein the at least one modulator generates a pair of demultiplexed signals from the multiplexed signal.

14. The method of claim 12 wherein the parameter adjusted using the feedback signal is a modulator bias input parameter.

15. The method of claim 12 wherein the parameter adjusted using the feedback signal is a modulator RF input parameter.

16. The method of claim 12 wherein the modulator is an electro-optical modulator.

17. The method of claim 12 wherein the modulator is a Y-fed balanced bridge intensity modulator.

18. The method of claim 12 further comprising providing a plurality of modulators, said plurality of modulators being configured to demultiplex the multiplexed signal in stages.

19. The method of claim 18 further comprising: using a first modulator to form a first stage in which the multiplexed signal is at least partially demultiplexed into a pair of partially demultiplexed signals; and routing the partially demultiplexed signals to a second stage in which the partially demultiplexed signals are further demultiplexed to recover the component signals.

20. The method of claim 19 wherein the second stage comprises a plurality of modulators, each modulator receiving one of the partially demultiplexed signals and demultiplexing the received one of the partially demultiplexed signals to obtain a pair of the component signals.

21. The method of claim 12 wherein the modulating signal has a modulation depth below about 10 percent.

22. The method of claim 12 wherein the modulation frequency of each component signal is much lower than a data rate of the component signal.

23. A demultiplexer for demultiplexing a multiplexed signal, said multiplexed signal being a combination of a plurality of component signals, each component signal being associated with a respective modulating signal having a respective modulation frequency, said demultiplexer comprising: an input interface over which the multiplexed signal can be received; a plurality of receivers, each of said receivers being configured to detect signals at an associated respective one of said modulation frequencies such that the component signals can be recovered from the multiplexed signal.

24. The demultiplexer of claim 22 further comprising at least one modulator for receiving the multiplexed signal from the input interface, at least partially demultiplexing the multiplexed signal into at least one partially demultiplexed signal and routing the partially demultiplexed signal toward the receivers.

25. The demultiplexer of claim 24 wherein the at least one modulator generates a pair of demultiplexed signals from the multiplexed signal.

26. The demultiplexer of claim 23 further comprising a plurality of modulators configured to demultiplex the multiplexed signal in stages, the first stage comprising a first modulator which at least partially demultiplexes the multiplexed signal into the partially demultiplexed signals and routes the partially demultiplexed signals to a respective pair of modulators, each of said modulators further demultiplexing its respective received partially demultiplexed signal into a pair of demultiplexed signals and routing each demultiplexed signal to a respective associated receiver.

27. The demultiplexer of claim 26 wherein each receiver generates a feedback signal related to intensity of a received signal at its associated modulation frequency, said feedback signal being used to adjust a parameter of at least one of the modulators such that the associated component signal can be recovered by the receiver.

28. The demultiplexer of claim 27 wherein the parameter adjusted using the feedback signal is a bias input parameter of the at least one modulator.

29. The demultiplexer of claim 27 wherein the parameter adjusted using the feedback signal is an RF input parameter of the at least one modulator.

30. A method of demultiplexing a multiplexed signal, said multiplexed signal being a combination of a plurality of component signals, each component signal being associated with a respective modulating signal having a respective modulation frequency, said method comprising: receiving the multiplexed signal over an input interface; providing a plurality of receivers, each of said receivers being configured to detect signals at an associated respective one of said modulation frequencies such that the component signals can be recovered from the multiplexed signal.

31. The method of claim 30 further comprising providing at least one modulator for receiving the multiplexed signal, said modulator at least partially demultiplexing the multiplexed signal into at least one partially demultiplexed signal and routing the partially demultiplexed signal toward the receivers.

32. The method of claim 31 wherem the at least one modulator generates a pair of demultiplexed signals from the multiplexed signal.

33. The method of claim 30 further comprising providing a plurality of modulators configured to demultiplex the multiplexed signal in stages.

34. The method of claim 33 further comprising configuring the plurality of modulators such that a first stage comprises a first modulator, said first modulator at least partially demultiplexing the multiplexed signal into the pair of partially demultiplexed signals and routing the partially demultiplexed signals to a respective pair of modulators in a second stage, each of said modulators of the second stage further demultiplexing its received partially demultiplexed signal into a pair of demultiplexed signals and routing each demultiplexed signal to a respective associated receiver.

35. The method of claim 33 wherein each receiver generates a feedback signal related to intensity of a received signal at its associated modulation frequency, said feedback signal being used to adjust a parameter of at least one of the modulators such that the associated component signal can be recovered by the receiver.

36. The method of claim 35 wherein the parameter adjusted using the feedback signal is a bias input parameter of the at least one modulator.

37. The method of claim 35 wherein the parameter adjusted using the feedback signal is an RF input parameter of the at least one modulator.

38. The method of claim 35 further comprising : applying a first turn-on signal to the input interface, said first turn- on signal being characterized by only one of the modulation frequencies associated with the plurality of receivers; routing the first turn-on signal through the modulators toward the receivers; and using the feedback signal generated by the receiver associated with the modulation frequency of the first turn-on signal to adjust the parameter of at least one of the modulators such that signals having the associated modulation frequency are routed through the modulators to the associated receiver.

39. The method of claim 38 further comprising: applying a second turn-on signal to the input interface, said second turn-on signal being characterized by the modulation frequency of the first turn-on signal and a second modulation frequency associated with a second receiver of the plurality of receivers; routing the second turn-on signal through the modulators toward the receivers; and using the feedback signal generated by the second receiver to adjust the parameter of at least one of the modulators such that signals having the modulation frequency associated with the second receiver are routed through the modulators to the second receiver.