WO2001080010A2

WO2001080010A2 - Method and system for upgrading fault-tolerant systems

Info

Publication number: WO2001080010A2
Application number: PCT/US2001/012137
Authority: WO
Inventors: Jeffrey S. Somers; Mark Tetreault; Timothy M. Wegener
Original assignee: Stratus Technologies International, S.A.R.L.
Priority date: 2000-04-13
Filing date: 2001-04-13
Publication date: 2001-10-25
Also published as: AU2001293360A1; WO2001080010A3

Abstract

The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on-line CPU provide certain register and memory state information to general purpose registers (408) on an I/O board. The I/O subsystem then provides the register contents to general purpose registers on the off-line CPU board, (408) and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU (410). At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board (412). When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line. The I/O subsystem then holds the off-line CPU in the known state by stalling the return of an acknowledgement of the write operation (416). When the on-line CPU later performs the same write operation, the on-line and the off-line CPUs are then in essentially the same state. The I/O processor may then reset the CPUs (418) to ensure that the off-line CPU goes on line and starts a next operating cycle in lock-step with the reset on-line CPU. The system also dynamically selects a CPU output stream comparison method based on the number of CPUs on line at a given time.

Description

METHOD AND SYSTEM FOR UPGRADING FAULT- TOLERANT SYSTEMS

Field of the Invention

The invention relates in general to fault-tolerant computer systems and, more particularly, to mechanisms for upgrading the systems to include additional central processing units ("CPUs") while the system is operative.

Background Information

The fault-tolerant systems of interest operate redundant CPUs in lock-step, that is, in cycle-to-cycle synchronism. Accordingly, before an off-line CPU is brought on-line, to upgrade the system from single-mode redundancy to double-mode redundancy, or double to triple-mode redundancy and so forth, the off-line CPU must first be synchronized to the state of an on-line CPU. Similarly, an off-line CPU must be synchronized to the on-line CPU when, for example, a faulty CPU is replaced.

In prior known lock-step systems, the on-line CPU communicates directly with the offline CPU in accordance with a special synchronization protocol. The CPU boards in the prior system include dedicated synchronization hardware that allows the CPUs to communicate using the synchronization protocol. Accordingly, the CPU boards are both time-consuming and expensive to design and manufacture.

Using the synchronization protocol, the on-line CPU directs the off-line CPU to set various components, such as certain registers and memory locations, to states that correspond to the states of the associated registers and memory locations of the on-line CPU. The on-line CPU thus controls a series of back and forth communications between the two CPUs, to provide the state information to the off-line CPU and to instruct the offline CPU to use the information to set the registers and memory locations to the appropriate states. Accordingly, the other processing operations performed by the on-line CPU may be disrupted during the synchronization process. SUMMARY OF THE INVENTION

The inventive system includes an I/O subsystem that controls the synchronization of an offline CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on- line CPU provide certain register and memory state information to general purpose registers on an I/O board. The I/O subsystem then copies the register contents to general purpose registers on the off-line CPU board, and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU.

At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board. When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line. The I/O subsystem then holds the off-line CPU in the known state by stalling the return of an acknowledgement of the write operation. When the on-line CPU later performs the same write operation, the on-line and the off-line CPUs are then in essentially the same state, and the I/O processor resets the CPUs to ensure that the off-line CPU goes on line and starts a next operating cycle in lock-step with the on-line CPU.

The I/O subsystem includes comparison logic that is updated when the off-line CPU changes its status to on-line as part of the reset operation. The comparison logic then compares the output streams from the previously on-line CPUs and the newly added on-line CPU. Accordingly, after the CPUs reset, the comparison logic compares two output streams if the system went from single to double modular redundancy, or three output streams if the system went from double to triple modular redundancy, and so forth. As discussed in more detail below, when the output streams do not agree the comparison logic also properly handles voting based on the number of on-line CPUs. The system thus dynamically changes its comparison method as CPUs are added to or removed from the system.

The communications between the on-line CPU and the I/O subsystem, and the I/O subsystem and the off-line CPU do not require a special synchronization communication protocol. Accordingly, the synchronization operation is less complex than the synchronization operations of the prior lock-step systems. Further, the components involved in the synchronization operation, namely, the general purpose registers and the DMA engine, are used for more than just the synchronization operation, and are thus not dedicated synchronization hardware. Also, the synchronization operation is controlled by the I/O subsystem, and thus, the processing operations of the on-line CPU are only minimally interrupted or disrupted. Finally, the comparison logic used to ensure valid output streams dynamically changes based on the number of on-line CPUs, and the system can thus be upgraded in the field.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention description below refers to the accompanying drawings, of which:

Fig. 1 is a functional block diagram of a system constructed in accordance with the invention;

Fig. 2 is a flow chart of the CPU synchronization operations of the system of Fig. 1; and

Fig. 3 is a more detailed functional block diagram of a portion of the system of Fig. 1.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE

EMBODIMENT

Referring to Fig. 1, a CPU 10, which is included on a CPU board 12 along with associated memory 120 and registers 122, communicates with various I/O devices, such as storage devices 24, a keyboard 26, and a monitor 28 through an I/O subsystem 14, which includes an I/O bus 16 and an I/O board 20 and associated component. To add fault tolerance, a second CPU 30 is included in the system. The two CPUs 10 and 30 must operate in lock-step, that is, in cycle-to-cycle synchronism. Accordingly, when the CPU 30 is brought on-line, the associated memory 130 and registers 132 on the CPU board 32 must be in essentially the same state as the corresponding memory 120 and registers 122 on the CPU board 12.

For convenience, the CPU 10, CPU board 12 and associated components are referred to hereinafter as the "on-line CPU," and the CPU 30, CPU board 32 and associated components are referred to hereinafter as the "off-line CPU." Also for convenience, we have depicted only those on-board components that are involved in the synchronization operation. We discuss below how the off-line CPU is brought on-line in synchronism with the on-line CPU.

Referring now also to Fig. 2, when the off-line CPU is plugged in, the off-line CPU performs conventional tests to ensure that it is operational. If the off-line CPU is operational, an I/O system manager 40 requests configuration information from the CPU, to determine if the CPU is equivalent to the on-line CPU (step 400). The off-line CPU provides to the I/O system manager information such as the size and type of memory, the number and types of processors, and so forth (step 402). If the I/O system manager determines that the off-line CPU is the equivalent of the on-line CPU, the manager turns on the off-line CPU (step 404). The I/O system manager may be, for example, a kernel in the operating system, such that the operating system ultimately controls the synchronization operation, or the manager may be part of the system's BIOS. Accordingly, the I/O system manager may be distributed throughout the system or resident on a given board.

Each CPU includes a set of general purpose registers ("GPR") 124, 134 that are used to hold status, error and other information. The I/O subsystem includes on the I/O board 20 associated, or "shadow," sets of GPRs 224, 234, one for each CPU that can be supported by the system. When a given CPU changes the information in its GPR, the change is also written into the corresponding GPR on the I/O board. Other system components can then look at the contents of the I/O subsystem GPRs, as needed, for updated status information, and so forth. The on-line CPU can write to the GPR 234 associated with the off-line CPU, and in this way can communicate with the off-line CPU without requiring a specialized communication protocol or specialized hardware.

One register in the GPR is a configuration register that includes information about the on- line-or off-line status of each of the CPUs. The on-line CPUs write their on-line status into the configuration register in each set of GPRs. When the off-line CPU is plugged in and turned on, the CPU automatically records its change of status from turned off to turned on in the configuration registers of the associated GPRs 134 and 234. The off-line CPU can not write to the GPRs associated with the on-line CPUs, and thus, the configuration registers in the remaining GPRs on the I/O board do not change. The I/O subsystem copies the contents of at least the configuration register to the GPR 134 of the off-line CPU. The off-line CPU reads the configuration information to determine if there are any CPUs then on-line. If so, the off-line CPU participates in a synchronization operation that is under the control of the I/O subsystem by looking to the GPR 134 for associated commands.

To start the synchronization operation, the I/O system manager 40 issues an interrupt to the on-line CPU (step 406). The on-line CPU checks the GPRs 224 and 234 on the I/O board, to determine the cause of the interrupt. The on-line CPU thus determines that an off-line CPU is being brought on-line, after checking the configuration register 234 that is associated with the off-line CPU. The on-line CPU then participates in the synchronization operation.

As part of the synchronization operation, the I/O system manager 40 requests that the online CPU write the states of various components, such as certain registers 122 and/or the contents of certain memory locations in memory 120, to specified locations in the GPR 234 that is associated with the off-line CPU (step 408). The on-line CPU then proceeds with its other processing operations in a usual manner.

Before copying the contents of the GPR 234 to the GPR 134, the I/O system manager or the on-line CPU, as appropriate, includes in the GPR 234 a command that tells the off-line CPU to set certain of its registers 132 and/or certain of its memory locations to the specified states. Once I/O system manager copies the contents of the GPR 234 to the GPR 134 on the off-line board 32, the off-line CPU consults the GPR 134 and, in accordance with the command contained therein, sets the appropriate registers 132 and/or memory locations in the memory 130 to the states specified in the GPR. The offline CPU acknowledges that it has executed the command by writing an acknowledgement to the GPR 234. As necessary, the I/O system manager 40 directs the on-line CPU to continue writing state information to the specified locations in the GPR 234, and so forth.

A DMA engine 240, which operates under the control of the I/O system manager 40, also supplies memory state information to the off-line CPU (step 410). The DMA engine essentially copies the contents of memory pages from the memory 120 of the online CPU to predetermined locations in a memory 130 of the off-line CPU. The system manager 40 controls the timing of the data move operation, so that the operation only minimally delays the processing operations of the on-line CPU.

The I/O subsystem manager may stall or mask incoming interrupts and allow the on-line CPU to respond to any queued interrupts before the start of the memory copy operation. This ensures that the copied memory information does not change while the memory copy operation is taking place. The I/O subsystem manager may, as necessary, monitor the operations of the online CPU after the memory copy, to keep track of changes to the contents of the memory. The I/O system manager then provides the changes to the off-line CPU during a later step in the synchronization operation.

Both the off-line CPU and the on-line CPU are each directed to write a synchronization token into the appropriate GPRs 224 and 234 (step 412). As discussed in more detail below, the synchronization tokens serve to remind the CPUs, after reset, that they have completed the synchronization operation.

The I/O system manager 40 next triggers a system management interrupt to all of the I/O ^' system processors. In response, all of the processors save their register states to memory. As necessary, the I/O system manager also directs that the memory change information be provided to the off-line CPU and stored in memory. Further, the I/O system manager directs the on-line CPU to initiate, as a final step, a CPU synchronization procedure (step 414). The on-line CPU instructs the off-line CPU to perform a "sync write" operation by writing into the GPR 234 a command that instructs the off-line CPU to write to a predetermined register 236 on the I/O board 20. The register 236 may, but need not, be part of the GPR 234. The on-line CPU then starts a timer (not shown) to establish when the on-line CPU will write to the same register 236.

The I/O system manager 40 copies the contents of the GPR 234 to the GPR 134 on the off-line CPU. The off-line CPU reads the GPR 134, updates memory, as appropriate, and writes to the register 236. When the off-line CPU writes to the register 236, the off-line CPU has completed setting its register and memory to the specified states and is ready to go on-line. In response to the write to the register 236, the I/O subsystem stalls the off-line CPU in its current, known state by delaying the sending of a write acknowledge (step 416). At an appropriate time after the start of the sync write operation, that is, when the timer times out, the on-line CPU also writes to the register 236. The two CPUs are then in essentially the same, known state. The I/O subsystem then resets both the on-line CPU and the stalled off-line CPU, to ensure that they both start the next operating cycle in lock-step (step 418).

When the two CPUs 10 and 30 come out of reset, they consult the GPRs on the I/O board 20, to determine the cause of the reset. The synchronization token, which was written into the register 234 before the reset, informs the CPUs that they have just completed a synchronization operation. The off-line CPU then sets its status to on-line, and writes the change of status to the configuration registers in the GPRs 224 and 234. Further, the memories are turned on and the saved register states are restored. At the start of a next clock cycle, the two CPUs 10 and 30 begin their processing operations in lock-step.

The interrupts that had been delayed earlier are provided to each of the CPUs, and normal

CPU operations continue. After reset, the system may also check that the contents of the memory 130 of the previously off-line CPU match the contents of the memory 120 of the on-line CPU, to ensure that the CPUs will continue operating in lockstep. If the memories 130 and 120 do not agree, the system takes the previously off-line CPU off-line again.

Referring also to Fig. 3, the I/O subsystem includes on the I/O boards 26 comparison logic 300 that determines if the output streams of address/data/control signals from all of the online CPUs agree. The comparison logic thus compares two output streams when there are two on-line CPUs, three output streams when there are three online CPUs, and so forth. The comparison logic dynamically selects the comparison method, based on the number of CPUs currently on-line.

When the off-line CPU changes its status to on-line and updates the GPR configuration information as discussed above, the change in status also updates the comparison logic. Based on the status information in the GPRs, the comparison logic in the exemplary system configures itself to perform a two-stream compare or a three-stream compare. The comparison logic may include, in the example, three AND gates 301, 302, 303 for the two stream compare and a fourth AND gate 304 that is used for the three stream compare. A selector 306 then selects one of the three AND gates 301-303 for the two-stream compare, all four AND gates for the three stream compare or no AND gates for a single stream pass-through, based on the states of the status bits in the configuration register of one or more GPRs. Of course, it is contemplated that any bit comparator gate or device may serve the function of the AND gates 300-04 in accord with the present invention. For example, XOR gates may be used in place of the AND gates.

If three CPUs, referred to as CPUs 0, 1 and 2 in the drawing, are currently on-line, the comparison logic compares the three output streams bit-by-bit for each operating cycle in AND gates 301-303, where the output streams are referred to in the drawing as the numbered lines entering these AND gates. If the AND gate 304 indicates that all three output streams do not agree, the comparison logic identifies the improperly functioning CPU by majority vote. The comparison logic thus identifies the CPU that sent the one stream that does not agree with the other two streams. The comparison logic then sends a signal on line 314 to the malfunctioning CPU, instructing the CPU to go offline. The selector 310 also sends one of the valid output streams to the system components, based on the signals provided by the AND gates 301-304.

When the malfunctioning CPU goes off-line, the CPU updates its configuration information appropriately. In the example, the comparison logic dynamically configures itself to compare the output streams from the remaining two on-line CPUs.

If only two CPUs are on-line, the system compares the two output streams in the appropriate AND gate 301, 302 or 303. If the two output streams agree, a selector 310 sends one of the streams to the system components. If the two streams do not agree, the selector 310 sends the two output streams internally to a voter delay buffer 312. In one embodiment, voter delay buffer 312 includes a first FIFO buffer and a second FIFO buffer (not shown). The output from the first and second CPUs is stored in the first and second FIFO buffers respectively. This action prevents the system components from receiving data which may have been corrupted by a malfunctioning CPU and saves data that would otherwise be lost or discarded while identifying the malfunctioning CPU.

As the data is received by the voter delay buffer 312, the system uses diagnostic procedures to identify which CPU is malfunctioning. If the first CPU is malfunctioning, it is isolated and system operation continues with the second CPU. Data stored in the second FIFO buffer is supplied over the system I/O bus, with subsequently processed data from the second CPU thereafter provided over the system I/O bus. Conversely, if the second CPU is malfunctioning, it is isolated and system operation continues with the first CPU. Data stored in the first FIFO buffer is supplied over the system I/O bus, with subsequently processed data from the first CPU thereafter provided over the system I/O bus.

If only one CPU is on-line, the comparison logic 300 no longer needs to act on the remaining output stream. Accordingly, the selector 306 informs the selector 310 which CPU is then on-line, and the selector 310 passes the corresponding output stream through to the appropriate system components.

As discussed above, the off-line CPU is synchronized to the on-line CPU without need of a special synchronization communication protocol or dedicated synchronization hardware on the CPU board. Further, the synchronization operation, which is controlled by the I/O system manager, causes minimal disruption of the other activities of the online CPU, and is thus not noticed by a system user. Also, the system dynamically configures its comparison logic based on the number of CPUs on-line at any given time. Accordingly, the system can be upgraded from single to double to triple modular redundancy and so forth and/or faulty CPUs can be removed and/or replaced, while the system is operative and without adversely affecting the operations of the system. The same operation may also be used to bring additional CPUs on-line and into lock-step operation with the on-line CPUs.

The foregoing description has been limited to a specific embodiment of this invention. It will be apparent, however, that variations and modifications may be made to the invention, such as allowing off-line CPUs to read from and write to the associated GPR on the I/O board, operating the two CPUs in lock-step from the same lαiown state without resetting the CPUs, providing various other arrangements of AND gates or other logic gates in the comparison logic to produce the appropriate control signals for the selectors, using a cross-bar or other type of multiple-input line switch in place of the selectors to provide signals to the system components, performing the comparison operations in software, or firmware, and so forth, with the attainment of some or all of its advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

What is claimed is:

Claims

1. A fault-tolerant computer system including: A. an on-line CPU; B. an off-line CPU; C. an I/O subsystem that communicates with the on-line and off-line CPUs; and D. an I/O system manager that controls a synchronization operation in which the offline CPU is synchronized to on-line CPU, the I/O system manager directing i. the on-line CPU to provide component state information to the I/O subsystem, ii. the I/O subsystem to provide the component state information to the offline CPU, and iii. the off-line CPU to set corresponding components to the specified states, the I/O system manager controlling the time at which the off-line CPU is brought on-line to operate in lock-step with the on-line CPU by directing each of the CPUs to a known operating state before bringing the off-line CPU on-line.

2. The computer system of claim 1 wherein the I/O subsystem includes registers in which the on-line CPU writes the component state information that is to be provided to the off-line CPU.

3. The computer system of claim 2 further includes a DMA engine that under the control of the I/O system manager copies memory states associated with the on-line CPU to the off-line CPU before the off-line CPU is brought on-line.

4. The computer system of claim 3 wherein the I/O system manager further iv. directs the on-line CPU to perform a sync write operation in which the online CPU includes in the registers a write command that directs the off-line CPU to write to a predetermined register when the off-line CPU is ready to go on-line, and v. stalls the off-line CPU in a known state associated with the sync write operation until the on-line CPU is in the same known state.

5. The computer system of claim 4 wherein the I/O system manager stalls the off-line CPU by delaying acknowledgment of the write until the on-line CPU also writes to the predetermined register.

6. The computer system of claim 3 wherein the I/O system manager resets the on-line and the off-line CPUs after completion of the sync write operation, to bring the off-line CPU on-line and in lock-step with the on-line CPU.

7. The computer system of claim 6 wherein a. the I/O system manager directs the off-line CPU to write a synchronization token to the registers, and b. the on-line and off-line CPUs determine that they are reset as part of a synchronization operation when they read the synchronization token in the* registers.

8. The computer system of claim 1 wherein the system further includes one or more additional on-line CPUs that operate in lock-step with the on-line CPU.

9. The computer system of claim 1 further including comparison logic for comparing output streams from two or more on-line CPUs, the comparison logic selecting at a given time the number of streams to compare based on the number of CPUs on line at the given time.

10. The computer system of claim 9, wherein the comparison logic further includes a voter delay buffer for holding output streams from two on-line CPUs, the voter delay buffer holding the streams until the system determines which of the two streams to send on.

11. A method for synchronizing an off-line CPU to an on-line CPU, the method including the steps of A. providing component state information from an on-line CPU to an I/O subsystem; B. providing the component state information from the I/O subsystem to an off-line CPU and directing the off-line CPU to set corresponding components to the same states; C. directing the off-line CPU to a known state; D. holding the off-line CPU in the known state until the on-line CPU is in the same known state; E. allowing the off-line CPU to go on-line and operate in lock-step with the on-line CPU in a next operating cycle.

12. The method of claim 11 wherein the step of providing component state information from the on-line CPU to the I/O subsystem includes writing the information to registers in the I/O subsystem.

13. The method of claim 11 further including in the step of providing component state information from the on-line CPU to the I/O subsystem the step of copying memory states associated with the on-line CPU to the off-line CPU.

14. The method of claim 11 wherein the step of directing the off-line CPU to a known state includes the step of directing the off-line CPU to write to a predetermined register when the off- line CPU is ready to go on-line.

15. The method of claim 14 wherein the step of holding the off-line CPU in the known state includes the step of stalling the off-line CPU by delaying an acknowledgement of the write to the predetermined register until the on-line CPU also writes to the predetermined register.

16. The method of claim 15 wherein the step of allowing the off-line CPU to go on-line includes the step of resetting the off-line CPU and the on-line CPU, to bring the off-line CPU on- line and in lock-step with the on-line CPU.

17. The method of claim 16 wherein the step of resetting the CPUs further includes c. directing the off-line CPU to write a synchronization token to the registers, and d. after reset, checking the registers to determine the reason for the reset, the CPUs determining that the reset is part of a synchronization operation when they find the synchronization token in the registers.

18. A fault tolerant computer system including: A. one or more CPUs; B. an I/O subsystem that communicates with the CPUs, the I/O subsystem including i. registers for holding CPU status information, ii. comparison logic for comparing output streams from any number of on- line CPUs, and iii. one or more selectors for selecting a comparison method based on the number of CPUs on-line at a given time

19. The system of claim 18 further including a. a voter delay buffer for holding the output streams from two on-line CPUs until the system can determine which of the two CPUs is malfunctioning, and b. the selectors select the voter delay buffer to hold the output streams when two CPUs are on-line and the output streams from the two on-line CPUs do not agree.

20. The system of claim 19 wherein c. the selectors select a majority vote comparison method if three or more CPUs are on-line, and d. the selectors select as malfunctioning the on-line CPU that provides the output stream that does not agree with the output streams from a majority of the on-line CPUs.

21. The system of claim 20 wherein e. the comparison logic includes a plurality of comparison gates; and f. the selectors select the gates to be used for a given comparison operation.

22. A method for selecting a valid output stream from one or more CPUs, the method including the steps of A. determining how many CPUs are on-line at a given time; B. selecting a comparison method based on the number of CPUs on-line; C. if three or more CPUs are on-line selecting one of the data streams that agrees with a majority of the other data streams; D. if two CPUs are on-line and the corresponding data streams do not agree, i. sending the data streams to a voter delay buffer, ii. holding the data streams in the buffer until one of the CPUs goes off-line, and iii. selecting the output stream that corresponds to the remaining on-line CPU.

23. The method of claim 22 wherein the step of comparing the output streams from three or more on-line CPUs includes selecting an appropriate number of comparison gates to identify which of the output streams does not agree with the majority of output streams.

24. The method of claim 23 wherein the step of selecting an output stream when three or more CPUs are on-line further includes notifying the CPU, which corresponds to the output stream that does not agree with the majority, that the CPU should go off-line.