WO2001035165A1 - Data path design for multiple electron beam lithography system - Google Patents
Data path design for multiple electron beam lithography system Download PDFInfo
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- WO2001035165A1 WO2001035165A1 PCT/US2000/041988 US0041988W WO0135165A1 WO 2001035165 A1 WO2001035165 A1 WO 2001035165A1 US 0041988 W US0041988 W US 0041988W WO 0135165 A1 WO0135165 A1 WO 0135165A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
- H01J37/3177—Multi-beam, e.g. fly's eye, comb probe
Definitions
- This invention relates to the field of lithography, and in particular to data path design for multiple beam lithography.
- the data path is the hardware required to process and deliver pattern data in a lithography system.
- Maskless lithography systems including electron, ion and laser beam systems, all require hardware to process and deliver the pattern data.
- Such data path designs are well known for systems with single beams.
- Systems with multiple beams require a different type of data path - one that functions to efficiently break-up the pattern data and simultaneously deliver it to each beam.
- the spacing of the beams and the relationship of this spacmg to the die dimensions becomes very important.
- US Pat. No. 4,390,789 a multiple column electron beam lithography system, with one electron beam per column, is described.
- the X and Y column spacmgs are mechanically ad j ustable to match the X and Y die dimensions, respectively.
- mechanical adjustment of columns is not practical for a high throughput manufacturing environment in which wafers with different die sizes may be being processed simultaneously withm the same fabrication facility.
- the data path in this case must be more complex in order to accommodate possible mismatches between the X and Y column spacmgs and the X and Y die dimensions, respectively.
- This invention includes a data process and distribution system for multiple beam lithography.
- Full advantage is taken in the data path design of the required pattern data structure, m particular, for semiconductor wafers, the high degree of parallel data use arising from the onentation of dies on the wafer parallel both to the orientation of the array of writing cells and to the wafer stage scan direction.
- decompressed pattern data is distributed and stored locally, either at each writing cell m a first embodiment or for each group of cells oriented along the scan-axis of the wafer stage in a second embodiment.
- the first embodiment is comp ⁇ sed of a pattern storage device, a controller, a multiplicity of decompression engines, a multiplicity of beamlet pattern memo ⁇ es and a multiplicity of blankers connected m said order.
- the second embodiment is comp ⁇ sed of a pattern hbrary storage device, a controller, a raster image processor, a multiplicity of row buffers and a cell array connected m said order.
- the raster image processor is comp ⁇ sed of a geometry processor connected to a raster ASICS, m turn connected to a SDRAM.
- the SDRAM has sufficient memory to store a complete die pattern.
- Each row buffer has sufficient memory to store one die stripe of data.
- the raster image processor and the row buffer have ECC and CRC hardware, so as to reduce errors.
- FIG 1 shows a schematic of the cell electron optical components and a block diagram of the cell control electronics.
- FIG. 2a shows a schematic of a die and depicts how it is w ⁇ tten using st ⁇ pes and subst ⁇ pes.
- FIG. 2b shows a magnified view of FIG. 2a focusing on two adjacent stripes and their decomposition into subst ⁇ pes.
- FIG. 2c shows a schematic of a single subst ⁇ pe that is 3.2 ⁇ m wide and 20.0704 mm long.
- FIG. 2d shows a schematic of the cells, each with 32 beams, writing on a wafer.
- FIG. 2e shows a magnified view of FIG. 2d, indicating the electronic scanning of the 32 beams of a single cell over the writing area, and the scanning of the stage underneath the cell.
- FIG. 2f shows a schematic of a single stripe and its decomposition into subst ⁇ pes.
- FIG. 2g shows a magnified view of FIG. 2f, indicating a single subst ⁇ pe and its decomposition into writing pixels.
- FIG. 2h shows a magnified view of FIG. 2g, indicating the pixel exposure sequence across a single subst ⁇ pe.
- FIG. 3 shows a block diagram representing an overview of the data path in a first embodiment of the present invention.
- FIG. 4 shows a block diagram of a beamlet pattern memory (BPM) 324 showing the bus and address structure for the first embodiment of this mvention.
- BPM beamlet pattern memory
- FIG. 5a shows a schematic of the arrangement of 121 dies on a 300 mm diameter wafer, with the dotted lines indicating the cell placement.
- the die area is larger than the cell footp ⁇ nt.
- FIG. 5b shows a schematic cross-sectional side-view of FIG. 5a along a horizontal axis through the center of the wafer, indicating cell and die size differences.
- FIG. 6 shows a schematic of how the pattern data for the dies in FIG. 5a (with the die area larger than the cell footprint) is dist ⁇ ubbed to the cells m a cell array.
- FIG. 7a shows a schematic of the arrangement of 157 dies on a 300 mm diameter wafer, with the dotted lines indicating the cell placement.
- the die area is smaller than the cell footp ⁇ nt.
- FIG. 7b shows a schematic cross-sectional side-view of FIG. 7a along a ho ⁇ zontal axis through the center of the wafer, indicating cell and die size differences.
- FIG. 8 shows a schematic of how the pattern data for the dies in FIG. 7a (with the die area smaller than the cell footprint) are distributed to the cells in a cell array.
- FIG. 9 shows a block diagram of a top-level view of the data path in a second embodiment of the present invention.
- FIG. 10 shows a block diagram of the raster image processor.
- FIG. 11 shows a block diagram of a single row buffer board.
- FIG. 12 shows a block diagram of a row buffer indicating the row buffer ASIC design.
- FIG. 13 shows a block diagram of a top-level view of the data path in a second embodiment of the present invention, indicating error detection and correction strategies.
- the data path system for a multiple beam electron lithography system in the present invention enables the patterning of semiconductor wafers directly using a plurality of electron beams, each simultaneously supplied with patterning information from a large pattern library storage device. Before considering the details of the data path system, it is first useful to outline the design considerations impelling the need for a multiple beam electron lithography system.
- Throughput is determined by the total time to expose the wafer plus wafer exchange, align ment, and stage overhead. It is possible to keep this overhead to 25% or less of the total. Thus, 90 s of exposure and 30 s of overhead results m a total time per wafer of 120 s, giving a system throughput of 30 wafers per hour.
- Electron Beam Direct Write (EBDW) lithography requires the beams to be unblanked as they write the patterns.
- the present invention uses a raster scan, in which all the beams simultaneously scan regular raster patterns and the beams are unblanked where the resist is to be exposed and remain blanked where the resist is not to be exposed. Patterns being written are made up of exposed and unexposed pixels, typically square, and at least several times smaller than the minimum feature size.
- Precision electron optics have a limited field size (writing area), which is roughly 100 ⁇ m wide for the column 100 which is part of the present invention.
- the addition of mechanical stage scanning orthogonal to the electronic scan allows a long stripe of pattern data to be wntten. If the mechanical stage repeatedly steps over by the width of the stripe, the whole wafer can be written m a series of long stripes that are abutted.
- A 707 cm 2 for a 300 mm diameter wafer
- T 90 s (combines with 30 s overhead to give 30 wafers per hour)
- p 25 nm
- P 32 beams per column
- GDS-II is an industry standard data format, used to define integrated circuit (IC) mask layers, within a semiconductor chip design.
- the GDS-II data consists of polygonal shapes. These polygons are hierarchically instanced to create complex patterns. Modern IC design methodology constructs extremely dense devices, using a library of characterized, and replicated macrocells. The hierarchy in the GDS-II data allows these dense, but repetitive designs, to be described by a small and manageable data file.
- a GDS-II data file, for all layers of a chip design, will be on the order of 10 MBytes to 2 GBytes.
- the data necessary for a single die will be significantly smaller, but the need to include many of the commonly used macrocells m the definitions of each single die reduces the data compression intrinsic in a typical GDS-II data file significantly.
- a "cell” is defined as a single structure incorporating the source structure to generate electrons, the electron-optics and associated acceleration and deflection structures, and the necessary support electronics.
- the multiple column electron beam lithography system incorporates more than 200
- cells into an mtegrated column structure, consisting of a two dimensional array of rows and columns.
- the multibeam electron hthography (MEL) system uses a 15 x 15 array of electron beam cells, on a roughly 20 mm x 20 mm grid, with 32 beamlets 150 per cell.
- a single cell creates an electronic scan line, which is 102 4 ⁇ m long by a single pixel (25 nm) wide.
- the stage mechanically scans in a direction orthogonal to the scan line, with each cell w ⁇ tmg a 102.4 ⁇ m x 20 mm st ⁇ p of pixels on the wafer, called a cell stripe.
- MEL multibeam electron hthography
- a die stripe is a stripe of pixels that is 102.4 ⁇ m wide and as long as the die. This can be broken down further, where a die substr ⁇ e is a stripe of pixels that is 3.2 ⁇ m wide and as long as the die. If the die is wider than the cell spacing, then a cell stripe will consist of a subset of the die stripe. On the other hand, if the die is narrower than the cell spacing, then the cell stripe will consist of whole and fractional sections of the die stripe.
- the size of the pattern that the die information represents and the size of the pattern that a cell 520 can write have a unique relationship that is determined by the way in which the lithography system writes patterns. Without stage motion, a cell 520 can write a pattern which is 102.4 um wide (along the X-axis), but only one pixel size (25 nm) long (along the Y-axis, the direction of stage scanning), called a "scan line". By moving the stage in the Y-axis direction while scan lines are being written, the cell 520, in combination with the stage, can write a cell stripe that is 102 4_ m in the X- Axis by 20.07 mm m the Y-axis.
- each cell 520 m conjunction with the motion of the stage, writes successive stripes of a pattern, each of which is 102.4 _ m wide by 20.07 mm long, until a complete cell writing area of 20.07 mm by 20.07 mm has been patterned.
- Other cells 520 m the cell array 540 write adjoining 20.07 mm x 20.07 mm areas, where the 15 x 15 cell array 540 covers the entire patterned area on the wafer. Since all cells in the array of cells write simultaneously, the entire wafer has been patterned when a single 20.07 mm x 20.07 mm cell pattern has been written.
- each beamlet in each cell would write the same pattern data at the same time.
- a column of cells as a line of cells in the Y-axis - parallel to the stage motion during cell stripe writing, and a row of cells as a line of cells in the X-axis - perpendicular to the stage motion during cell stripe writing.
- the patterns that the cells have written will have merged into a stripe that extends from one edge of the wafer being patterned to the opposite edge, and that incorporates multiple copies of that single stripe of the die pattern to be written. Since die patterns are placed on the wafer m regular arrays, it can be considered that the system is patterning, in much the same way, rows and columns of copies of the die pattern in question on the wafer being patterned.
- each cell is causing to be w ⁇ tten.
- Cell columns combine to write a single stripe of pattern image that is a repetition of the same die stripe many times over. This is true whether the die stripe is longer than, shorter than or the same length as the cell stripe.
- each cell 520 in a cell column is writing a portion of the same die stripe data. In some cases, two neighboring cells 520 will write parts of the same die.
- a single cell will write parts or all of more than one die.
- An example (m which the numbers have been rounded for simplicity) would be where the cell stripe length is 20 mm and the die stripe length is 15 mm. All cell stripes in this example are written simultaneously.
- the first cell 520 m the cell column would write the full die stripe for the first copy of the die pattern along this column and the first 5 mm of the same die stripe of the second die copy along the column.
- the second cell 520 in the cell column would write the last 10 mm of the same die st ⁇ pe in the second die copy of that column on the wafer and the first 10mm of the same die stripe in the third die pattern copy
- the third cell in the column would write the last 5 mm of the same die st ⁇ pe in the third die copy and would write all of the same die stripe for the fourth copy of the die pattern for that die column on the wafer.
- the cells 520 m a particular cell row each write the same sect ⁇ on(s) of a die stripe on the wafer, but these will only be the same sect ⁇ on(s) of the same die st ⁇ pe if the width (the length along the X- axis) of the cell writing area is the same as the width of the die pattern (again, the length along the X- axis).
- the width is 20 mm and the die pattern width is 15 mm.
- cell “0" of the cell row would write die stripe “0" of the die pattern in die row "0".
- Cell “1” of the cell row would write die stripe "50” of the die pattern m die row "1".
- Cell “2” would write die st ⁇ pe "100” of the die pattern in die row "2”.
- Cell “3” would write die stripe "0" of the die pattern in die row "4".
- the following section describes details of how the data path system m the present invention uses the die pattern information stored in the pattern library storage device 302 to control a multiplicity of writing cells 520 in a cell array 540 to properly pattern wafers with high throughput and high spatial resolution.
- Two patterning examples are discussed m detail: (1) where the dimensions 556 of the dies 502 being written are larger than the dimensions 546 of the cell 520 w ⁇ ting area, and (2) where the dimensions 756 of the dies 704 are smaller than the dimemsions 546 of the cell 520 writing area.
- FIG. 1 shows a schematic cross-sectional side view of a single electron optical column 100 as employed in the present invention.
- the electron source assembly 102 is controlled by the source control 104. Electrons are emitted by each of the field emitter tips 162 due to the electric field induced at the tips 162 by a voltage applied between the tip substrate 164 and the individual gate electrodes 166.
- the source control monitors the currents collected on the beam current monitoring aperture plate 110 and regulates the voltages on the gate electrodes 166 to maintain the beam currents constant.
- Lens electrodes 168 focus the individual beams down the column to the spray aperture plate 109.
- the alignment deflector control 108 provides DC deflection voltages to the alignment deflector
- the beamlets 150 are centered on the blanking aperture by sweeping the alignment deflector voltages to scan the beamlets 150 m a raster over the hole 137 m the blanking aperture 136 while measuring the blanking aperture current with the blanking aperture current sense control 138.
- the beam blanker d ⁇ vers 114 provide the beam blanking signals to the beam blankers 112.
- a small voltage is applied by the blanker driver 114 to the two plates of the blanker 112, thus deflecting the beam out of the hole 137 in the blanking aperture 136.
- the blanker driver 114 sets the blanker 112 voltages to 0 V, and the beam is thus allowed to pass through the hole 137 in the blanking aperture 136.
- the rotator 116 is an electrostatic octupole requiring eight voltage drive signals which are supplied by the beam rotator control 118. Drive voltages to the rotator 116 are set only once during a calibration procedure performed during the initial system setup. The purpose of the rotator 116 is to adjust the azimuthal rotation (rotation around the column axis) of the multiplicity of beams 150 in each column 100 to align with the underlying patterns on the wafer - a process called "overlay".
- the voltage on the shield electrode 120 is controlled by the focus and shield electrode control 122.
- the shield electrode 120 provides an offset bias voltage for individual focusing of each column 100.
- the mainfield deflector control 128 supplies low frequency ( ⁇ 50 kHz) deflection voltages to the mamfield upper 124 and lower 126 deflectors to compensate for stage positioning errors and the normal movement of the wafer 144 under the beams 150 caused by stage movement during scan-line w ⁇ t g.
- the subfield deflector control 132 supplies high frequency (>10 MHz) signals to the subfield deflector 130.
- the subfield deflector 130 provides the fast w ⁇ tmg ramp which generates the scanning of beams 150 on the wafer 144.
- the voltage on the focus electrode 134 controls the fine focusing of each column 100 and is provided by the focus and shield electrode control 122.
- the blanking aperture current sense control 138 monitors the current at the blanking aperture 136 to assist with beam alignment during set-up of the column 100.
- the back-scattered electron (BSE) detectors 140 are controlled by the BSE detector control 142.
- the BSE detectors 140 comprise four silicon PIN diodes.
- the BSE detector control contains four analog pre-amplifiers, and four fast A/D converters. The key function of the BSE detectors 140 is to obtain accurate wafer alignment on each written wafer 144.
- FIG. 2 schematically shows a die 202 with X-Y dimensions corresponding to the largest area which can be written by a single optical column 100, and the decomposition of the die pattern data into die stripes and die subst ⁇ pes.
- the die 202 and die stripes 204 are shown.
- die stripe "1" 206, die st ⁇ pe "2" 208, and die subst ⁇ pes 210 are shown.
- die subst ⁇ pe detail 212 is shown.
- the die 202 has dimensions of 20.0704 mm x 20.0704 mm square, where:
- FIG. 2b close-ups of the ends of die stripe "1" 206 and die stripe "2" 208 are shown, as well as the decomposition of die stripe "1" 206 into 32 die sub-stripes 210. All die stripes 204 are decomposed in the same way as is shown here for die stripe "1" 206.
- FIG. 2c a close-up detail view of a single die sub-stripe 210 is shown.
- the number of 25 nm x 25 nm pixels in each 3.2 ⁇ m wide die sub-stripe is then:
- FIGs 2d-2h show several diagrams depicting the writing strategy employed by the lithography writing head.
- the schematic diagrams in FIGs 2d and 2e show the wafer 144, the writing area 1402, the 32 beams 1406 from each source, the stripe 1414 written by the 32 beams 1406, and the serpentine motion 1418 of the stage.
- FIGs 2f-2h show increasing magnification of the stripe 1414 written by 32 beams 1406 and the subst ⁇ pe 1410 written by a single beam.
- the stripe 1414 is 102.4 ⁇ m in width x 20.0704 mm long, and is composed of 32 subst ⁇ pes 1410, which are 3.2 ⁇ m in width x 20.0704 mm long.
- the width of each subst ⁇ pe 1410 is composed of 64 writing pixels, each of which are 50 nm x 50 nm.
- Each cell covers an approximately 20 mm x 20 mm square writing area 1402 on the surface of the wafer 144. Thus, the entire surface area of the wafer 144 is covered by the 201 cells.
- the 32 beams 1406 are 3.2 ⁇ m apart from each other on the wafer 144, and are simultaneously scanned along the array direction using the subfield deflectors 130. Each pixel is 50 nm x 50 nm, and the subfield deflector
- This subst ⁇ pe 1410 corresponds to the same subst ⁇ pe 204 depicted m FIGs 2a and 2c.
- the stage moves slowly (relative to the beam scanning speed) in the direction pe ⁇ endicular to the scan direction of the subfield deflectors 130 (see FIG. 1). As the stage moves, the 32 beams 1406 are simultaneously scanned back and forth to create a stripe 1414 that is written across the 20 mm x 20 mm writing area.
- FIG. 3 shows a first embodiment of the present invention.
- the pattern library storage In FIG. 3, the pattern library storage
- PLS high-speed data link "1” 304
- controller 306 high-speed data link “2” 308, sub-stripe storage array (SSSA) 310, disk drives 312, data links 314, disk drive controllers 316, high-speed data links "3" 318, beamlet controllers 319, decompression engines 320, row-data links 322, beamlet pattern memories (BPMs) 324 and outputs to blankers 326 are shown.
- An off-line pattern preparation system pre-processes the CAD data (typically in GDS-II format) into compressed die sub-st ⁇ pe blocks. Each die sub-stripe block defines the patterning data for a rectangular section of the die measuring 3.2 ⁇ m by the die height, where "height" is the die dimension along the direction of stage motion.
- PLS 302 Pattern Library Storage
- the storage capacity of the PLS 302 is configurable based on the number of device layers to be randomly accessed.
- the typical compressed data size for a 3 cm x 3 cm device will be about 20 GB, assuming at least a 10: 1 compression of the bit-mapped data.
- Pattern data is supplied to the controller 306 by the high-speed data link "1" 304.
- the SSSA 310 contains an array of disk drives 312, each storing data for four neighboring die sub-stripes. Data from each disk drive 312 is supplied through data link 314 to the disk controller 316.
- each disk controller 316 is shown supplying pattern data to four decompression engines 320 through the high-speed data links "3" 318.
- the exact number of decompression engines 320 required would be determined during design optimization and is not part of the present invention.
- Each decompression engine 320 supplies decompressed pattern data to 15 beamlet pattern memories (BPMs) 324 using the row data links 322.
- BPMs beamlet pattern memories
- the reason that a single decompression engine 320 can supply pattern data to 15 BPMs 324 is that all of these cells share the same stage X-axis coordinate, as illustrated in FIGS. 5a and 7a, where the stage motion during writing is parallel to the Y-axis in this embodiment. It is of note that the axis designation used here is arbitrary.
- Each BPM 324 supplies die sub-stripe data to a single beam blanker driver 114 withm a single cell the cell array 540.
- each electron column 100 withm each cell 520 has 32 beamlets (writing 32 neighboring die sub-stripes), so only 480 (15 x 32) die sub-stripes (out of the total 6272 maximum possible) need to be accessed on any single stripe scan of the stage.
- each disk drive 312 and disk controller 316 supplies die sub-stripe pattern data to four decompression engines 320, so there are 120 disks 312 in the SSSA 310, where
- the stage transit time from start of one cell stripe scan to the start of the next cell stripe scan, assuming a 20 mm cell stripe length, is roughly 500 ms. This is the time allowed to unload the die sub-st ⁇ pe data from each disk in the SSSA 310.
- Each compressed die sub-st ⁇ pe data block is about 2 MB in size, again assuming that we can achieve a compression ratio of about 10:1.
- This 2 MB of data is transferred from the disk 312 to the SSSA controller 316 every cell stripe scan of the stage - to make this transfer in 500 ms implies a data transfer rate requirement of about 4 MB/s through data link 314.
- the complete die sub-stripe data for 4 die sub-stripes of the next die st ⁇ pe are read from the SSSA disk controller 316 memory and delivered to four separate decompression engines 320.
- data for the die stripe following the next die stripe is being unloaded from the disk 312 into the SSSA controller 316 memory.
- each die sub-stripe requires a separate decompression engine 320, requiring 480 individual decompression engines 320.
- the decompression engine 320 broadcasts the same complete decompressed die sub-stripe data to 15 separate BPMs 324, one for each of the 15 scan-aligned (Y-axis, or stage scan direction) beamlets. All scan-aligned beamlets use data from the same compressed pattern data block, but each beamlet will typically read the decompressed pixel data in a different sequence, as shown m TABLES 2 and 4 and FIGS 6 and 8.
- FIG. 4 is a functional block diagram of a beamlet pattern memory (BPM) 324 showing the bus and address structure.
- BPM beamlet pattern memory
- each BPM there is sufficient memory in each BPM to contain both the current and next stripe pixel data.
- the two memory banks 'A' 410 and 'B' 412 alternate so that one is being loaded from the de-compression engine 320 while the other is being read out onto the read data bus 416.
- Individual BPM controllers 406 receive start, stop, and repeat instructions from the control bus 404, allowing each to read its particular sub-stripe data sequence
- the BPM address structure 430 enables the addressing of any beamlet within the entire cell array
- FIGS. 5 and 6 illustrate the patterning of a 300 mm wafer 504 for the case of dies 502 larger than the X-Y spacing 546 of the cells 520.
- dies 502, 300 mm wafer 504, edge exclusion area 505, wafer edge 506, X-axis cell numbers 510, Y-axis cell numbers 512, cells 520, X-axis cell boundaries 530, Y-axis cell bounda ⁇ es 532, and cell spacing 546 are shown.
- FIG. 5a shows the arrangement of a total of 121 dies 502 on a
- the X-axis 530 and Y-axis bounda ⁇ es 532 of the cells 520 are shown as dashed lines, while the X-axis and Y-axis edges of the dies 502 are shown as solid lines. Because the sizes of the dies 502 differ from the sizes of the cells 520, there is a "beat" pattern between them as can be seen from FIG. 5a. For the example shown m FIG. 5, this means that each cell 520 writes an area smaller than the area of a die 502, thus every die 502 is necessarily written by more than one cell 520.
- FIG. 5b shows a schematic cross-sectional side-view of FIG. 5a along a horizontal axis through the center of the wafer 504.
- the next cell column to the right is “B”, and so on, across the cell array 540 to the rightmost cell column “O”.
- a similar scheme is used for die 502 labelling. All the dies 502 in a vertical column at the left of the wafer 504 are called die column "a”. The next die column to the right is "b”, and so on, across the wafer 504 to the rightmost die column "m”.
- FIG. 5b can also represent a cross-sectional side view of FIG. 5a along a vertical axis through the center of the wafer 504 if the labels are changed as follows:
- a ⁇ A', B -» B' ,... , N ⁇ N', 0 -> 0' where now all the cells 520 in the bottom horizontal row of FIG. 5a are called cell row "A' ".
- the next cell row up is "B' ", and so on up the cell array 540 to the topmost cell row "O".
- the die 502 labels are also changed as follows: a -» a', b ⁇ b', ... , 1 -» r, m -* m' where now all the dies 502 in the bottom horizontal row of wafer 504 are die row "a' ".
- the next die row up is "b' ", and so on up the wafer 504 to the topmost die row "m' ".
- the cell row labels "A' " through “O' ", and die row labels "a' " through “m' " are used in
- TABLE 1 describes the allocation of die stripe data to all the cells 520 in the cell array 540 using the notation shown in FIG. 5b.
- the left edge 532 of cell column "A” is aligned with the left edge 552 of die column “a” (at the far left of FIG. 5a).
- die column “a” refers to all of the three dies 502 m the vertical row at the left of the wafer 504 in FIG. 5a.
- Die column “b” refers to all of the 7 dies 502 in the next vertical row to the right, and so on, across the wafer 504 to die column “m” which refers to all of the three dies 502 in the rightmost vertical row of the wafer 504.
- the third line shows that the first die stripes for die column “b" ("0” through “181") are w ⁇ tten by cell column “B", while the remaining die stripes (“182” through “209”) are w ⁇ tten by cell column “C”.
- TABLE 1 shows the complete distribution of die st ⁇ pe data for all the cell columns "A” through “O” of the cell array 540. Note that cell column “N” writes only 182 die stripes and cell column "O" is not used for writing at all.
- die stripes of die column “a” are written sequentially: “0”, “1”, “2”,.... ,”194", "195”, for a total of 196 die stripes out of a total of 210 die stripes for die column "a”.
- the entire wafer 504 has been written by the cell array 540.
- die stripes of die column “a” are written sequentially: “196”, “197”,..., “209”, corresponding to the remaining 14 stripes for die column “a” which were not written by cell column “A”.
- cell column “B” begins to write die stripes of die column “b”: “0”, “1”, .... , “181”, for a total of 182 die stripes.
- cell column “A” has just completed writing die stripe "195" of die column “a” and the entire wafer 504 has been written by the cell array 540. Note that the sum of 14 die stripes for die column “a” and 182 die stripes for die column “b” equals 196, the number of die stripes written by each cell 520 in the cell array 540.
- TABLE 2 describes how the die stripe 204 data is used by each cell 520 along each cell row, i.e., in the perpendicular direction from the cell columns considered in TABLE 1. From FIG 5a, given the definitions of cell columns and cell rows, the following table correlates the X-axis cell numbers 510
- the cell column data consists of the patterning data for the dies 502 being written on the wafer 540.
- the cell row data tells each cell 520 the proper sequence for using the cell column data.
- FIG. 5a shows that all cells 520 along each cell column "A” through “O” write the same die stripe on all of the dies 502 m their respective die columns. For example from TABLE 1 (top line), all the cells
- FIG. 5a shows that the "beat" pattern between the die size 556 and the cell spacing 546 in the vertical (column) direction requires that each of the individual cells 520 along every cell column "A" through “O” must write the pattern data in a different sequence.
- the purpose of the cell row data "A' " through “O' " is to define the proper writing sequence for all of the cells 520 along each horizontal row of cells 520 across the cell array 540, where typically, the proper writing sequence will be different for each cell row.
- TABLE 2 is similar m some ways to TABLE 1 since both tables derive from the "beat" pattern between the writing areas of each cell 520 in cell array 540 and the areas of each die 502 on wafer 504.
- the top row of TABLE 2 shows that cell row "A' " writes a section of the die stripe from 0.00 mm to 20.07 mm, corresponding to the entire length of a cell st ⁇ pe, i.e., the entire distance which any cell 520 can write. Because the die size 556 is larger than the cell spacing 546, there is unused die stripe data, shown in the ⁇ ghtmost two columns of TABLE 2, corresponding to the length of the die stripe from 20.07 mm to 21.50 mm which cell row "A' " could not write.
- FIG. 6 illustrates how the pattern data for the dies 502 on wafer 504 is distributed to the cells 520 in cell array 540, consistent with the table above showing the co ⁇ elation between X-axis cell numbers 510 and the cell column data, as well as the correlation between Y-axis cell numbers and the cell row data.
- each beamlet pattern memory (BPM) 324 was shown to correspond to a single beamlet withm the cell array 540.
- TABLE 2 shows the sections of each die stripe written by each die row, given m distance (in mm) along each die stripe. To convert these distances to address steps along the die stripe, we divide by the pixel size, in this case assumed to be 25 nm. The following table shows conversions from distance to address steps for cell rows "A' ", "B' “, "M' ", and "N' " taken from TABLE 2:
- the fifth column from the left converts the pixel numbers into the hexadecimal addresses used in BPM 324 beamlet addressing.
- the rightmost column shows the writing sequence for the segments of die stripes, as well as the segments of die stripes which are unused in each particular cell row.
- FIG. 6 illustrates the application of the hexadecimal addresses within the various cell rows "A' ",
- each memory block 602 represents the collection of 32 BPMs die stripe memories 604, each supplying blanking data to a separate beam blanker 112 within the optical column.
- memories 604 would correspond to memory bank 'A' 410 in a BPM 324.
- the other or memory bank 'B' 412 would be used in a 'ping pong' alternating use method, as described in FIG. 4.
- FIG. 6 shows the maximum die stripe data storage capability m this embodiment, allowing for a die stripe 30.0032 mm long, giving a maximum number of pixels:
- FIGS. 7 and 8 illustrate the patterning of a 300 mm wafer 704 for the case of dies 702 smaller than the X-Y spacing 546 of the cells 520.
- FIG. 7a dies 702, 300 mm wafer 704, wafer exclusion area 705, wafer edge 706, X-axis cell numbers 510, Y-axis cell numbers 512, cells 520, X-axis cell boundaries 530, Y-axis cell boundaries 532, and cell spacing 546 are shown.
- FIG. 7a shows the arrangement of a total of 157 dies 702 on a 300 mm diameter wafer 704, assuming a 6 mm edge exclusion, i.e., no dies can extend into the area 705 of wafer 704 which is withm 6 mm distance measured radially inwards from the edge 706 of the wafer 704.
- the X-axis 530 and Y-axis boundaries 532 of the cells 520 are shown as dashed lines, while the X-axis and Y-axis edges of the dies 702 are shown as solid lines. Because the sizes of the dies 702 differ from the sizes of the cells 520, there is a "beat" pattern between them as can be seen from FIG. 7a. For the example shown in FIG. 7, this means that each cell 520 writes an area larger than the area of a die 702. In general, most or all cells 520 will write more than one die 702. In some cases, however, cells 520 near the edge 706 of the wafer 704 may write only one die 702.
- FIG. 7b shows a schematic cross-sectional side-view of FIG. 7a along a horizontal axis through the center of the wafer 704.
- the cells 520, cell boundaries 532, 20.0704 mm cell spacing 546, cell array 540, dies 702, die edges 752, die dimension 756, and wafer 704 are shown.
- die 702 labelling All the dies 702 in a vertical column at the left of the wafer 704 are called die column "a”. The next die column to the right is "b", and so on, across the wafer 504 to the rightmost die column "o".
- the cell column labels "A” through “O”, and die column labels "a” through “o” are used in TABLE 3 to illustrate a second specific example of how the data path of the present invention distributes die stripe data to the cells 520 in the multibeam electron lithography system.
- FIG. 7b can also represent a cross-sectional side view of FIG. 7a along a vertical axis through the center of the wafer 704 if the labels are changed as follows:
- a ⁇ A', B ⁇ B' ,... , N ⁇ N', O ⁇ O' where now all the cells 520 in the bottom horizontal row of FIG. 7a are called cell row "A' ".
- the next cell row up is "B' ", and so on up the cell array 540 to the topmost cell row "O”.
- the die 702 labels are also changed as follows: a ⁇ a', b ⁇ b', ... , n ⁇ n', o ⁇ o'
- TABLE 3 describes the allocation of die stripe data to all the cells 520 in the cell array 540 using the notation shown m FIG. 7b.
- the left edge 532 of cell column "A” is aligned with the left edge 752 of die column “a” (at the far left of FIG. 7a).
- all cells 520 in cell column “A” will require the same die stripe data.
- all cells 520 in cell column “B” will also require the same die stripe data, typically different data than for cell column “A”. Similar considerations hold for cell columns “C” through “O” as for FIG. 5a.
- the die column “a” refers to all of the three dies 702 in the vertical row at the left of the wafer 704 in FIG. 7a.
- Die column “b” refers to all of the 7 dies 702 in the next vertical row to the right, and so on, across the wafer 704 to die column “o” which refers to all of the three dies 702 in the ⁇ ghtmost vertical row of the wafer 704.
- TABLE 3 shows cell column "B” first w ⁇ t g die stripes "11" through “184 of die column “b”, then die st ⁇ pes "0" through “21” of die column “c”, for a total of 196 die st ⁇ pes.
- TABLE 3 shows the complete dist ⁇ bution of die stripe data for all the cell columns "A” through “O” of the cell array 540. Note that cell column "O” writes only 31 die stripes. From TABLE 3, we can now detemine the sequence of die stripe data being supplied simultaneously to each of the cells 520 m the cell array 540.
- the first die stripe supplied to cell column "A” is “0" of die column “a", for cell column “B” the first die stripe supplied is “11” of die column “b”, for cell column “C” the first die stripe supplied is "22” of die column “c”, and so on down the third column, labelled “Die Stripes, First” in TABLE 3, to cell column “O” for which the first die stripe supplied is "154" of die column "o".
- die stripes of die column “a” are written sequentially: "0", "1",
- die st ⁇ pes of die column “b” are w ⁇ tten sequentially: “11”, “12”,..., “184”, corresponding to the remaining 174 stripes for die column “b” which were not w ⁇ tten by cell column "A”.
- Cell column "B” then writes die stripes of die column “c”: “0”, “1”, ....
- cell column “A” has also just completed writing 196 die st ⁇ pes and the entire wafer 704 has been written by the cell array 540 Similar considerations hold for cell columns “C”, “D”, .... , "M” m cell array 540.
- the case for cell column “O” is different because it is at the edge of the patterned area on wafer 704.
- the w ⁇ tmg sequence for cell column “O” is die stripes "154", "155”,....
- TABLE 4 describes how the die stripe 204 data is used by each cell 520 along each cell row, i.e., in the perpendicular direction from the cell columns considered m TABLE 3.
- the correlation of the X-axis cell numbers 510 (from 0 through 14) and the Y-axis cell numbers 512 (from 0 through 14) with the required cell column data and cell row data is the same as for TABLES 1 and 2.
- the cell column data consists of the patterning data for the dies 702 being w ⁇ tten on the wafer
- the cell row data tells each cell 520 the proper sequence for using the cell column data.
- FIG. 5a shows that all cells 520 along each cell column "A” through “O” write the same die stripe on all of the dies 702 in their respective die columns. For example from TABLE 3 (top line), all the cells 520 in cell column "A” initially are writing the same die stripe data into all the dies 702 in die column “a”.
- FIG. 7a shows that the "beat" pattern between the die size 756 and the cell spacing 546 in the vertical (column) direction requires that each of the individual cells 520 along every cell column "A" through “O” must write the pattern data in a different sequence.
- the purpose of the cell row data "A' " through “O' " is to define the proper writing sequence for all of the cells 520 along each horizontal row of cells 520 across the cell array 540, where typically, the proper w ⁇ tmg sequence will be different for each cell row.
- TABLE 4 is similar in some ways to TABLE 3 since both tables derive from the "beat" pattern between the writing areas of each cell 520 in cell array 540 and the areas of each die 702 on wafer 704. Since in this example, we have assumed that the X and Y dimensions 756 of dies 702 are the same (which is not part of the present invention), and because the X and Y cell spacmgs 546 are also the same (which is also not part of the present invention), then the corresponding X and Y "beat” patterns are identical. The leftmost two columns in TABLE 4 correspond to the second interpretation of FIG. 7b, described above, wherein the cell row labelling is "A' " through “O' " and the die row labelling is "a' " through “o' ".
- die row "b'” is written with the same die st ⁇ pe data as die row "a' ", thus the rightmost two columns in TABLE 4 show the reused die st ⁇ pe data.
- This reused die st ⁇ pe data is used first to pattern die row "a' " and then second to pattern the beginning of die row "b' ".
- TABLE 4 shows cell row data allocations for die rows "c' " through “o' " Note that for cell row “O' ", die row “o' “ from 15.77 mm to 18.94 mm is written, after which all the cells 520 m cell row “O' " are blanked until cell rows "A' " through “N' " complete writing wafer 704. TABLE 4 shows that for cell row "O' ", there is unused die st ⁇ pe pattern data: 0.00 to 15.77 mm of the die st ⁇ pe - this situation results from the fact that cell row "O' " is at the edge of the patterned area of wafer 704.
- FIG. 8 illustrates how the pattern data for the dies 702 on wafer 704 is distributed to the cells 520 in cell array 540, consistent with the table above showing the correlation between X-axis cell numbers 510 and the cell column data, as well as the correlation between Y-axis cell numbers and the cell row data.
- each beamlet pattern memory (BPM) 324 was shown to correspond to a single beamlet withm the cell array 540.
- TABLE 4 shows the sections of each die stripe written by each die row, given in distance (in mm) along each die stripe To convert these distances to address steps along the die stripe, we divide by the pixel size, in this case assumed to be 25 nm. The following table shows conversions from distance to address steps for cell rows "A' ", "B' “, "M' ", and "N' " taken from TABLE 4-
- the fourth column from the left converts the pixel numbers into the hexadecimal addresses used in BPM 324 beamlet addressing.
- the rightmost column shows the writing sequence for the segments of die stripes, as well as the segments of die stripes which are unused in each particular cell row.
- FIG. 8 illustrates the application of the hexadecimal addresses within the various cell rows "A' “, “B' “, .... , “O' “ for the writing of wafer 704.
- the die stripe numbers from TABLE 4 are shown for the corresponding cell columns "A", “B”, .... , "O”.
- each memory block 602 represents the collection of 32 BPMs die stripe memories 604, each supplying blanking data to a separate beam blanker 112 within the optical column.
- memories 604 would correspond to memory bank 'A' 410 in a BPM 324.
- the 32 memories 604 are labelled "0" through “31” for each cell column "A", ... , "O", shown in FIG. 8, co ⁇ espondmg to the numbering of individual beamlets 150 within the particular columns 100 in the cells 520 corresponding to the memory banks 602.
- the second embodiment is an effort to improve the flexibility and performance of the design, to improve the packaging by reducing the total required board count and to reduce the number and power requirements of those components in the vacuum to reduce the amount of heat generated.
- This second embodiment increases the amount of preprocessing the information goes through before the system begins replicating the die.
- the die layer information is reduced to pixel data p ⁇ or to actual writing of the patterns. This greatly increases the amount of intermediate memory storage, but also greatly improves performance. This also eliminates the need for aligning die patterns and die pattern sizes on cell st ⁇ pe boundaries.
- This embodiment takes advantage of the data structure to reduce the amount of total memory required m the vacuum by having all cells in a common column of cells access different locations in the same physical memory for the data, rather than creating a unique copy of the die data for each cell.
- This embodiment also simplifies the task of generating the intermediate format files and reduces the resultant file size by maintaining the data storage in die stripe width rather than reducing the data to sub-stripe components m the intermediate file format as assumed m embodiment one.
- the stage scans along the X-axis, with each cell writing a 102.4 ⁇ m x 20.0704 mm strip of pixels on the wafer, called a cell stripe.
- a line of cells 520 along the stage scan axis is called a row of cells.
- the stage scan axis is the X-axis in this embodiment of the data path design, and the primary beam scan axis is the Y-axis. This designation is purely arbitrary and used as a convenient convention.
- a die st ⁇ pe is a st ⁇ pe of pixels that is 102.4 ⁇ m wide and as long as the die. If the die is wider than the cell spacing, then a cell stripe will consist of a subset of the die st ⁇ pe. On the other hand, if the die is narrower than the cell spacing, then the cell stripe will consist of whole and fractional sections of the die st ⁇ pe. Thus, withm a row, each cell writes different sections of the same die stripe. This data commonality, along each row, is exploited m the Data Path architecture of the present invention. In this embodiment of the data path design, the all cells 520 along a single row of cells 520 are driven so that the data they write is read from different portions of the same memory image of the die stripe data currently being w ⁇ tten.
- the dies that the cells 520 have caused to be written are put down in repeating patterns that are parallel to the cells 520 themselves.
- the term "row of cells" 520 has been defined to mean a line of cells 520 parallel to the scan direction of the stage.
- the data path can be described as a collection of embedded processors, custom designed ASICs, SDRAMs, glue logic, and software.
- a block diagram of this implementation of the data path is shown in figure 9. Included are Ethernet link 910, which is used by the controller 906 to bring in pattern data from an outside source and the Pattern Library Storage (PLS) 902, which communicates to the controller 906 through the high speed data bus 904.
- the controller 906 communicates to the raster image processor (RIP) 916 through the image data link 908.
- the raster image processor (RIP) 916 converts the pattern data into raster data which is then passed, die stripe by die sfripe, through the raster image pipeline 1116 to the row buffer board 924 array 922.
- the array 922 contains 15 row buffer boards 924 each communicate to the cell 520 array blanking plates 928 via the communication lines 926 that drive blanking plates 112 for all 32 beamlets 150 in each of 15 cells m a row (also see fig. 1). It should be noted that the row buffer board 924 array 922, the communication lines 926 and the call 520 array blanking plates are mounted inside the vacuum enclosure 920, leading to unique implementation issues for the raster image pipeline 1116, which must pass the data through the vacuum bar ⁇ er.
- data is processed in die st ⁇ pes in "Just In Time” fashion. This means that while the system is actually writing the structures for a single stripe, the Data Path is loading the row buffer memories with the data necessary to write the next stripe.
- the hierarchically organized data for a single chip is stored m a format and organization that minimizes file size (typically GDS-II format). It is highly compressed and hierarchical and because it contains all layers - dies - of the chip, makes the file unusable by the multibeam electron lithography (MEL) data path.
- MEL multibeam electron lithography
- An off-line pattern preparation system pre-processes the file into a format that can be used directly.
- This format separates the information necessary for a single layer of the circuit design in question into die st ⁇ pes m the order needed by the rows of cells. This preparation also decomposes the original data format polygonal structures into simpler trapezoids. This intermediate format will expand the data, multiplying its size by a factor of approximately four (4). A single layer will take between 4 Mbytes and 800 Mbytes of storage.
- a multibeam electron lithography (MEL) system will include a Pattern Library Storage (PLS)
- the total size of the PLS 902 is arbitrary as long as there is sufficient storage to allow all intermediate format copies of the requisite data representations of all necessary dies.
- a storage medium capable of holding 500 Gbytes of information would be capable of holding dozens of die data files in intermediate format.
- the functionality of the PLS 902, the combination of the high speed data bus 904 and the controller 906 can be provided by a high-end commercially available file server.
- the data transfer rate is extremely high and the e ⁇ or rate in the data that such a system would deliver to the raster image processor (RIP) 916 is essentially zero, as high-end file servers are designed to operate for many years without an undetected or uncorrected bit error.
- RIP raster image processor
- ECC error correction code
- the controller 906 can be used as the conversion engine for converting the original data format to the intermediate format and storing it in the PLS 902. Alternately, an off-line engine may serve to convert the original circuit design file to the intermediate format. If this were the case, the intermediate files would be downloaded through the Controller 906 to the PLS 902 through the available Ethernet link 910.
- the controller 906 is the first stage of the Data Path pipeline. During lot transition, the controller 906 will transfer the required die layer data file from the PLS 902 across the high speed data bus 904 and send it to the RIP 916 across the image data link 908. The system cannot begin processing wafers until the RIP 916 has completed rasterizing the die data.
- Figure 10 shows a specific implementation of the raster image processor (RIP) 916.
- the data is received from the image data link 908 by the geometry processor 1106, which converts the trapezoid pattern data to write commands and block transfer (BIT) commands and passes them to the raster ASICs via the internal command bus 1108.
- the raster ASICs execute these commands and transfer the resultant pixelated die data to the internal 320 Gbyte pixel RAM array 1112 across the internal memory bus 1114, a bi-directional link between the pixel RAM array 1112 and the raster ASICs 1110.
- the data is read, in stripe format, from the pixel RAM array 1112 by the raster ASICs 1110, and is transferred across the internal pixel memory bus 1114 and out the raster image pipeline 1116.
- the RIP 916 is the second stage in the Data Path pipeline, and is used to convert the intermediate format data into a bitmap pattern for the entire layer.
- the raster image processor (RIP) 916 receives the geometrically represented data across the image data link 908 from the controller 906.
- the geometry processor 1106 traverses the incoming intermediate format data and decomposes the representation - still in a shallow hierarchical form in simple trapezoid geometries - into a flat representation set of trapezoid draw commands and block transfer (BIT) commands.
- BIT block transfer
- ASICs 1110 execute these commands, transfering the pixelated data across the internal pixel memory bus 1114 into the pixel RAM a ⁇ ay 1112, thus generating the bitmap pattern for the full die layer.
- the pattern stored in the 320 GByte pixel RAM array 1112, can be read out, in stripe order, by the raster ASICs 1110 and sent to each of the 15 row buffer boards 924.
- the raster image processor (RIP) 916 is a high speed, raster image processor that requires fast polygon drawing rate (>4 Gpixels/sec), pixel RAM array 1112 with storage for the current layer (> 320 Gbytes), and a high speed data interface to subsequent stages of the Data Path through the raster image pipeline 1116. Bi-directional communications capability is desirable across the raster image pipeline 1116 for verification and timing purposes.
- the raster image pipeline 1116 like many of the communication busses described in this embodiment of the Data Path patent, can be implemented using a number of different technologies and protocols, such as UltraFastWide SCSI, Gigabit Ethernet and Fibre Channel.
- the latter is extremely high speed (>4 Gpixels/sec), robust and can be implemented over a variety of media, including fiber optic, twisted pair and co-axial cable as well as over certain local bus designs. While local bus (or back plain), twisted pair cable or co-axial cable are preferred for their ease and simplicity within a single equipment rack, fiber optic cable has many advantages for the design of the raster image pipeline 1116, as this would simplify the problems associated with running multiple high speed communications cables in parallel in a noisy, high voltage environment and would solve the problems associated with passing cables through a vacuum barrier.
- An implementation of the raster image pipeline 1116 that included an individual high speed Fibre Channel from the RIP 916 to each of the 15 row buffer boards 924 would provide an aggregate data transfer capability of 60 Gpixels/sec.
- the design of the RIP 916 should incorporate features to provide a high level of reliability and availability, and should minimize design and verification complexity, risk and cost.
- the stage transit time from the start of one cell stripe scan to the start of the neighbor cell stripe scan, assuming a 20 mm cell stripe length, is roughly 500 ms. This is the time allowed to load the appropriate die stripe data for the next stripe to be written from the raster image processor (RIP) 916 raster memory 1112 into the memories 1212 of the array of row buffer boards 922 (see fig. 9).
- Each row buffer board 924 contains enough memory 1212 to contain two die stripes - the die stripe that is currently being written and the die stripe that is currently being downloaded from the Raster Image Processor (RIP) 916 through the raster image pipeline 1116.
- Figure 11 shows a specific implementation of row buffer board 924, one of 15 row buffer boards 924 in the row buffer board array 922 (see fig. 9).
- the internal design is broken up into 16 row buffers 1220, each intended to handle the data for two (2) cell sub-stripes and to drive the blanking control for two (2) beamlets 150 within each of the 15 cells in a cell row.
- Each row buffer board 924 receives the data from the raster image processor 916 through the raster image pipeline 1116, which is designed to send data to all 15 row buffer boards 924 simultaneously.
- the data coming in from the raster image pipeline 1116 is fed to the clock and data recovery driver 1206, as is a common clock signal.
- the data which is being fed to the clock and data recovery is broken up into groups of two pixels and sent across the internal data communication bus 1208 to the row buffer
- the row buffer ASICs 1210 send this data across the internal stripe memory pixel bus 1214 to the alternate stripe buffer in the stripe buffer memory 1212, which consists of a 32Mbyte SDRAM array.
- the common clock signal is fed to all row buffer ASICs 1210 which, in turn, use this signal to drive the blanking signal for the individual pixel data, and is fed directly to the 15 cells as a blanking gate pulse to aid in pixel write precision.
- Each row buffer board 924 double buffers two die stripes of pattern data, loaded from the Raster Image Processor (RIP) 916. During writing, the row buffer board 924 reads each cell's appropriate piece of the die stripe.
- Custom circuitry within each row buffer 1220 in this implementation directly drives the blanker plates for two (2) of the beamlets 150 within each of the 15 cells within the cell row with this pattern data. Each row buffer 1220 thus drives 30 blanker plates.
- the row buffer board 924 also contains the clock recovery and blanking gate hardware.
- the row buffer board 924 functions are to input the pattern data from the raster image processor (RIP) 916 into the alternate stripe buffer of the stripe buffer memory 1212, to output the pattern data, as needed, to each cell in the row.
- the structure is further broken down into 16 discrete row buffers 1220, each of which handles the data for two beamlets 150 within a cell for every cell within the cell row controlled by this row buffer board 924.
- a very important additional function is the recovery of the 250 MHz blanking signal clock and the generation of the 2 ns blanking gate pulse.
- Each row buffer board 924 contains 16 row buffer ASICs 1210, and 64 each 4 Mbit 3 16 bit wide double data rate (DDR) synchronous dynamic random access memory (SDRAM) 1212, organized into 16 discrete row buffers 1220. This partitioning accomplishes two goals - the row buffer ASIC 1210 pin count is kept in the range of 208 to 240 pins, keeping the packaging within industry standards, and there is no duplicated die stripe pattern data within the SDRAMs 1212. The complete set of 15 row buffer boards 924 will contain 240 row buffer ASICs 1210 and 960
- All 15 row buffer boards 924 can be located within the vacuum chamber (within which the cells are located), which is desirable because of the cost and complexity of vacuum feedthroughs. If the row buffer boards 924 were outside the vacuum, the system would require 6,600 vacuum feedthroughs. Putting the row buffer boards 924 inside the vacuum reduces this count to 540. The row buffer boards 924 will generate a significant amount of heat, but this heat can be removed by installing liquid cooled plates sandwiched between each of the row buffer boards 924.
- Figure 12 shows a block diagram of a single row buffer 1220 as shown within a row buffer board
- Data and control signals come into the input FIFO 1304 of the row buffer ASIC
- the internal data communication bus 1208 is broken into the data pathway 1308, which flows only into the input FIFO 1304, and the control signal pathway 1306, which is bi-directional. Data is read across the internal bi-directional communications link 1312 from the input FIFO 1304, and control signals are sent to control signals are sent to the input FIFO 1304, by the Memory Queue and Driver Interface
- Data is then sent across the internal stripe memory pixel bus 1214 to the alternate stripe buffer in the stripe buffer memory 1212, which consists of a 32Mbyte SDRAM array.
- the internal stripe memory pixel bus 1214 is broken into the address and control signal path 1316, which flows only into the stripe buffer memory 1212, and the data path 1314, which is bi-directional.
- the output logic driver 1318 requests the memory queue and interface driver 1310 to read the appropriate data from the primary write stripe buffer of the stripe buffer memory 1212.
- the data is received across the internal stripe memory pixel bus 1314 by the memory queue and interface driver 1310 and then sent to the output logic driver 1318 over the data path 1320.
- the output logic driver then clocks all 30 blanking signals to the appropriate cell blanking lines 1322 simultaneously.
- the row buffer ASIC 1210 contains all the logic to support the bitmap buffering and blanking drive for two beamlets 150 (see fig. 1) in all 15 cells within a row of cells. It should be noted that a single row buffer board 924 contains 16 row buffers 1220, enough to drive all beamlets 150 that constitute the output of all cells within a single row of 15 cells.
- the row buffer ASIC 1210 controls 32 MB of SDRAM 1212, loads pattern data, from the raster image processor 916 into SDRAM 1212, reads and serializes the pattern from the SDRAM 1212, and sends 30 blanker signals along blanking lines 1322.
- a specific iteration of the design embodiment shown in figures 9 through 12 that includes error correction hardware is shown in FIG. 13. Included are the Pattern Library Storage (PLS) 902, which communicates to the controller 906 through the high speed data bus 904.
- the controller 906 communicates to the raster image processor (RIP) 916 through the image data link 908.
- the raster image processor (RIP) 916 converts the pattern data into raster data and generates cyclic redundancy check (CRC) information.
- CRC cyclic redundancy check
- the data and appropriate CRC information are then passed, die stripe by die stripe, through the raster image pipeline 1116 to the row buffer board 924 array 922.
- the array 922 contains 15 row buffer boards 924, each with 320 Gbytes of row memory with error correction code (ECC) logic 1008, which is the error correcting equivalent of stripe buffer memory 1212.
- ECC error correction code
- check CRC logic 1006 checks for communications and network data errors and communicates these back to the RIP 916 via the communication lines 1002. Only if no errors are detected are the blanking signals sent out communications lines 926 that drive all 32 beamlet 150 blanking plates in each of 15 cells in a row. The two primary types of errors are classified as hard and soft.
- Hard errors are component failures which require the replacement of the failed component. Reliability requires a design which minimizes these failures as well as simplifying the diagnosis of them. Soft e ⁇ ors are random, non- repeatable errors that are typically caused by electrical noise and radiation, and are transient in nature. Reliability requires a design that can detect and correct these errors on the fly.
- the raster image processor (RIP) 916 will require a 320 Gbytes pixel RAM array 1112 and 100 instances of custom ASICs 1110. These devices typically exhibit 25 failures per billion device hours (commonly called FITs), which would give a mean time between failures (MTBF) for the raster image processor 916 of 23,000 hours.
- FITs failures per billion device hours
- redundancy and automatic monitoring systems can be included in this implementation of the design.
- this implementation accommodates easy diagnosis and replacement of subsystems and components.
- the row buffer boards 924 in this embodiment include self-checking logic. This includes such error handling hardware as cyclic redundancy check (CRC) 1006 for the blanking data to the tips, as well as fault tolerant hardware (row memory with ECC 1008 and other corrective measures, such as redundant circuitry).
- CRC cyclic redundancy check
- fault tolerant hardware row memory with ECC 1008 and other corrective measures, such as redundant circuitry.
- ECC memory An alternative to ECC memory is to have CRC for the raster image processor (RIP) 916 hardware that will generate CRC Check codes withm the row buffer 1004. This can be used to correct errors in the row buffer board 924 and can detect (but not correct) hard and soft errors in the RIP 916.
- CRC logic comprising the Extract CRC block 1004 supplying the CRC to the Check CRC 1006 block, which compares the CRC with a second CRC generated from the data supplied by the row memory 1008
- the line data is prevented from reaching the blankers by the output logic 1318 of the row buffers 1220
- the stage would then be stopped, turned around and the st ⁇ pe re-t ⁇ ed starting at the next unwritten line.
- Another potential source of soft errors is the transmission of data from the RIP 916 to the row buffer boards 924.
- a 300mm wafer has 10 14 pixels.
- the data link between the RIP 916 and the row buffer boards 924 will need a bit error rate of 10 "16 .
- a typical data link suitable for use for the raster image pipeline 1116 between the RIP 916 and the row buffer boards 924 has an uncorrected Bit Error Rate of 10 "5 .
- a commercially available forward error correction chipset is typically capable of improving this bit error rate to 10 "20 , which is more than adequate. This forward error correction strategy is not shown in figure 13.
- the data path design could be used for a multiple ion beam system.
- the data path design could be used for any lithography system with more than one cell in conjunction with more than one charged particle beam per cell.
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AU41359/01A AU4135901A (en) | 1999-11-07 | 2000-11-07 | Data path design for multiple electron beam lithography system |
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EP1387389A2 (en) * | 2002-07-30 | 2004-02-04 | Hitachi, Ltd. | Multi-electron beam exposure method and apparatus |
WO2004038509A2 (en) * | 2002-10-25 | 2004-05-06 | Mapper Lithography Ip B.V. | Lithography system |
WO2004044653A2 (en) * | 2002-11-06 | 2004-05-27 | Applied Materials Israel, Ltd. | Method and device for rastering source redundancy |
WO2008052080A2 (en) * | 2006-10-25 | 2008-05-02 | Kla-Tencor Technologies Corporation | Method of data encoding, compression, and transmission enabling maskless lithography |
WO2009127659A3 (en) * | 2008-04-15 | 2009-12-10 | Mapper Lithography Ip B.V. | Beamlet blanker arrangement |
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US8258484B2 (en) | 2008-04-15 | 2012-09-04 | Mapper Lithography Ip B.V. | Beamlet blanker arrangement |
US8653485B2 (en) | 2008-04-15 | 2014-02-18 | Mapper Lithography Ip B.V. | Projection lens arrangement |
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