WO2001004760A1

WO2001004760A1 - Memory controller

Info

Publication number: WO2001004760A1
Application number: PCT/JP1999/003669
Authority: WO
Inventors: Shin Kokura; Kenichi Kurosawa; Hidehito Takewa; Shuji Ishikura; Koji Matsuda
Original assignee: Hitachi, Ltd.
Priority date: 1999-07-07
Filing date: 1999-07-07
Publication date: 2001-01-18
Also published as: JP3956698B2

Abstract

In data prefetching, there can be a case where previously accessed data becomes useless and the memory efficiency declines. To control data prefetching for an area where data to be accessed sequentially is stored and an area where data is not sequentially accessed, a memory is divided in areas and a register is provided for judging for each area whether data is prefetched or not by a memory controller. A mode register for the area where data to be accessed sequentially is stored is set in a prefetch mode and a mode register for the area where data is not sequentially accessed is set in a non-prefetch mode. Thus, the memory controller prefetches data only in accessing the area where data prefetching is necessary, thereby improving the memory efficiency.

Description

Specification

Memory controller Technical field

The present invention relates to a data processing device, and more particularly to a prefetch control of a memory control device that performs a prefetch from a memory. Background art

In the field of computers, general programs tend to reuse data that has been accessed once, and also tend to refer to data that is near data that has been accessed once. These tendencies are called local references. In many computers, a high-speed memory called cache memory is placed between the CPU and the memory in order to reduce the latency of memory access by utilizing this local referability. This cache memory has a copy of the recently accessed memory, and instead of accessing the memory, accesses the cache memory, which is faster than the memory, to reduce the latency of memory access. We are working to reduce this and improve processing performance.

The cache controller that manages the cache memory manages the validity and invalidity of the contents stored in the cache memory in units of n times the data size processed by the CPU. A unit that manages this cache memory is called a cache line. In the case of a 32-bit architecture CPU, this cache line is n times 4 bytes, usually 16, 32, 64, and 128 kb. . The transfer from the memory to the cache memory performed by the cache controller is a management unit. This is done on a cache line basis.

On the other hand, in a memory, a DRAM or a synchronous DRAM is used. In a DRAM or a synchronous DRAM, storage elements are arranged in a grid, and each storage element is accessed by designating a row and a column. Do In these memories, the access time for different columns in the same row is shorter than the access time for specifying a row and then specifying a column. In the case of DRAM, a method of successively accessing storage elements in different columns in the same row is called page mode access, and in the case of synchronous DRAM, it is called burst mode access.

The case where instructions and data necessary for processing by the CPU do not exist in the cache memory is called a cache miss. When a cache miss occurs, the cache controller continuously reads data of the cache line size from the memory. This read operation is called a cache fill operation. The memory controller assumes that when a read access from the CPU to the memory occurs, a cache miss occurs and a cache file operation occurs, and the memory controller performs a page mode or a burst mode. Data is read ahead of time. The read data is stored in a buffer in the memory controller. This operation is called prefetch.

As a technique for controlling this prefetch operation, there is a technique described in Japanese Patent Application Laid-Open No. H10-55307. In Japanese Patent Application Laid-Open No. H10-55307, a CPU generates a control signal indicating whether a request for a memory is a request for an instruction or a request for data. By incorporating a prefetch logic circuit that determines the amount of data to be prefetched from the memory to the cache memory according to this control signal, unnecessary memory access is reduced and the efficiency of the memory system is reduced. Has been improved. Further, Japanese Patent Application Laid-Open No. 5-2717163 discloses a technique for efficiently using a cache by controlling the replacement of data once prefetched in a cache memory. I have.

Japanese Unexamined Patent Publication No. Hei 10-55307 discloses a method of prefetching data from memory due to the difference between memory access to instructions (instruction fetch) and memory access to data (data fetch). By changing the amount, the efficiency of the memory system is improved. However, in Japanese Patent Application Laid-Open No. 10-55307, the re-fetch is controlled by a control signal indicating whether it is a request for an instruction or a request for data. Very high possibility of continuous access like data used for array or matrix operation, and passing data that is effective to prefetch and data with IZ0 or other CPU For example, there are data that cannot be prefetched effectively, such as data to be processed and data whose processing size is small and unnecessary memory access occurs frequently when prefetching is used. Even if it says data in this way, there is a case where the performance is improved by performing pre-fetching, and a case where the performance is deteriorated by performing pre-fetching conversely. However, it is difficult to improve the access efficiency of the memory system if the amount of data to be prefetched from the memory is determined solely because of data access.

On the other hand, in Japanese Patent Application Laid-Open No. Hei 5-271 673, the presence or absence of a prefetch and the replacement are controlled in units of cache entries. It is necessary to register the address of the tree, and it is necessary to specify the necessity and unnecessary of prefetching in detail, and change the amount of data prefetched from the memory. It is difficult.

An object of the present invention is to prefetch data from a memory in accordance with how data is used. It is to improve the efficiency of the memory system by making it possible to change the amount of data to be touched. Disclosure of the invention

The memory address space is divided into a plurality of areas, and a mode register that determines whether or not the memory controller performs prefetching for each of the divided areas is provided to the memory controller. Provide. In accordance with the mode register, the memory controller operates the prefetch function for each area including the address of the memory accessed by the CPU, and accesses data from the memory.

In a program that performs processing, it is unnecessary to set the mode register in the area that stores valid data for prefetching to the prefetch operation mode and use prefetching. Set the mode register in the area that stores data that frequently accesses frequently to the prefetch non-operation mode.

By this, when reading data continuously, the prefetch function is operated, and the data is read continuously continuously in advance, and the data to be accessed by one shot is prefetched. This makes it possible to control from a program so that unnecessary data reading caused by performing the etching is not caused, thereby improving the memory access efficiency. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a prefetch state management unit. FIG. 3 is a timing chart showing the operation of the computer according to the embodiment of the present invention. It is a gujaat.

FIG. 4 is a diagram showing a state transition of the state management unit.

FIG. 5 is a state transition diagram showing the operation of the memory sequencer.

FIG. 6 is a configuration diagram of a computer having a function of setting a mode register.

FIG. 7 is a configuration diagram of the access monitoring unit.

FIG. 8 is a diagram showing a state transition of a continuous access determination logic.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a portion related to memory control of a data processing device, such as a computer or a programmable controller to which the present invention is applied, according to an embodiment of the present invention. . The CPU 1 has a cache memory 20 composed of a memory that can be accessed at high speed. A copy of the contents of DRAM 7 is stored in cache memory 20, but no distinction is made between instructions and data. In the present embodiment, CPU 1 has a 32-bit architecture, and has an address bus ADDR, a 4-byte data bus DAT, a bus start signal BS- indicating the start of the bus, and an access space. Normally, three chip select signals CS0—, CS1—, and CS2—are used to select the memory elements connected in multiples, and CPU1 is used while read data is invalid. As means for stopping, each terminal of ゥ 8 signal WA IT— shall be provided. The "-" at the end of the signal name indicates that the signal is active. The DRAM 7 is a DRAM that can be accessed in the page mode, and has a row address select signal RAS and a column address select signal. It has a function to output read data corresponding to the row address and column address output to the address bus A to the 4-byte data bus D by the CAS— operation. The memory controller 2 includes a prefetch state management unit 5, a memory sequencer 4, a prefetch buffer 6, and a selector 11.

The CPU 1 reads data from the DRAM 7 via the memory controller 2 when an instruction or data necessary for processing is not present in the cache memory 20. At this time, the bus start signal B S— is asserted for one cycle. At the same time as the assertion of the bus start signal BS—, the address storing the instruction data necessary for processing is output to the address signal ADDR. Further, at this time, one of the chip select signals CS0—, CS1— and CS2— indicating the address area of the memory where the instruction data is stored is asserted. The bus start signal B S- and the chip select signals C S0—, C S1—, and C S2— are input to the prefetch state management unit 5 of the memory controller 2. The prefetch state management unit 5 prefetches data from the DRAM 7 to an address area corresponding to each of the chip select signals CS0_, CS1, and CS2—. A mode register 8 is provided to control the two modes of whether or not. That is, in the present embodiment, the unit of the area for controlling the prefetch is for each chip select space.

The prefetch state management unit 5 controls the memory sequencer 4, the prefetch buffer 6, and the output selector 11 according to the value of the mode register 8. From the prefetch state management unit 5, a start signal REQ to the memory sequencer 4 and a prefetch access indicating whether the memory access requested by the start signal REQ is a prefetch access or not. Signal PRF is output Is forced. Also, a data valid signal DV indicating that valid data is being output from the DRAM 7 to the data bus D is input.

The memory sequencer 4 controls the row address select signal RAS— and the column address select signal CAS— in accordance with the start signal REQ and the prefetch access signal PRF from the prefetch state management unit 5, and Control to read data from DRAM7. The memory sequencer 4 includes a row / column address generator 51. The row / column address generator 51 generates a row address and a column address according to the address ADDR from the CPU 1, and outputs a row address select signal RAS— and a column address select signal output from the memory sequencer 4. The row and column addresses are output to address bus A in synchronization with the control timing of the control signal CAS—.

The prefetch state management unit 5 includes a prefetch buffer data set signal PBSET for setting data in the prefetch buffer 6 and an output selector selection signal OPSEL for selecting an output of the output selector 11. Thus, the prefetch buffer 6 and the output selector 11 are controlled. The prefetch buffer 6 is composed of four-stage buffers for storing data to be read ahead in one prefetch. In the present embodiment, one prefetch prefetches cache line data, which is the number of data stored in one entry of the cache 20. One cache line is 16 notes, equivalent to four 32 bits (four bytes) of data. Accordingly, one stage of 32-bit data is stored in each stage of the prefetch buffer. The data size of the cache line varies depending on the configuration of the cache, and the data size to be prefetched in the present invention is not limited to 16 bytes. The prefetch state management unit 5 has a function of setting the data output from the DRAM 7 to the data bus D to the buffer of an arbitrary stage in accordance with the value of the prefetch buffer data set signal PBSET. It has. Specifically, when the prefetch buffer data set signal PBSET is 0, the data output from the DRAM 7 is set in the first-stage buffer, and when the signal PBSET is 1, The data output by DRAM 7 is set in the second-stage buffer, and when the signal PBSET is 2, the data output by DRAM 7 is set in the third buffer, and the signal PBSET is output. In the case of 3, the data output from DRAM7 is set in the fourth buffer. All data stored in all buffers are output to the output selector 11.

The output selector 11 selects the data output by the DRAM 7 and the data output by the prefetch buffer 6 according to the value of the output selector selection signal OPSEL, and outputs the selected data to the processor data bus DAT. Specifically, when the signal OPSEL is 0, the first stage of the prefetcher buffer 6 is output to the processor data bus DAT, and when the signal OPSEL is 1, the second stage buffer and signal are output. When the OPSEL power is 2, the third buffer and when the signal OPSEL is 3, the value of the fourth buffer is output to the processor data bus DAT.

In the software executed by CPU 1, data is classified into the following two types. One is very likely to be accessed continuously, such as data used for array or matrix operations, and the data that can be prefetched is effective. Data that cannot be used by the cache memory because data is transferred to and from ZO, or data that requires unnecessary memory access frequently if prefetching is performed because the size of the data to be processed is small. You. Such a classification is to be performed in advance by a program creator when a program is created. Then, when compiling and linking the program, the area of DRAM 7 that stores valid data to be prefetched and the unnecessary access when prefetching is performed. The area of DRAM 7 that stores data that frequently occurs is placed in a different chip select space. Instructions are placed in areas that store data that is valid for prefetching.

In the program initialization routine, the mode register 8 corresponding to the chip selector signal indicating the area where prefetch valid data is stored is set to the prefetch accessible mode, and the prefetch is performed. Sets the mode register 8 corresponding to the chip selector signal indicating the area for storing unnecessary data to the prefetch access prohibition mode. The means for setting the value of the mode register 8 is not particularly shown, but is performed by access from CPU 1 to a specific address in the register space determined by hardware.

The mode register 8 may be provided independently for each chip select space as many as the number of chip select signals or in the form of a register file. A circuit capable of storing a 1-bit state may be provided for each chip select space, as long as it is possible to identify whether or not the pre-fetch is possible for each chip space. However, in the following description, at least chip select is required. The explanation is made by associating the chip select space with each bit of one register having the bit width of the number of signals. Then, by examining the value 0Z1 of each bit of the mode register 8, it is determined whether or not the prefetch can be performed at the time of access in the corresponding chip select space. FIG. 2 is a block diagram showing a configuration of the prefetch state management unit 5. The detailed function of the prefetch state management unit will be described with reference to FIG. The prefetch state management unit 5 includes a state management unit 52, a buffer management unit 53, an access determination unit 56, a mode register 8, a comparator 54, and an address buffer 55. The access determination unit 56 receives the chip select signals CS 0—, CS 1—, and CS 2— output from the CPU 1 and the value of the mode register 8 as inputs, and outputs the prefetch availability determination result signal JUG. Output. The prefetch enable / disable determination result signal JUG is a logical product of the chip select signals CS0—, CS1—, and CS2—and the set value of the mode register 8 corresponding to each chip select signal. And the logical sum of the results. The prefetch enable / disable judgment result signal JUG indicates whether the memory area indicated by the currently asserted chip select signal is set to enable prefetch or disable prefetch. This signal is asserted if prefetching is possible, or negated if prefetching is disabled.

The address buffer 55 holds the value of the address bus ADDR of the CPU 1 when the address buffer set signal ABSET from the state management unit 52 is asserted. The comparator 54 compares the value of the address bus 55 with the address bus ADDR of the CPU 1, and compares the value of the address buffer 55 with the value of the address bus ADDR of the CPU 1 with the lower 4 bits. Asserts the comparison result signal HIT if the values except the bits match, or negates if they do not match. Here, the value to be compared except for the lower 4 bits is the data force 16 bits that are prefetched at a time, and the address is within the range of the lower 4 bits. For this reason, the address comparison is performed excluding the lower 4 bits to determine whether or not an address in the same prefetch range is being accessed. The state management unit 52 includes a bus start signal BS— which is an output signal of the CPU 1, a prefetch determination result signal JUG which is a determination result of the access determination unit 56, and a data validator from the memory sequencer 4. This is a state transition block in which the internal state transitions when the input signal DV is input. The state management unit 52 outputs a start signal REQ, a prefetch access signal PRF, an address buffer set signal ABSET and a wait signal WAIT— according to the transition of the internal state, and furthermore, the state management. Outputs the internal state of section 52 to status signal ST.

FIG. 4 shows a state transition diagram of the state management unit 52. The state 100 is a state indicating that the data stored in the prefetch buffer 6 in FIG. 1 is invalid. State 101 is a wait state in which the start of prefetch is instructed by the prefetch access signal PRF and the first data is ready. Similarly, state 102 is a state in which prefetching has been started and the second data is being waited for. Similarly, states 103 and 104 are states in which the third and fourth data are being waited for, respectively. In the present embodiment, since four data are pre-read by one prefetch, there are four states in which each data is temporarily waited until it is ready. The state 106 is a state indicating that prefetching has been started and four valid data have been stored in the prefetch buffer 6. On the other hand, the state 105 is a single access state indicating that only the data requested by the CPU is accessed without executing the prefetch access. Therefore, the activation signal REQ is asserted in the states 101, 102, 103, 104 and 105, and the prefetch access signal PRF is set in the states 101, 102, 1 Asserted at 0 3, 104, and transmitted to memory sequencer 4. Also, from state 100 to state 101, state 100 When transitioning from state 106 to state 105, state 106 to state 101, and from state 106 to state 105, that is, instructing the start of prefetch or single-shot access At this time, the address buffer set signal ABSET is asserted, and the address buffer 55 holds the value of the address bus ADDR of CPU 1.

These are the internal states related to the prefetch state. Apart from these internal states, there is state 10Ί108 as an internal state indicating a request state from the CPU. State 107 is a state in which an access request from the CPU can be accepted. State 108 is a state in which the data requested by the CPU is not ready, and thus the CPU is waiting for data.エイ Eight signal WAIT— is asserted at the time of transition from state 107 to state 108 and at state 108, and is reported to CPU1.

Next, transition of each state will be described. The initial state of the state management unit 52 is such that there is no access request from the CPU 1, there is no prefetched data, and the access request from the CPU 1 can be accepted at any time. It is in state 100 and state 107.

First, as for the state transition related to prefetching, the transition condition for transition from state 1001 to state 101 is that bus start signal BS— is asserted and prefetching is performed. That is, the judgment result signal JUG is asserted. In other words, this is a case where an access request from the CPU 1 is generated and the value of the mode register 8 corresponding to the chip selector space including the address specified by the access indicates a state in which prefetching is performed. On the other hand, the transition condition from the state 100 to the state 105 is that the bus start signal BS— is asserted and the prefetch availability judgment result signal JUG is negated. is there. State from state 101 to state 102, state from state 102 The conditions for transition from state 103, state 103 to state 104, state 104 to state 106, and state 105 to state 100 are as follows. Signal DV is asserted. That is, the data from the memory output for each data request becomes valid. The transition condition from the state 106 to the state 101 is that the bus start signal BS— is asserted or the state 108, the comparison result signal HI HI is negated, and the pre- Switch enable / disable determination result signal JUG is asserted. That is, an access from CPU 1 occurs, and the address range of the address previously read ahead stored in address buffer 55 does not overlap with the address of the next access, and This is the case when the access is to an area that performs prefetching. On the other hand, the transition condition from the state 106 to the state 105 is that the bus start signal BS— is asserted or the state 108, and the prefetch availability judgment result signal JUG is negative. In the case of This is the same as the transition condition for transition from state 100 to state 105, in which an access from CPU1 occurs and the access is to an area where prefetching is not performed.

Next, the transition conditions from the state 107 to the state 108 are as follows: 1) The bus start signal BS- is an assert and the prefetch availability judgment result signal JUG is a negative, or 2) The comparison result signal HIT of the comparator 54 is asserted and the pref X switch enable / disable judgment result signal JUG is asserted, and any of the states 101, 102, 103, 104 If it is determined that the data to be read is not set in the prefetch buffer 6 according to the ADDR of the CPU 1 and the current state, either of the above is true. Whether the data to be read by the CPU 1 is set in the prefetch buffer 6 is determined by, for example, the address buffer 55 if the internal state is state 102. It can be determined based on whether or not the value stored in the address indicated by is already set in the prefetch buffer 6. If the internal state is state 102, the address indicated by the address buffer 55 and the value stored next to the address indicated by the address buffer 55 are both prefetch buffers. It can be determined based on whether or not it has already been set to 6. The other states can be similarly determined. The condition for transition from the state 108 to the state 107 is that necessary data is set in the prefetch buffer 6 or the data knowledge signal DV is asserted in the state 105.

The buffer management unit 53 includes a state signal ST indicating the internal state of the state management unit 52, the lower 4 bits of the address bus ADDR from the CPU 1, and the comparison result signal HIT of the comparator 54. Is a logic block that takes the input as an input and outputs the prefetch buffer set signal PBSET that sets data in the prefetch buffer 6 and the output selection signal OPSEL of the output selector 11. . The signal OPSEL has four values from 0 to 3 corresponding to the number of data of one cache line to be read ahead by prefetching, and outputs 0 when the signal HIT is negated. When the signal HIT is asserted, the result of decoding the lower 4 bits of the address bus ADDR is output. Similarly, the prefetch buffer set signal PBSET also has four values from 0 to 3, and the state management unit 52 is in the state 102 in FIG. 4 according to the value of the state signal ST. 1 if the state management unit 52 is in the state 103 in FIG. 4, 2 if the state management unit 52 is in the state 104 in FIG. 4, and otherwise. Asserts 0 in the state of.

FIG. 5 shows the operation of the memory sequencer 4 as a state transition diagram. The state 110 is the idle state, and the prefetch state management unit 5 It indicates the state of waiting for the start signal REQ from. State 1 1 1 indicates a row address access state, in which the RAS address of DRAM 7 corresponding to the address accessed from CPU 1 is output to address bus A, and row address select signal RAS -Is asserted. State 1 1 2 indicates the first column address access state, in which the DRAM 7 CAS address corresponding to the address accessed from CPU 1 is output to address bus A, and the column address select signal is output. CAS— is asserted. States 113, 111, and 115 indicate the second, third, and fourth row address access states that are performed prior to the prefetch, respectively. The initial state of the memory sequencer 4 is state 110. The transition condition from state 110 to state 111 is the assertion of the activation signal REQ. This starts access to DRAM 7.

The transition conditions for transitioning from state 1 1 1, state 1 1 2, state 1 1 3, state 1 1 4, state 1 15 to the next state are determined by the DRAM 7 access time, and the DRAM 7 access time Each time elapses, the state transits to the next state. In particular, in state 112, when the access time of DRAM 7 elapses, the state transits from state 112 to state 113 if the prefetch access signal PRF is asserted, and if it is negated. Transition from state 1 1 2 to state 1 110 is made. That is, after one data is accessed from the DRAM 7, if the prefetch is specified, the CAS address of the data to be prefetched is continuously output under the same RAS address, and One cache line of data will be accessed continuously. Note that the data knowledge signal DV is in a state where the CAS address is output, the data read from the DRAM 7 is determined, and the access for one data is completed 1 1 2, 1 1 3, 1 1 4, Asserted on transition from 1 15 to the next state. FIG. 3 is a timing chart showing the operation of the memory controller 2 shown in FIG. The CPU 1 and the memory controller 2 shown in FIG. 1 operate in synchronization with a clock signal CLK not shown in FIG. 1, and are selected by CS 0— of the CPU 1. The area corresponding to the address space of the DRAM chip (hereinafter referred to as the CS0_ area; the same applies to other areas) is the prefetch disabled mode, and the CS1 area is the prefetch area. It is assumed that the switchable mode is set.

First, CPU 1 shall access address ADDR 1 in the CS 0— area. In this case, BS_, CS 0— is asserted, and the address ADDR 1 is output to ADDR. The prefetch state management unit 5 of the memory controller 2 asserts WAIT—until the data of ADDR1 is ready, that is, until the data is determined on the data bus DAT. At the same time, REQ is asserted to the memory sequencer 4 to notify the occurrence of access. At this time, the prefetch access signal PRF is not asserted because the CSO area is set to the prefetch disable mode. The memory sequencer 4 outputs the row address R1 corresponding to the address ADDR1 accessed from the CPU 1 to the address bus A, and asserts RAS—. Next, the column address C1 of ADDR1 is output to address node A, and CAS— is asserted to determine the access address to DRAM 7. By the operation of the memory controller 2, the DRAM 7 outputs the data D1 corresponding to ADDR1 to the memory data bus D. Therefore, the memory sequencer 4 asserts the data read signal DV to the fetch state manager 6 at the timing when the data D1 is output to the memory data bus D. The prefetch state management unit 5 negates the wait signal WAIT. In response to the assertion of the data valid signal DV, and selects the selector. 11 outputs the data D 1 output to the memory data bus D to the processor data node DAT of the CPU 1.

Next, it is assumed that CPU 1 accesses the address ADDR5 of the CS1-region. Since the CS1—area is set in the prefetch enabled mode, the prefetch state management unit 5 asserts PRF. The memory sequencer 4 outputs the row address R5 corresponding to the address ADDR5 to the address bus A, and asserts RAS—. Subsequently, a column address C5 corresponding to ADDR5 is output and CAS— is asserted. At this time, since the PRF is asserted, C6, C7, and C8 are continuously output to the address bus A, and CAS— is also asserted in response to the output of each column address. Repeat the steps in the same way. Here, the column address C 6 is a value obtained by adding 1 to the column address C 5, C 7 is obtained by adding 1 to C 6, and C 8 is obtained by adding 1 to C 7. The data corresponding to the row address R5 and the column address C5 is D5, the data corresponding to the row address R5 and the column address C6 is D6, and the row address is D5. The data corresponding to R5 and column address C7 is D7, and the data corresponding to row address R5 and column address C8 is D8. Then, these data D5 to D8 are continuously output to the memory data bus D.

Also, it is possible to set the CS1 area to the prefetchable mode, and the instructions and data stored in the CS1 area can be accessed continuously like data used for array or matrix operations. If the fetch is very large and prefetching is a valid data or instruction, then access to ADDR5 followed by ADDR6 is likely to occur. The row address of ADDR6 is R5, and the column address is C6. In other words, the data corresponding to ADDR 6 is D6, and if CPU 1 next accesses ADDR 6, Since this data has already been read from the DRAM 7 and stored in the prefetch buffer 6, it is possible to output D6 to the processor data bus without asserting the wait signal WAIT— to the CPU 1. And become possible. In addition, since the prefetch operation is not performed for the CS0—area, DRAM7 is idle between the time when D1 is output to the memory data bus D and the time when D5 is output. State. In other words, there is no additional unnecessary memory access, which increases the efficiency of DRAM 7 and increases the data processing capacity of the entire system.

In the above description, the chip select signal has been used to identify, when the DRAM 7 is divided into a predetermined area, the access from the CPU 1 to the divided area. The chip select signal may be used in its original sense to distinguish the DRAM chip itself that constitutes the memory. In this case, execution / non-execution of prefetch is controlled for each memory chip. This makes it possible to control the prefetch according to the re-memory configuration.

FIG. 6 shows an embodiment provided with a function of changing the setting of the mode register 8 described in FIG. 1 based on the actually accessed address. In this embodiment, an access monitoring unit 70 for changing the value of the mode register 8 is provided inside the prefetch state management unit 5. The access monitoring unit 70 receives the chip select signals CS 0—, CS 1—, CS 2—, the bus start signal BS—, and the comparison result signal HIT as input, and outputs the chip select signal as output. Set 0, Set 1, and Set 2 are signals that set the value of mode register 8 corresponding to signals CS 0—, CS 1—, and CS 2—, respectively, and Rset 0 is a signal that resets similarly. , Rset 1 or Rset 2 is asserted. FIG. 7 is a diagram showing an outline of the inside of the access monitoring unit 70. The access monitor 70 includes a continuous access determination logic 71 and a mode register selection logic 72. FIG. 8 is a state transition diagram for explaining the operation of the continuous access determination logic 71. The initial state of the continuous access determination logic 71 is the first state in which access is performed first, which is state 910. Next, when access from CPU 1 starts, the HIT signal, which indicates that the previously accessed address matches the address accessed this time except for the lower 4 bits, is asserted. In addition, if the same chip select signal as the previously accessed chip select space is asserted, that is, if the next access is made within the same cache line as the first access, Transit to the second consecutive access state, which is state 9 1 1. In this state, two consecutive accesses are made to the same prefetch range. In this state 911, CPU 1 further accesses the same chip select space, indicating that the previously accessed address and the currently accessed address are identical except for the lower 4 bits. When the HIT signal is asserted, the state transits to the third consecutive access state, state 912. In this state, three consecutive accesses are made to the same prefetch range. Also, the condition for transition to the third consecutive access state is not satisfied. The state transits to state 910, which is the initial state in which CPU 1 accesses occur. Similarly, in the third consecutive access state in state 912, if CPU 1 accesses the same chip select space and the HIT signal is asserted, the fourth consecutive access in state 913 is performed. The state transits to state 910. On the other hand, when an access of CPU 1 that does not transit to state 913 occurs, the state transits to state 910.

In state 9 13, transition to state 9 10 when CPU 1 starts access I do. However, when transitioning from state 913 to state 910, the continuous access decision logic 71 asserts the prefetchable signal PFON. When transitioning from state 911 or state 912 to state 91, the continuous access decision logic 71 asserts the prefetch disable signal PFOFF, that is, one cache line. If all of the accesses are made within the same prefetch range when accessing the same amount of data, the prefetch is valid in the chip select space where the access was made. Upon determining that data is stored, the continuous access determination logic 71 asserts the prefetch enable signal PF0N, but otherwise, the preselection space is stored in the chip select space. Judge that the switch is invalid and assert the prefetch disable signal PFOFF.

The mode register selection logic 72 has the function of retaining the chip select signal accessed last time.When the PFON signal is asserted, the mode register 8 sets the signal corresponding to the retained chip select signal. Assert any one of Set 0, Set 1, and Set 2. When the PFOFF signal is asserted, one of Rset0, Rset1, and Rset2, which is the reset signal of the mode register 8 corresponding to the held chip select signal, is asserted. When the mode register 8 is set, it indicates the prefetch access enabled mode, and when reset, it indicates the prefetch access prohibition mode. In this way, it is possible to change the setting of mode register 8 based on the state of the address actually accessed, and to automatically set whether or not to execute prefetch processing for each chip select space. it can.

In each of the above embodiments, the case where a DRAM is used as a memory has been described. However, the present invention is not limited to a DRAM as a memory. The present invention can be applied to storage elements typified by general semiconductor memories such as SDRAM and PBRAM, and the configuration in that case is the same as that of the present embodiment. Further, in the above embodiment, the data to be accessed has been described as being continuously stored in the same DRAM, but the memory may have an interleaved configuration. . In this case, it can be realized by setting the mode register 8 so that the execution and non-execution of the prefetch between the memory chips constituting the continuous addresses are the same. In the above embodiments, the chip select signal from the CPU 1 is used to identify whether prefetching is possible or not. However, depending on the system, the upper bits of the address accessed by the CPU may be used. Since the chip select signal is determined by the CPU, the input from the CPU 1 to the prefetch state management unit 5 may be only the address bus ADDR and the bus start signal BS—. In this case, the access determination unit 56 needs to perform processing for obtaining the chip selector space based on the address data from the address bus ADDR. Thus, the number of signal pins of CPU 1 can be reduced. However, a delay occurs due to the time for the address data output to the address bus ADDR to settle and the processing for obtaining the chip selector space from the address data.

Further, in the above-described embodiment, the unit of the area for controlling the prefetch matches the chip select space. For example, the mode register 8 of the prefetch state management unit 5 may be The address register that stores the boundary of the area is used.The address ADDR value accessed by the CPU 1 input to the prefetch state management unit 5 is used as the address of the area boundary stored in the mode register 8. By performing the comparison, it is possible to control the prefetch for each area of an arbitrary size. In this case, the mode is used to divide the memory into two areas. If register 1 is divided into three areas and the memory is divided into three areas, mode register 8 is required for each divided area, so that mode register 8 is divided into two. Since the number of comparisons with this value increases, the processing in the access determination unit 56 becomes complicated, and the number of registers increases, resulting in an increase in circuit scale.

In the present invention, a memory area for storing data that can be effectively prefetched and a memory area for storing data that is frequently accessed unnecessarily when prefetching is performed include: In the case where data that is placed in different chip select spaces but data that is effective for prefetching and data that is frequently accessed unnecessarily after prefetching are not classified are as follows: Create a program as follows.

First, at the time of program initialization processing, all the mode registers 8 are set in advance to a prefetch accessible mode. After that, when performing a process in which the data to be processed is data in which unnecessary access frequently occurs when prefetching is performed, immediately before performing the process, a chip indicating an address in which the corresponding data is stored. An instruction to set the mode register 8 corresponding to the select signal to the prefetch access disabled mode is described. Furthermore, when the processing of data that is frequently accessed when prefetching is completed is completed, the value of the mode register 8 that was previously set to the prefetch access prohibition mode is set to the prefetch access mode. Write the instruction to return to the end of the processing. This makes it possible to explicitly describe whether or not to execute prefetching in the program.

In the above embodiment, the memory controller 2 is provided independently of the CPU 1. However, the memory sequencer 4, which controls the prefetch in the memory controller 2, Prefetch state management unit 5, prefetch The etch buffer 6 and the selector 11 may be provided between the cache memory 20 and the main memory DRAM 7, and may be provided in the CPU 1 together with the cache memory 20. Conversely, the cache memory 20 may be provided externally to the CPU.

As described above, according to the present invention, it is possible to divide an area for storing programs and data and to control whether or not to prefetch each area. Therefore, in the data access, when the prefetch function is activated, the prefetch function is activated when the data stored in the area that stores data is accessed, and the prefetch access function is activated. If this is done, unnecessary data will be prefetched and memory access performance will be degraded.When accessing an area where data is stored, the prefetch function will be suppressed. The efficiency of memory access can be improved. Industrial applicability

As described above, the memory control device according to the present invention is useful as an efficient memory system by controlling the prefetch function in data access, and is useful for data processing. Suitable for memory control of equipment.

Claims

The scope of the claims

1. It is located between the processor and the memory, and has a prefetching means for prefetching and a storage means for storing the prefetch result when accessing the memory from the processor. In the memory controller,

The memory control device includes a prefetch management unit that determines whether to perform prefetching when the processor accesses the memory, and an address space of the memory is divided into a plurality of management areas. ,

The prefetch management means includes a register for controlling the prefetch for each of the management areas,

When the processor accesses the memory, based on the value of the register corresponding to the management area including the address to be accessed, whether or not to prefetch in the access, A memory control device characterized by determining the following.

2. The processor outputs a selection signal for selecting a storage element of the memory,

The address space of the memory is divided into the management area according to the selection signal,

2. The memory control device according to claim 1, wherein in access from a processor, a value of the register is determined based on the selection signal.

3. When the processor accesses the same management area a predetermined number of times or more, the prefetch management means pre-registers the register corresponding to the management area with respect to the management area. 2. The memory control according to claim 1, further comprising means for setting to perform fetching.

4. The processor outputs a selection signal for selecting a storage element of the memory,

The management area is a storage element forming a memory,

In an access from a processor, a value of the register is determined based on a storage element to be accessed.

The memory controller according to item 1.

5. When the predetermined number of consecutive accesses from the processor are performed to the same prefetch range, the prefetch management means includes a management including the prefetch range. 2. The memory control device according to claim 1, further comprising: means for setting the register corresponding to an area so as to prefetch the management area.

6. A programmable controller having an arithmetic processing unit and a memory, wherein when accessing the memory from the arithmetic processing unit, prefetch means for prefetching, and the prefetch unit In a programmable controller provided with storage means for storing a result of prefetching by the switching means, when the arithmetic processing unit accesses the memory, the prefetching means controls the prefetching. Equipped with prefetch management means to determine whether or not to perform

The prefetch management means includes a register for controlling prefetch for each management area of the memory in which an address space is divided into a plurality of management areas, and includes an address to be accessed. To determine whether to perform prefetching in the access based on the value of the register corresponding to the management area to be accessed.

A programmable controller.

7. Prefetches to read ahead when accessing memory from the processor Memory control processing in a memory control device having a function of performing a

When accessing the memory from the processor, a process of determining a management area to be accessed in the memory in which the address space is divided into a plurality of management areas;

A process of counting the number of accesses performed for each management area of the memory;

Processing for detecting that the processor has accessed the same management area by a predetermined number of times or more;

A process of setting a register value corresponding to the management area that has been accessed a predetermined number of times or more so as to perform prefetching when the management area is accessed.