WO2000077785A1

WO2000077785A1 - Reproduction system and integrated circuit

Info

Publication number: WO2000077785A1
Application number: PCT/JP1999/003165
Authority: WO
Inventors: Tatsuya Komatsu; Takashi Nara
Original assignee: Hitachi, Ltd.
Priority date: 1999-06-15
Filing date: 1999-06-15
Publication date: 2000-12-21

Abstract

A reproduction system such as a hard disk drive comprises a signal processing circuit for reproducing data by processing the signals obtained from a head. The signal processing circuit has three modes of operation, that is, stop mode where the disk drive means is at rest, normal mode where the disk drive means operates to reproduce data, and standby mode where the disk drive means operates but data is not reproduced. In the stop mode, the drive means and the signal processing circuit is shut off or supplied with zero volt; in the normal mode, the drive means and the signal processing circuit are supplied with normal power; and in the standby mode, the analog circuit in the signal processing circuit is supplied with power at voltage lower than normal.

Description

Description Media playback system and semiconductor integrated circuit

The present invention relates to a technology that is effective in reducing the power consumption of a reproduction system for a storage medium such as a magnetic disk, a magnetic tape, or an optical disk. This technology relates to technology that is effective when used in a hard disk control system that generates a write signal to be supplied to a head.

Background art

In response to the recent progress of the information society, recording devices for digitizing and recording various kinds of information and data are required to have higher speed and larger capacity. A hard disk drive is one of the recording devices that meet such demands.

For example, as shown in FIG. 9, a hard disk drive includes a write amplifier and a magnetic head that drive a magnetic head HD to generate a pulse current for writing binary digital data to a magnetic recording disk. A read / write execution unit 11 including a read amplifier that amplifies a data signal read via HD, a signal processing unit that performs collation of data read by the read / write execution unit 11 12.Format control unit that has the function of converting data into a format suitable for data exchange with external devices.13.Spindle drive that drives the disk rotation axis. SPM and magnetic head are retained. The voice coil motor that moves the arm (big-up) that controls the VCM The disk control unit that controls the disk rotation speed and the position of the head by controlling the VCM It is composed of a disk control unit 15 that connects to external devices such as a host computer 20 and controls the entire disk drive, etc., and is formed as a semiconductor integrated circuit on a separate semiconductor chip. Often. Of these, the signal processing unit 12 that performs verification of data read from the disk requires particularly high-speed signal processing because it affects the read / write speed of the disk, so amplifiers, filters, analog / digital conversion, etc. Signal integrated circuit (hereinafter referred to as an A / D converter) and a digital signal processing circuit that is optimally mounted with a digital signal processing circuit. Channel LSI).

By the way, the above-mentioned hard disk drive is composed of an LSI having an analog circuit built therein like a data channel LSI 12 and an LSI consisting only of a digital circuit like a disk control unit 15. The number of LSIs that operate at low voltages such as 3.3 V and 1.8 V is increasing. However, since only a single power supply such as 5 V is supplied from the personal computer to the hard disk drive according to the standard, if the power supply voltage needs to be changed by the LSI, a voltage regulation system is provided, and the hard disk drive is I had to deal with it by voltage conversion.

However, if a power supply IC such as a general-purpose switching regulator is used as such a voltage regulator, the number of components increases, making it difficult to reduce the size. It became clear that there was a problem of increased power consumption because the number of regular evenings had to be increased.

An object of the present invention is to reduce power consumption of a medium reproducing system such as a hard disk device.

Another object of the present invention is to reduce the number of components of a medium reproducing system such as a hard disk drive, and to make it possible to reduce the size and cost.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

To briefly explain the outline of the representative inventions disclosed in the present application, It is as follows.

That is, in a medium reproduction system such as a hard disk device, a signal processing circuit for processing a signal obtained from a head to reproduce data includes a pause state in which a driving unit for driving a medium is stopped, and a deactivation state in which the driving unit operates. A normal operation state for reproducing data overnight and a standby state in which the driving means operates but does not reproduce the data are provided. In the pause state, supply of power supply voltage to the driving means and the signal processing circuit is cut off. Alternatively, in the normal operation state, the original power supply voltage is supplied to the driving means and the signal processing circuit, and in the standby state, the analog circuit in the signal processing circuit has a level lower than the original power supply voltage. It was configured to supply a low power supply voltage.

According to the above-described means, for a circuit that does not need to be operated or whose output signal accuracy may be low depending on the operation state (mode), the power supply voltage supplied according to the operation state is cut off or reduced. Therefore, the total power consumption can be reduced.

The signal processing circuit is composed of one or more semiconductor integrated circuits, and any one of the semiconductor integrated circuits can generate a plurality of power supply voltages based on a single external power supply voltage. A power supply circuit including a voltage generation circuit and a voltage switching circuit capable of switching a voltage generated by the power supply voltage generation circuit is provided. This eliminates the need for a power supply IC such as a switching regulator and the like even if the number of required power supply voltages is large, thus reducing the number of parts and reducing the cost and size of a hard disk. The device can be realized.

Further, in a semiconductor integrated circuit including an analog circuit and a digital circuit, and including a voltage generation circuit for generating a substrate bias voltage for the digital circuit unit, the voltage generation circuit operates the substrate bias voltage for the digital circuit unit. It is configured to be switchable according to the state.

According to the above-described means, when the operation of the digital circuit is unnecessary or when the power supply voltage may be low, the threshold voltage of the MOSFET is set to an absolute value in order to reduce the leakage current in the MOSFET. So that the substrate bias voltage is higher Can be generated, so that the total power consumption can be reduced. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a hard disk control system as an example of a medium reproduction system according to the present invention and a block diagram showing an overall configuration example of a hard disk device using the same.

FIG. 2 is a block diagram showing one embodiment of a data channel LSI used in a hard disk control system,

FIG. 3 is a circuit diagram showing a specific example of a power supply circuit provided in the data channel LSI of the embodiment;

FIG. 4 is a circuit diagram showing a specific example of a DC—DC converter that constitutes a voltage regulator.

FIG. 5 is a circuit diagram showing a specific example of a variable gain amplifier provided in the data channel LSI of the embodiment;

FIG. 6 is an explanatory diagram showing a method for aligning a magnetic head using a read signal, FIG. 7 is a block diagram showing another embodiment of a hard disk control system to which the present invention is applied,

FIG. 8 is a block diagram showing an embodiment of a DVD control system to which the present invention is applied, and FIG. 9 is a block diagram showing a configuration example of a conventional hard disk device. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram showing a configuration example of a hard disk device as an example of a medium reproduction system effective by applying the present invention.

In FIG. 1, 100 is a recording medium such as a magnetic disk, 110 is a spindle motor for rotating the magnetic disk 100, and 120 is a write head and a read head. The magnetic head 130 is an actuating unit such as a voice coil motor for moving an arm having a magnetic head 120 at the tip. Reference numeral 210 denotes a motor driver for driving the above-mentioned spindle motor 110 and voice coil motor 130, which comprises a spindle motor driving circuit and a voice coil motor driving circuit. Reference numeral 220 denotes an amplifier for amplifying a current corresponding to a change in the magnetic field detected by the magnetic head 120 and transmitting a read signal to the data channel processor 230 or a data channel processor 230. A read 'write' amplifier that amplifies the write pulse signal from 0 and outputs the drive current of the magnetic head 120, and 240 is sent from the data channel processor 230 A hard disk controller that takes in the RDT and performs error correction processing, or performs error correction coding processing on the write data from the host and outputs it to the data channel processor 230. It is. The data channel processor 230 performs signal processing such as modulation / demodulation processing suitable for digital magnetic recording and waveform shaping in consideration of magnetic recording characteristics.

Reference numeral 250 denotes an interface controller for transferring and controlling data between the system and an external device, and the above-mentioned hard disk controller 240 represents an interface controller 250. Is connected to a host computer such as a microcomputer overnight on the PC. The microcontroller 260 controls the entire system as a whole and calculates the sector position etc. based on the address information supplied from the hard disk controller 240. This is a cache memory for a buffer that temporarily stores read data that has been read. Microcomputer 260 determines which operation mode is based on the signal from hard disk controller 240, and controls each part of the system according to the operation mode.

The motor driver 210 is composed of a spindle motor drive circuit and a voice coil motor drive circuit. The signal output from the micro-combination driver 260 keeps the relative speed of the head constant. The spindle motor drive circuit is servo-controlled, and the voice coil motor drive circuit is servo-controlled so that the center of the head coincides with the center of the track.

Above driver, driver 210, read 'write' amplifier 220, data channel A hard disk control system 200 is composed of a microprocessor 230, a hard disk controller 240, an in-system controller 250, a micro-computer controller 260, and a cache memory 270. The control system 200, the magnetic disk 100, The spindle motor 110, the magnetic head 120, and the voice coil motor 130 constitute a hard disk device as an example of a medium reproducing system.

Although not particularly limited, in this embodiment, the mode driver 210, read 'write' amplifier 220, data channel processor 230, hard disk 'controller 240, interface' controller 250, microcomputer 260, and cache memory 270 are each formed as an independent semiconductor integrated circuit on a semiconductor chip such as a single crystal silicon substrate.

FIG. 2 shows an embodiment of the data channel processor 230 constituting the hard disk control system shown in FIG.

In FIG. 2, reference numeral 401 denotes a variable gain amplifier that amplifies a lead signal input to the external terminals R nx and R ny as a differential signal from a read 'write' amplifier 220 connected to the magnetic head 120; 402 is an active filter that removes high-frequency noise from the amplified read signal and passes a signal in a desired band, and 403 converts the read signal (analog signal) into a digital signal (“1”, “0” lead pulse). An AD conversion circuit 404 for converting the signal, detects an amplitude of the read signal, forms a gain control signal for the variable gain amplifier 401, and amplifies the read signal to a signal having a predetermined amplitude.

Reference numeral 405 denotes a read PLL (phase “locked loop”) circuit for forming a read clock signal RCLK in phase with the read pulse based on the lead pulse, and 406 denotes an external clock generation circuit (crystal oscillation circuit). Circuit 407 is a write PLL circuit that forms a write clock signal W CLK based on SCCLK. 407 is a circuit that reproduces the read data RDT based on the read pulse or uses the write pulse signal W CLK based on the read pulse. The light clock formed by the PLL circuit 406 A digital circuit that takes in the externally input write data WD on the basis of the clock signal WCLK, forms a write pulse signal WP corresponding to "1" and "0", and outputs it to the outside. It is. The write data WD is supplied from the hard disk controller 240 and the like, and the write pulse signal WP is supplied to the read / write amplifier 220.

The variable gain amplifier 401 has a function of variably amplifying the amplitude of a read signal that has been degraded and attenuated by nonlinear electromagnetic characteristics of a magnetic head or the like to a predetermined amplitude level. The filter circuit 402 removes the aliasing noise caused by the A / D conversion operation in the subsequent A / D converter 403 in advance, and extracts the maximum useful information from the read signal. It has a function to switch the cut-off frequency at intervals of, for example, about 1 mm according to different data rates at the outer and outer peripheral portions.

The digitizing circuit 407 detects the amplitude level of the read signal, the data rate, etc., and supplies the variable gain amplifier 401 and the filter circuit 402 with the variable gain amplifier 401 and the filter circuit 402 so that the write data can be compared with the read signal. Control information and timing information such as the sampling clock of the / 0 converter 403 are generated and supplied to the automatic gain control circuit 404 and the read PLL circuit 405.Through these circuits, the gain variable amplifier 401 and the filter circuit 402, A / D converter 403 is feed-pack controlled.

For example, the frequency and phase of the sampling clock of the AZD converter 403 are adjusted by controlling the PLL circuit 405 based on the above-mentioned data rate detection signal. The 8/0 converter 403 corrects the sampling point deviation of the read signal waveform by adjusting the sampling clock timing.

Further, in FIG. 2, reference numeral 408 denotes a servo PLL circuit which forms an externally supplied clock signal OSCCL # or a servo clock signal SRVCL # based on a read pulse and outputs the same to the outside, and 409 denotes the above-mentioned PLL circuit. Variable gain amplifier 401, active filter 402, AD conversion circuit 403, automatic gain control circuit 404 A reference voltage generation circuit that generates a reference voltage Vref required for an analog circuit or a power supply circuit such as a power supply circuit. A voltage switching circuit for switching between the power supply voltage required for operation, such as 3.3 V, 2.5 V, and 1.8 V, and the voltage regulation that generates the substrate bias voltage VBB 41 1 and the generated voltage 412 It is a power supply circuit consisting of

Reference numeral 420 denotes a serial interface circuit for receiving commands and the like from the microcomputer 260 and for notifying the microcomputer 260 that data reading or writing has been completed, etc., and 430 denotes a data channel. This is a control circuit that controls the entire inside of the processor 230. Although not shown in FIG. 2, each of the PLL circuits 405, 406, and 408 includes a phase comparator, a charge pump circuit, a voltage-controlled oscillator, and the like.

As shown in FIG. 3, the reference voltage generation circuit 409 includes a constant voltage generation circuit 409a that generates a constant voltage such as 3.3 V and a resistance ladder circuit 409b. By dividing the generated reference voltage Vref with a resistor ladder circuit 409b, multiple voltages such as 3.3V, 2.5V, and 1.8V can be extracted as reference voltages. I have. The voltage switching circuit 412 is controlled by a signal indicating the operation mode supplied from the microcombiner 260 or a voltage switching control signal CSS formed based on the operation mode signal, and is generated by the reference voltage generation circuit 409. It is composed of selectors SEL 1 to SELn which select a reference voltage according to the operation mode from the reference voltages thus supplied and supply the selected voltage to the voltage regulator 41 1.

The voltage regulator 41 consists of DC-DC converters DCC1 to DCCn in a number corresponding to the number of ICs and circuit blocks to which the generated voltage is supplied. According to the reference voltage supplied from the switching circuit 412, the module driver 210, read 'write' amplifier 220, hard disk controller 240, interface controller '250, microcontroller view 260, cache memory 270 Other IC or LSI The power supply voltages Vc cl to Vc cn are generated and supplied to the outside. However, the selectors SEL 1 to SE Ln can select 0 V in addition to the reference voltage from the resistor ladder circuit 409, and when this 0 V is supplied to the DC-DC converters DC C1 to DCCn. , DC-DC Comparator DC C1 ~ DC Cn do not operate, that is, are configured so that no current flows.

FIG. 4 shows a specific example of the DC-DC converters DCC1 to DCCn constituting the voltage regulator 41 1.

In the DC-DC converter of this embodiment, the reference voltage Vref selected by the voltage switching circuit 412 is applied to the non-inverting input terminal of the operational amplifier AMP that functions as a non-inverting amplifier circuit, and the inverting input terminal of the operational amplifier AMP Is connected to the collector of a pnp bipolar transistor Tr whose base is connected to the output terminal Vo ut and is configured so that the output voltage divided by the resistance ratio of the resistors R 1 and R 2 is fed back. ing. As a result, a power supply voltage Vc ci (i = 1, 2,... N) of a predetermined level corresponding to the reference voltage Vref is generated and output, and even if the output current fluctuates, the output voltage is changed by the feedback loop. Is kept constant.

The resistors R 1 and R 2 for dividing the resistors and the trimming resistors may be provided in parallel so that the generated voltage can be finely adjusted. In addition, the DC-DC converter that constitutes the voltage regulator 41 is not limited to the circuit type shown in Fig. 4, and a switching regulator can be used instead of the DC-DC converter. It is.

FIG. 5 shows a specific example of the variable gain amplifier 401. The variable gain amplifier of this embodiment uses a multiplication type circuit composed of bipolar transistors, I 1 to 14 are constant current sources, Vin is an input signal to the amplifier, Vout is an output signal of the amplifier, VREF Is a reference voltage such as Vr e 回路 "supplied from the reference voltage generating circuit 409, VAGC is a gain control voltage supplied from the automatic gain control circuit 404, and VB is a bias voltage which provides a base operating point of an input transistor. In the variable gain amplifier 401, the gain increases when the gain control voltage VAGC is increased, and the VAGC is increased. When the gain is reduced, the amplification factor is reduced.On the other hand, when the power supply voltage Vcc decreases, the amplitude of the output signal Vout decreases, and the difference between Vcc and VREF and VB decreases. .

Next, using Table 1, the relationship between the types of the above operation modes and the level of the power supply voltage supplied to each of the above ICs or LSIs in each operation mode in the hard disk control system of the present embodiment will be described. explain.

table 1

The operation modes in the hard disk control system according to the present embodiment include a sleep mode, an idle mode, a rough servo mode, a just servo mode, a read mode, and a write mode.

In the sleep mode, the power supply voltage is supplied only to the interface controller 250 and the microcomputer 260 while the hard disk drive is turned on but waiting for a start command. Control is performed so that power supply voltage is not supplied to IC and SI. Therefore, both Svindormo 110 and Voicecoil Mo 130 are stopped. In evening Since the power supply voltage is supplied to the face controller 250 and the microcomputer 260, it can respond to an access request to the hard disk control system from an external personal computer at any time.

However, at this time, the microcomputer 260 operates temporarily because it is waiting for a command, but it does not need to operate at such a high speed, so the microcomputer 260 operates at 0.9 V, which is lower than during normal operation. Power supply voltage is supplied. In this mode, the power supply voltage (3.3 V) during normal operation is supplied to the power supply circuit (voltage regulation circuit and voltage switching circuit) 410 and the serial interface circuit 420 in the data channel processor 230. Then, when a signal indicating a mode change or the like is supplied from the microphone opening combination 260, it is possible to take measures such as switching of the power supply generated from the power supply circuit 410. Therefore, in Table 1, the data processor is a circuit excluding the power supply circuit 410 and the serial interface circuit 420, and the same applies to other modes.

Next, the idle mode is a standby mode in which the spinning motor 110 is rotating but the voice coil motor 130 is stopped and the magnetic head is waiting at a predetermined standby position such as inside a disk track. At this time, the power supply voltage for the cache memory 270 is cut off or set to 0 V, and the power supply voltage for normal operation is 1.8 V and 3.3 V for the micro combination 260 and the interface 250. V is supplied to each other, and the other data processor 230 and the read / write 'amplifier 220 and the motor dryino,' the 210 has a lower power supply voltage than the read / write operation (2.5 V, 3.3 V, 1.8 V) are supplied. At this time, regarding the data channel processor 230, the power supply voltage supply system is separated between the analog circuit section and the digital circuit section, and only the power supply voltage of the analog circuit section is supplied with a voltage lower than that in the normal operation. It may be. In recent years, the power supply voltage of digital circuits in particular has been reduced, and LSIs that operate with a power supply voltage of 1.8 V have been provided. Therefore, for the data channel processor 230 including the analog and digital circuits, the analog It is fully conceivable that the circuit is designed to operate at a power supply voltage of 3.3 V or 3.3 V, and the digital circuit operates at a power supply voltage of 3.3 V 1.8 V. In such a case, it may not be preferable to lower the power supply voltage for the digital circuit, and when the digital circuit is composed of the CM0S circuit, the power supply voltage is low because the power consumption is originally low. The benefits of lowering the voltage may not be so great, so only the power supply voltage of the analog circuit section needs to be lower than during normal operation.

In the just servo mode, the head is moved to a desired track position for reading or writing data. At this time, both the spindle motor 110 and the voice coil motor 130 have a precise servo mode. Since the motor control is required, the power supply voltage of 5 V higher than that in the idle mode is supplied to the motor driver 210. In the just servo mode, similarly to the read mode and the write mode, control is performed such that the center of the head is at the center of the target track by the waveform of the signal from the read / write amplifier 220.

In the hard disk control system of this embodiment, a sector servo system, which is one of the embedded servo systems, is employed as a head support system. In the sector servo method, as shown in Fig. 6 (A), between the sectors where the sync information (synchronization data) SYNC and the sector information SDT are recorded, the SBD is shifted slightly by the adjacent track. In this method, the servo data SBD is read during servo control to perform position control.

Specifically, when the center of the head HD matches the center of the target track as shown in Fig. 6 (A), the output waveform of the read amplifier becomes the center waveform as shown in Fig. 6 (C). The amplitude is the largest. On the other hand, when the center of the head HD is shifted inward or outward from the center of the target track, the output waveform of the read amplifier has the amplitude of the previous or subsequent waveform as shown in Fig. 6 (B) or (D). growing. Therefore, the head coil is controlled by controlling the voice coil mode so that the output waveform of the read amplifier has the largest amplitude of the middle waveform as shown in Fig. 6 (C). . In order to perform the servo control as described above, the read 'write' amplifier 220 and the analog circuit in the data channel processor 230 are also connected to the analog circuit in the idle mode. Supply voltage such as 3 V is supplied.

Further, the just servo mode is an operation performed based on a read or write request from an external personal computer or the like. Since read or write preparation is performed during head alignment in this mode, the · A power supply voltage such as 3.3 V, which is higher than 2.5 V in the idle mode, is also supplied to the controller 240. On the other hand, in this mode, the operation of the cache memory 270 is unnecessary, so the power supply voltage to the cache memory 270 is cut off or set to 0 V. However, in the just servo mode before reading, the power supply voltage may be supplied to the cache memory 270 in advance so that the operation can be performed immediately after the reading is started.

In the read mode, a higher power supply voltage (3.3 V) is supplied to the data channel processor 230 and the read / write amplifier 220 for the read operation than in the idle mode. Since the motor 110 and the voice coil motor 130 require precise servo control, the motor driver 210 is supplied with a higher 5 V power supply voltage than in the idle mode. At the same time, a power supply voltage (3.3 V) is supplied to the cache memory 270 in order to allow a buffer (temporary storage) of the data read out.

The power supply voltage supplied to each IC or LSI in the write mode is almost the same as in the read mode. That is, the power supply voltage (3.3 V) higher than that in the idle mode is supplied to the data channel processor 230 and the read / write amplifier 220, respectively. Since 0 and the voice coil module 130 require precise servo control, a power supply voltage of 5 V higher than that in the idle mode is supplied to the motor driver 210. However, since no data is read, that is, the data buffer is unnecessary, the power supply voltage to the cache memory 270 is cut off or set to 0 V.

The rough mode is used to read or write the next data. This is an operation state of waiting near the previous track. In this case, since the spindle motor 110 needs precise servo control, the motor driver 210 has the above idle mode. A higher 5 V supply voltage is supplied. However, since the head position does not require high precision, the read 'write' amplifier 220 and data channel processor 230 have a 2.5 V lower voltage than in the above read mode and write mode. The power supply voltage is supplied. Comparing the rough servo mode and the idle mode, the only difference is that the power supply voltage to the motor driver 210 is 5 V in the rough mode and 3.3 V in the idle mode. different.

As described above, the motor driver 210 includes a driver for the spindle motor and a driver for the voice coil motor. In the rough mode, at least the driver for the spindle motor is in the idle mode. It is only necessary to supply a higher 5 V power supply voltage. The power supply voltage supplied to the other ICs and LSIs is the same as in the idle mode, and the power supply voltage to the cache memory 270 is cut off or set to 0 V.

Read / write in rough servo mode.If a power supply voltage of 2.5 V, which is lower than that in read mode and write mode, is supplied to the amplifier 220 and the data processor 230, read will occur. In the variable gain amplifier 401 of the light amplifier 220 and the data channel processor 230, the output amplitude decreases, the waveform distortion of the output signal increases, and the conversion accuracy of the AD converter 403 decreases. You. Therefore, even if it is attempted to control the center of the head to be at the center of the target track based on the waveform of the signal from the read 'write' amplifier 220, the accuracy and response speed of the signal will be reduced. Although high head position control is not possible, rough servo control that positions the head near the target track can be performed.

Further, in this embodiment, a digital IC or LSI other than the interface controller 250 (hard disk controller 240, micro-computer controller 260, and cache memory 270) And de il channel · pro The substrate bias voltage VBB for the digital circuit section in the processor 230 is changed between the sleep mode and other modes. As a result, the power consumption of the digital IC (or LSI) including the P-type MOSFET and the N-type MOSFET and the digital circuit can be reduced in the sleeve mode.

For example, in the CMOS circuit constituting the microcomputer 260, a P-type MOS FET (P-MOS) substrate (or a well) is supplied with, for example, 0 V in the sleep mode, and in other modes, for example, 1.8V is applied. Similarly, for the N-type MOS SFET (N-MOS) substrate (or well) of the above CMOS circuit, for example, 1.0 V is applied in sleep mode, and 0 V is applied in other modes. Is done.

As a result, in the sleep mode, the threshold voltages of P-MOS and N-MOS become absolutely large, so that the leakage current of MOS FET can be reduced. On the other hand, in modes other than the sleep mode, the threshold voltages of P-MOS and N-MOS are relatively small in absolute value, so that the operation speed can be improved. .

Of course, the above 1.8V may be 3.3V or 2.5V. The above-mentioned 1.0V is not limited to this voltage value.

In the above embodiment, the voltage regulation circuit 41 1 and the voltage switching circuit 412 are provided in the data channel LSI 230 so as to supply a power supply voltage to another IC or LSI according to the operation mode. However, the LSI provided with the voltage regulator and the voltage switching circuit is not limited to the data channel LSI, but may be another IC or an LSI.

However, since the voltage regulation is a kind of analog circuit, it is desirable that the LSI provided with the voltage regulation circuit and the voltage switching circuit has an analog circuit in the chip in relation to the manufacturing process. As such an IC or LSI, in the system shown in FIG. 1, there are a motor driver 210 and a read / write amplifier 220 in addition to the data channel LSI. Of these, read 'write' amplifiers 22 Since 0 is provided on the side close to the head and is easily affected by noise, it is not a very desirable option to provide a voltage regulator for the lead, light, and amplifier 220.

Comparing the LSI for data channel 230 with the driver 210 for modem, the LS 1230 for data channel originally operates differently in various operation modes. Supplies a signal indicating the operation mode, and the generated voltage can be switched using the signal. Therefore, it can be said that it is most reasonable to provide a voltage regulator and a voltage switching circuit in the LSI 230 for the data channel as in the embodiment.

FIG. 7 shows another embodiment of the hard disk control system to which the present invention is applied. This embodiment is a combination of the data channel processor 230, the hard disk 'controller 240, the interface' controller 250, the microphone outlet controller 260, and the cache memory 27 in the first embodiment. 0 is formed on one semiconductor chip.

In this embodiment, a power supply voltage such as 1.8 V, 2.5 V, or 3.3 V based on a power supply voltage Vcc such as 5 V supplied from an external personal computer or the like in the common chip. A power supply circuit 410 including a voltage regulator 411 for generating V cci and a substrate bias voltage VBB and a voltage switching circuit 4 12 for switching the generated voltage is provided. The power supply circuit 410 is configured to switch the power supply voltage supplied to each circuit block according to each operation mode, for example, according to Table 1, as in the first embodiment. .

The voltage generated by the power supply circuit 410 is configured to be supplied to each circuit block in the chip via a power supply line formed on the chip. Also, a configuration is made so that the voltage generated by the power supply circuit 410 is supplied to the external driver 210 and read 'write' amplifier 220 via an external terminal. ing. Furthermore, it is also possible to adopt a configuration in which each circuit block in the chip is once externally supplied and supplied from a power supply terminal provided for each circuit block, regardless of the internal power supply wiring. As described above, in the LSI in which the micro-computer 260 as a digital circuit is formed on the same chip as the analog channel processor 230 as an analog circuit, as described in the above-described embodiment. Thus, even when the substrate bias potential of the microcombination 260 is switched between the sleeve mode and another mode, the formation portion of the microcombination 260 is connected to other circuit portions by a trench isolation or the like. By separating them, other circuits can be prevented from being affected.

FIG. 8 shows an embodiment of a digital video disk (DVD) control system capable of recording and reproducing according to the present invention. As shown in FIG. 8, in this embodiment, the read 'write' amplifier 220 and the data channel processor 230 are formed on one semiconductor chip. Further, a DVD controller 280 and an interface controller 250 corresponding to the hard disk controller 240 in the hard disk control system are also formed on another semiconductor chip. The driver 210, microcomputer 260, and cache memory 270 are formed on separate semiconductor chips as in the embodiment of FIG.

In this embodiment, the power supply voltage V such as 5 V supplied from an external personal computer or the like is supplied to the semiconductor chip on which the read / write amplifier 220 and the data channel processor 230 are formed. A voltage switch that switches between the power supply voltage V cci and the voltage that generates the substrate bias voltage VBB, such as 1.8 V, 2.5 V, and 3.3 V, based on the cc, and the generated voltage A power supply circuit 410 including the circuit 412 is provided. The power supply circuit 410 is configured to switch the power supply voltage supplied to each circuit block according to each operation mode according to, for example, Table 1 as in the first embodiment.

The voltage generated by the voltage regulator 4 1 1 is supplied to the read 'write' amplifier 220 and the data channel processor 230 in the chip via a separate power wiring formed on the chip. Is configured. Also, external driver 210, micro-computer 260, cache memory 270 The semiconductor chip on which the DVD controller 280 and the interface controller 250 are formed is configured so that the voltage generated by the power supply circuit 410 is supplied via external terminals. Have been.

As can be seen from Table 1, since the power supply voltage in each operation mode is the same for the read / write amplifier 220 and the data channel processor 230, the read / write · There is an advantage that the power supply voltage supply system is simplified by forming the amplifier 220 and the data channel processor 230 on the same chip.

In this DVD control system, as in the system shown in FIG. 7, the micro computer 260, the cache memory 270, the DVD controller 280, and the interface controller 250 are read. It can be configured as one LSI on the same semiconductor chip as the amplifier 220 and the data channel processor 230.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, in the above embodiment, the voltage switching circuit is provided between the reference voltage generating circuit and the voltage regulator to switch the generated voltage itself. However, the voltage switching circuit is provided at the subsequent stage of the voltage regulator. It is also possible to adopt a configuration in which a voltage to be supplied is selected and switched from among the generated voltages. Also, instead of providing DC-DC converters as many as the number of destination ICs or LSIs or blocks, DC-DC converters are used for ICs or LSIs or blocks whose power supply voltage is the same regardless of the mode. The voltage regulator and voltage switching circuit may be configured as independent ICs instead of being incorporated in any IC or LSI.

In addition, the power supply voltage of each IC or LSI can be controlled according to the operation mode, and the control of the digital circuit can be performed by stopping the supplied clock signal or changing the frequency to reduce power consumption. It is. Also, In the embodiment of FIG. 1, it has been described that the substrate bias voltage for the microcomputer 260 is controlled by the power supply circuit 410 provided on the data channel processor 230 side. When the device has a substrate bias generation circuit, the micro computer 260 itself may be configured to control the substrate bias voltage in accordance with the operation mode. Industrial applicability

The present invention is applicable not only to a hard disk drive but also to a floppy disk drive, a CD (compact disk) playback device, a DVD playback device, and other disk-type media playback systems or recording and playback systems, as well as VTRs (video tape recorders). It can be widely used in media playback systems in which digital circuits and analog circuits coexist, such as devices.

Claims

The scope of the claims

1. A head for reading data recorded on a medium, a driving means for driving the medium, and an analog circuit and a digital circuit. The driving means is controlled, and in response to reading data from the medium, What is claimed is: 1. A medium reproducing system comprising: a signal processing circuit that processes a signal obtained from a head and reproduces data, wherein the first state in which the driving unit is stopped and the driving unit operate to reproduce data. And a third state in which the driving means operates but the data is not reproduced. In the first state, supply of power supply voltage to the driving means and the signal processing circuit is interrupted or performed. 0 V. In the second state, the first power supply voltage is supplied to the driving means and the signal processing circuit. In the third state, the first power supply voltage is supplied to the analog circuit in the signal processing circuit. Is a medium reproducing system characterized in that a power supply voltage having an absolute value smaller than the first power supply voltage is supplied.

2. The medium is a disk-type medium, and the driving unit includes a first driving unit that rotationally drives the medium and a second driving unit that moves the head in a direction intersecting the rotation direction of the medium. The signal processing circuit has a function of processing a signal obtained from the head and controlling the second driving means to perform head positioning control, and the third state is a state of the medium. In the rough servo state, an idle state in which only rotational drive is performed, and a rough servo state in which the medium is driven to rotate and the head is relatively inaccurately controlled, the first and second drive means are in the rough servo state. On the other hand, the same power supply voltage as that in the second state is supplied, and in the idle state, a power supply voltage lower than that in the rough servo state is supplied to the first driving means. A contract characterized by Medium reproducing system according to claim 1.

3. A buffer memory for temporarily storing the reproduced data is provided, and the second state is controlled by controlling the first and second driving means to precisely position the head. The servo control includes a just servo state for performing the predetermined control, and a read state for reproducing the data from the signal obtained from the head while performing the precise positioning control of the head, and includes at least the first state and the second state. 3. The medium reproducing system according to claim 1, wherein a power supply voltage to the buffer memory is cut off or set to 0 V in three states.

4. The power supply voltage generation circuit which comprises one or more semiconductor integrated circuits in the signal processing circuit and can generate a plurality of power supply voltages based on a single external power supply voltage in any one of the semiconductor integrated circuits And a voltage switching circuit capable of switching a voltage generated by the power supply voltage generation circuit. The power supply circuit comprises: a power supply circuit for controlling the power supply voltage of the semiconductor integrated circuit other than the semiconductor integrated circuit provided with the power supply circuit. 4. The medium reproducing system according to claim 1, wherein the medium is controlled by:

5. The semiconductor integrated circuit provided with the power supply circuit is a semiconductor integrated circuit that performs signal processing such as modulation / demodulation processing suitable for digital magnetic recording and waveform shaping considering magnetic recording characteristics. The medium reproduction system according to claim 1, 2, 3, or 4.

6. A semiconductor integrated circuit in which an analog circuit other than a power supply circuit and a digital circuit are mixed, comprising: a voltage generating circuit for generating a substrate bias voltage for the digital circuit; A semiconductor integrated circuit characterized in that the voltage generating circuit is configured to be able to switch a substrate bias voltage for the digital circuit portion according to an operation state.

7. An analog circuit and a digital circuit other than the power supply circuit are mixed, and a signal obtained in response to the reading of data from the medium is processed to reproduce data and drive the medium. Semiconductor integrated circuit for signal processing for controlling driving means A voltage generating circuit for generating a substrate bias voltage for the digital circuit portion, wherein the voltage generating circuit is capable of switching the substrate bias voltage for the digital circuit portion in accordance with an operation state. A semiconductor integrated circuit characterized by being constituted.

Five

8. A first state in which the driving means is stopped, a second state in which the driving means operates to reproduce data, and a third state in which the driving means operates but does not reproduce the data, Only in the first state, the substrate bias voltage with respect to the above-mentioned digit circuit section cuts off the threshold voltage of the transistor constituting the above-mentioned digit circuit.

10 In the second state, the first power supply voltage is supplied to the digital circuit unit and the analog circuit unit, and in the third state, the digital circuit and the analog circuit 8. The semiconductor integrated circuit according to claim 7, wherein a power supply voltage lower than the first power supply voltage is supplied to the unit.

Fifteen

9. The semiconductor integrated circuit according to claim 6, further comprising a terminal for outputting the substrate bias voltage to the outside.

10. A head for reading data recorded on the medium, a drive means for driving the medium, and an analog circuit and a digital circuit. The drive means is controlled and the data from the medium is read out. What is claimed is: 1. A medium reproducing system comprising: a signal processing circuit that processes a signal obtained from the head in response to reading and reproduces data, wherein a first state in which the driving unit is stopped and the driving unit operates. And a third state in which the drive means operates but the data is not reproduced.25 The analog circuit controls the level of the power supply voltage in accordance with each state. The digital reproduction circuit is characterized in that the level of the substrate bias voltage is controlled according to each of the states.

11. In the second state, the first power supply voltage is supplied to the driving means, the analog circuit, and the digital circuit, respectively, and in the third state, the first circuit is supplied to the analog circuit in the signal processing circuit. In the first state, the supply of the power supply voltage to the drive means and the analog circuit is cut off or set to 0 V, and the substrate bias voltage to the digital circuit is supplied. 10. The medium reproducing system according to claim 10, wherein the medium reproducing system is configured such that the threshold voltage of the transistor constituting the digital circuit is set to a voltage that increases the absolute value.