WO2000072444A3 - Scannable flip flop circuit and method of operating an integrated circuit - Google Patents

Scannable flip flop circuit and method of operating an integrated circuit Download PDF

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Publication number
WO2000072444A3
WO2000072444A3 PCT/US2000/011348 US0011348W WO0072444A3 WO 2000072444 A3 WO2000072444 A3 WO 2000072444A3 US 0011348 W US0011348 W US 0011348W WO 0072444 A3 WO0072444 A3 WO 0072444A3
Authority
WO
WIPO (PCT)
Prior art keywords
latch
scannable
scannable flip
flip flop
clock input
Prior art date
Application number
PCT/US2000/011348
Other languages
French (fr)
Other versions
WO2000072444A9 (en
WO2000072444A2 (en
Inventor
Joseph A Hoffman
Joseph W Yoder
Original Assignee
Lockheed Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lockheed Corp filed Critical Lockheed Corp
Priority to AU63341/00A priority Critical patent/AU6334100A/en
Publication of WO2000072444A2 publication Critical patent/WO2000072444A2/en
Publication of WO2000072444A3 publication Critical patent/WO2000072444A3/en
Publication of WO2000072444A9 publication Critical patent/WO2000072444A9/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.
PCT/US2000/011348 1999-04-30 2000-04-28 Scannable flip flop circuit and method of operating an integrated circuit WO2000072444A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU63341/00A AU6334100A (en) 1999-04-30 2000-04-28 Method and apparatus for a scannable hybrid flip flop

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13212199P 1999-04-30 1999-04-30
US60/132,121 1999-04-30

Publications (3)

Publication Number Publication Date
WO2000072444A2 WO2000072444A2 (en) 2000-11-30
WO2000072444A3 true WO2000072444A3 (en) 2001-06-28
WO2000072444A9 WO2000072444A9 (en) 2001-07-26

Family

ID=22452577

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/011348 WO2000072444A2 (en) 1999-04-30 2000-04-28 Scannable flip flop circuit and method of operating an integrated circuit

Country Status (2)

Country Link
AU (1) AU6334100A (en)
WO (1) WO2000072444A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602210A (en) * 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4692634A (en) * 1986-04-28 1987-09-08 Advanced Micro Devices, Inc. Selectable multi-input CMOS data register
US5155432A (en) * 1987-10-07 1992-10-13 Xilinx, Inc. System for scan testing of logic circuit networks
EP0651566A1 (en) * 1993-10-29 1995-05-03 International Business Machines Corporation Programmable on-focal plane signal processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602210A (en) * 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4692634A (en) * 1986-04-28 1987-09-08 Advanced Micro Devices, Inc. Selectable multi-input CMOS data register
US5155432A (en) * 1987-10-07 1992-10-13 Xilinx, Inc. System for scan testing of logic circuit networks
EP0651566A1 (en) * 1993-10-29 1995-05-03 International Business Machines Corporation Programmable on-focal plane signal processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"HIGH-PERFORMANCE CMOS REGISTER", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 33, no. 3B, 1 August 1990 (1990-08-01), pages 363 - 366, XP000124389, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
WO2000072444A9 (en) 2001-07-26
AU6334100A (en) 2000-12-12
WO2000072444A2 (en) 2000-11-30

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