WO2000048243A1 - Flexible printed-circuit substrate, film carrier, semiconductor device on tape, semiconductor device, method of semiconductor manufacture, circuit susbstrate, and electronic device - Google Patents

Flexible printed-circuit substrate, film carrier, semiconductor device on tape, semiconductor device, method of semiconductor manufacture, circuit susbstrate, and electronic device Download PDF

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Publication number
WO2000048243A1
WO2000048243A1 PCT/JP2000/000552 JP0000552W WO0048243A1 WO 2000048243 A1 WO2000048243 A1 WO 2000048243A1 JP 0000552 W JP0000552 W JP 0000552W WO 0048243 A1 WO0048243 A1 WO 0048243A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
slit
wiring pattern
semiconductor device
wiring
Prior art date
Application number
PCT/JP2000/000552
Other languages
French (fr)
Japanese (ja)
Inventor
Masahiko Yanagisawa
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to KR1020007011228A priority Critical patent/KR100354203B1/en
Publication of WO2000048243A1 publication Critical patent/WO2000048243A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/0909—Preformed cutting or breaking line

Definitions

  • the present invention relates to a flexible wiring board, a film carrier, a tape-shaped semiconductor device, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
  • TAB Tepe Automated Bonding
  • the semiconductor chip is punched from the flexible wiring board to obtain a TCP (Tape Carrier Package), but errors may occur in the TCP punching position.
  • TCP Transmission Carrier Package
  • the wiring pattern had to be formed considerably inside the flexible wiring board from the punching position. In other words, it was necessary to secure a relatively large area including errors as the punched area, which had an effect on miniaturization and securing a wiring routing area.
  • the present invention has been made to solve this problem, and an object thereof is to provide a flexible wiring board, a film carrier, and a tape-shape capable of obtaining an accurate external shape and securing a maximum wiring area.
  • An object of the present invention is to provide a semiconductor device, a semiconductor device and a manufacturing method thereof, a circuit board, and an electronic device.
  • a flexible wiring substrate according to the present invention includes: a long base substrate; and a plurality of wiring patterns formed on the base substrate.
  • a slit is formed on a punched imaginary line including each wiring pattern inside,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape of punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed into a shape J5 by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • the slit may be formed only at a position forming an outer shape outside the wide portion.
  • a protective film may be provided on the wiring pattern and on the base substrate on a region avoiding the peripheral portion of the slit.
  • the protective film is provided so as to avoid the peripheral portion of the slit, the material for forming the protective film on the back surface of the base substrate via the slit is prevented.
  • a film carrier according to the present invention comprises: a base substrate; And a formed wiring pattern,
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • a slit is formed on an imaginary punched line including the wiring pattern inside,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern is the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • a tape-shaped semiconductor device includes a long base substrate, a plurality of wiring patterns formed on the base substrate, and a plurality of wiring patterns mounted on the base substrate.
  • a semiconductor chip electrically connected to a wiring pattern, wherein the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction.
  • the base substrate has a slit formed on a punched imaginary line including a wiring pattern inside thereof,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern can be increased. Then, the size of the semiconductor device can be reduced.
  • the semiconductor device according to the present invention is obtained by punching the base substrate of the tape-shaped semiconductor device by the punching virtual line.
  • the semiconductor device since the portion formed by the cut edge of the slit obtained by punching out the base substrate is located at an accurate position with respect to the wiring pattern, the semiconductor device is referred to based on the portion. Can handle.
  • the semiconductor device includes: a base substrate; a wiring pattern formed on the base substrate; and a semiconductor chip mounted on the base substrate and electrically connected to the wiring pattern.
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • a slit is formed on a punched imaginary line including a wiring pattern inside thereof,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. It is formed. That is, a part of the outer shape of the stamped member is formed in advance by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error has to be secured as a punching area, but in the present invention, a wide punching area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • the semiconductor device is electrically connected to the circuit board according to the present invention.
  • An electronic apparatus includes the above-described semiconductor device.
  • a method of manufacturing a semiconductor device comprising the steps of: mounting a semiconductor chip on a flexible base substrate on which a wiring pattern is formed and having a slit; Including the step of punching with a virtual line passing above,
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • the outer shape of the wide part is formed by the end of the slit left after punching.
  • an accurate outer shape can be obtained at the position where the most accurate punching is desired. That is, in the past, an accurate outer shape can be formed by a slit in a region where a relatively large region including an error had to be secured. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is increased. Then, the size of the semiconductor device can be reduced.
  • the method may include a step of providing a protective film on the wiring pattern and on the base substrate on a region avoiding a peripheral portion of the slit.
  • the protective film is provided so as to avoid the peripheral portion of the slit, the protective film is provided through the slit. As a result, the material forming the protective film on the back surface of the base substrate can be prevented from flowing around. (12) In this method of manufacturing a semiconductor device,
  • a plurality of the wiring patterns are formed on the base substrate;
  • the slit is formed corresponding to each wiring pattern
  • the base line may be punched by setting the virtual line in a region including each wiring pattern and passing through the corresponding slit.
  • a plurality of semiconductor devices can be simultaneously or continuously manufactured by electrically connecting the semiconductor chip to each of the plurality of wiring patterns.
  • FIG. 1 is a diagram showing a flexible wiring board according to an embodiment to which the present invention is applied.
  • FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
  • 3A and 3B are views showing a semiconductor device according to an embodiment to which the present invention is applied.
  • FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied.
  • FIG. 5 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment.
  • FIG. 6 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment.
  • 7A to 7C are diagrams showing a method for manufacturing a flexible wiring board according to the present embodiment.
  • FIG. 8A to 8C are diagrams illustrating the method for manufacturing the semiconductor device according to the present embodiment.
  • FIG. 9 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
  • FIG. 10 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
  • FIG. 1 is a diagram showing a flexible wiring board according to the present embodiment.
  • the flexible wiring substrate 1 includes a base substrate 10 and a plurality of wiring patterns 20 (only one is shown in FIG. 1).
  • the flexible wiring board 1 can be wound on a reel (not shown) and handled.
  • the flexible wiring substrate 1 is a TAB substrate (film carrier tape), but is not limited to this, and a COF (Chip On Film) substrate, It may be a substrate for COB (Chip On Board).
  • the base substrate 10 is a long (tape-shaped) base material, and is a support member for the wiring pattern 20.
  • the base substrate 10 has flexibility.
  • the base substrate 10 is often formed of polyimide resin, but other well-known materials can be used. If a plurality of sprocket holes 12 arranged in the length direction are formed at both ends in the width direction of the base substrate 10, the flexible wiring substrate 1 can be sent out by engaging a hook (not shown) with the sprocket holes 12. Can be.
  • one (a plurality of device holes) 14 are formed in the base substrate 10 for each wiring pattern 20.
  • the semiconductor chip can be bonded to an electrical connection (for example, an inner lead) with the semiconductor chip.
  • the shape of the device hole 14 is not particularly limited, and may be a size that can completely accommodate the semiconductor chip or a size that can partially accommodate the semiconductor chip.
  • a plurality of wiring patterns 20 are formed on the base substrate 10.
  • the wiring pattern 20 is bonded to the base board 10 via an adhesive (not shown).
  • the wiring pattern 20 is formed directly on the base board 10 without any adhesive.
  • the wiring patterns 20 may be formed side by side in the longitudinal direction of the long-sized pace substrate 10, may be formed side by side in the width direction, or may be formed in a matrix (in the longitudinal direction and in the longitudinal direction). (Arranged in the width direction). Each of the wiring patterns 20 often has the same shape, but may have different shapes. For example, a wiring pattern group formed by arranging n wiring patterns 20 having n kinds of shapes may be repeatedly formed. The plurality of wiring patterns 20 may be electrically connected by a plating lead (not shown) in order to perform electrical plating.
  • Each wiring pattern 20 has a plurality of wirings 22 and 24. Specifically, a plurality of wirings 22 are formed on one side (the upper side in FIG. 1) of the device hole 14 along the longitudinal direction of the base substrate 10, and on the other side (the lower side in FIG. 1). A plurality of wirings 24 are formed. Each of the wirings 22 and 24 includes an inner lead 26 and 28 formed at one end, and other ends 34 and 36.
  • the leads 26 and 28 project into the device hole 14.
  • the inner leads 26 and the inner leads 28 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10.
  • the inner leads 26 and 28 are electrical connections with the semiconductor chip 60 (see FIG. 2).
  • the ends 34, 36 extend on the opposite side to the inner leads 26, 28.
  • the ends 34 and the ends 36 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10.
  • the ends 34 and 36 may be formed so that at least one of the width and the pitch is wider than the inner leads 26 and 28.
  • the ends 34, 36 are electrically connected to other electrical components.
  • the end portion 36 of the wiring 24 is formed across the outer lead hole 38, and the portion inside the outer lead hole 38 of the end portion 36 is the outer lead. .
  • the connecting portion 30 between the inner lead 26 and the end portion 34 of the wiring 22 is formed to be inclined in a direction to increase the interval between the adjacent lead 26.
  • the wiring pattern 20 includes the wide portion 16 including the plurality of connection portions 30.
  • the wiring pattern 20 includes a narrow portion 18 that is narrower than the wide portion 16.
  • the narrow portion 18 shown in FIG. 1 is, for example, a portion extending linearly from the inner lead 26 to the connection portion 30.
  • the entire wiring 24 may also be referred to as a narrow portion.
  • the connection part 30 may be formed by drawing a straight line or may be formed by drawing a curve.
  • the connection part 32 between the inner lead 28 and the end part 36 of the wiring 24 shown in FIG. 1 may be formed in the same manner as the connection part 30.
  • a slit 40 is formed in the base substrate 10.
  • the slit 40 may be a cut or an elongated hole.
  • the slit 40 extends in the length direction of the base substrate 10, but may extend in the width direction, or may be formed obliquely with respect to the axis of the base substrate 10. You may. Further, the slit 40 may be formed in a straight line, may be bent, or may form a corner.
  • the slit 40 is formed on a virtual line 42 for punching.
  • the virtual line 42 includes at least a part of each wiring pattern 20 inside. At least one hole, for example, a device hole 14 or an outer lead hole 38 is formed inside the virtual line 42.
  • the imaginary line 42 is the contour of the outer shape of the final product except for the portion formed by the slit 40.
  • the end part becomes a part of the outer shape of the final product.
  • a part of the final product outer shape can be formed in advance.
  • the slit 40 can be formed at an accurate position with respect to the wiring pattern 20. Even if the position of the virtual 42 and the wiring pattern 20 is slightly shifted, the outer shape formed at the end of the slit 40 is formed at an accurate position with respect to the wiring pattern 20.
  • the virtual line 42 may be set at a position where at least one of the ends 34, 36 of the wirings 22, 24 is cut.
  • the inspection of the electrical characteristics may be performed using a portion outside the virtual line 42. Even if the end portions 34 and 36 are damaged as a result of the inspection of the electrical characteristics, this portion may be cut off and removed, so that there is no problem.
  • the slit 40 is formed in that portion, an accurate outer shape is secured. For example, the position of the outer shape outside the wide portion 16 of the wiring pattern 20 is often close to the wiring pattern 20. In this case, if the slit 40 is formed, The cutting of the wiring pattern 20 can be avoided.
  • the slit 40 may be formed only at a position outside the wide portion 16 and outside the wide portion 16, and may not be formed in other regions.
  • the slit 40 may not be formed at a position where there is room in the region, such as the outer shape of the narrow portion 18. By doing so, it is possible to minimize the formation of the slits 40 and prevent the strength of the base substrate 10 from decreasing.
  • the slit 40 is formed in the region where the slit 40 is formed.
  • the outer shape can be formed by the end of the slit 40.
  • the slit 240 shown in FIG. 9 is formed over the entire length of the wide portion 16. By doing so, the entire outer shape of the wide portion 16 can be formed by the end of the slit 240.
  • a plurality of slits 340 shorter than the length of the wide portion 16 may be formed in a row along the outer shape of the wide portion 16.
  • the width of the slit 40 may be equal to or greater than the sum of the thickness of the blade of the die for punching and the error during punching. In this case, even if an error is considered, the blade of the mold is located inside the slit 40, so that punching can always be performed in the slit 40.
  • a protective film 44 (see FIG. 2) may be provided on the wiring pattern 20.
  • the protective film 44 protects the wiring pattern 20 from oxidation and the like.
  • the protective film 44 may be formed of a resin such as a solder resist.
  • the protective film 44 is a part of the wiring pattern 20 excluding portions (inner leads, external terminals, outer leads, etc.) that are electrically connected to other components such as the semiconductor chip 60 (see FIG. 2).
  • the protective film 44 is provided not only on the wiring pattern 20 but also on the base substrate 10.
  • the peripheral portion of the slit 40 (specifically, the portion near the side where the opening of the slit 40 is formed) is formed on the base substrate 10.
  • a liquid material is provided. By doing so, it is possible to prevent the liquid material from going around the back surface of the base substrate 10 through the slit 40.
  • the formed protective film 44 is located at the periphery of the slit 40 (specifically, the opening of the slit 40). In the vicinity of the side forming the edge).
  • a positioning mark 50 is formed on the base substrate 10.
  • the positioning mark 50 can be formed of the same material as the wiring pattern 20 and may be formed simultaneously with the wiring pattern 20.
  • a positioning mark 50 is provided in a region offset from the wiring 22 in the width direction of the base substrate 10. By detecting the position of the positioning mark 5 °, the wiring pattern 20 may be positioned with respect to the terminal provided on another component connected thereto.
  • Holes 52, 54 for positioning are formed.
  • the holes 52 and 54 may be round holes or elongated holes extending in the width direction of the base substrate 10.
  • the film carrier according to the embodiment to which the present invention is applied has a shape obtained by cutting the flexible wiring board shown in FIG. 1 along a straight line (two-dot chain line indicated by reference numeral 56 in FIG. 1) in the width direction.
  • the film carrier is a piece of film cut from the above-described flexible wiring board.
  • the position where the flexible wiring substrate is cut is not particularly limited. In the example shown in FIG. 1, both sides of one wiring pattern 20 are set as the cutting positions, but both sides of a plurality of wiring patterns 20 may be set as the cutting positions.
  • FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
  • the tape-shaped semiconductor device has the above-described flexible wiring board 1 and a plurality of semiconductor chips 60 electrically connected to each wiring pattern 20.
  • the planar shape of the semiconductor chip 60 is generally rectangular, and may be rectangular or square.
  • a plurality of electrodes are formed on one surface of the semiconductor chip 60.
  • the electrodes are arranged along at least one side (often two or four) of the surface of the semiconductor chip. If the outer shape of the semiconductor chip 60 is rectangular, for example, The electrodes may be arranged in the longitudinal direction like a liquid crystal driving IC, or the electrodes may be arranged in the short direction.
  • the electrodes may be arranged at the end of the surface of the semiconductor chip 60 or may be arranged at the center.
  • Each electrode often includes a thin and flat pad made of aluminum or the like, and a bump formed thereon. If no bump is formed, only the pad will be the electrode.
  • a passivation film (not shown) is formed on the semiconductor chip avoiding at least a part of the electrode. Passhibeshiyon film, for example, S i 0 2, S i N, can be formed such as by Boriimi de resin.
  • the electrodes of the semiconductor chip 60 may be bonded to the inner leads 26 and 28 of the wiring pattern 20 via the device holes 14 by applying the TAB technology.
  • the semiconductor chip 60 may be face-down bonded.
  • the flexible wiring substrate is a substrate mounted with the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 and the base substrate facing each other, that is, a COF (Chip On Film). Good. .
  • the semiconductor chip 60 may be face-up bonded by applying wire bonding or the like.
  • the flexible wiring board is configured such that the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 faces the same direction as the mounting surface of the base substrate, and the semiconductor chip 60 is connected to the semiconductor chip 60 with a wire ( «) such as a gold wire. It may be a face-up type mounting substrate in which the electrodes of the chip 60 and the wiring patterns 20 are connected.
  • the tape-shaped semiconductor device may have a sealing portion 62.
  • the seal portion 62 seals at least an electrical connection portion (for example, the inner leads 26 and 28) between the electrode of the semiconductor chip 60 and the wiring pattern 20.
  • the seal portion 62 is often formed of resin.
  • the seal portion 62 preferably overlaps with the end of the protective film 44 (see FIG. 5). By doing so, it is possible to prevent the wiring pattern 20 from being exposed.
  • the sealing portion 62 may be provided by potting, It may be provided by one field.
  • the semiconductor device according to the present embodiment has a shape obtained by cutting the tape-shaped semiconductor device shown in FIG. 2 by a straight line extending in the width direction.
  • the tape-shaped semiconductor device may be cut on both sides of one wiring pattern 20 with a cutting jig 64 (such as a cutting tool or a punch).
  • the cutting position may be a position indicated by a two-dot chain line '56 in FIG.
  • 3A and 3B are views showing a semiconductor device having a shape obtained by punching out a base substrate of the tape-shaped semiconductor device shown in FIG.
  • the position where the base substrate 10 is punched is a virtual line 42 shown in FIG.
  • the punching of the base substrate 10 may be performed after the positioning bin is passed through the holes 52 and 54 and the base substrate 10 is positioned.
  • the distance (A dimension in the figure) between the end 66 formed by cutting the opening end of the slit 40 and the wiring pattern 20 is the same as that for forming the wiring pattern 20.
  • the range of error between the exposure and etching steps can be reduced. For this reason, the range of the wiring pattern 20 can be enlarged.
  • FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied.
  • a semiconductor device 72 to which the present invention is applied is electrically connected to a circuit board 70.
  • the circuit board 70 may be, for example, a liquid crystal panel.
  • the semiconductor device 72 is formed by punching a base substrate 10 of a tape-shaped semiconductor device with a contour surrounding the semiconductor chip 60.
  • the positioning between the circuit board 70 and the semiconductor device 72 may be performed by detecting the positioning mark 50 with a CCD camera or the like, calculating the coordinate position thereof, and transmitting this to the XY table.
  • the positional accuracy between the slit 40 and the wiring pattern 20 is high. For this reason, as shown in FIG. 3A, if the formed end portion 66 from which the slit 40 is cut is pressed against the positioning block 68 (the pressing force is F1, F2 in the figure). 2) Simple and highly accurate positioning is possible. Therefore, the connection between the semiconductor device 72 and the circuit board 70 can be achieved with high positioning accuracy and simplified equipment.
  • the base substrate 10 of the semiconductor device 72 may be provided to be bent.
  • the base substrate 10 may be bent around the end of the circuit substrate 70.
  • FIG. 8 shows a mobile phone 80 as an electronic apparatus having a semiconductor device to which the present invention is applied.
  • This mobile phone 80 also has a circuit board 70 (liquid crystal panel) to which the present invention is applied.
  • FIG. 6 shows a notebook personal computer 90 having a semiconductor device (not shown) to which the present invention is applied.
  • the electronic element (whether active element or passive element) is mounted on the flexible wiring board in the same manner as the semiconductor element, replacing the “semiconductor chip” with the “electronic element” of the present invention.
  • Electronic components manufactured using such electronic devices include, for example, optical devices, resistors, capacitors, coils, oscillators, filters, temperature sensors, summits, nos, squirrels, and volumes. Or a fuse.
  • FIGS. 7A to 8C are process explanatory diagrams showing a manufacturing process of a tab tape (an example of a flexible wiring board).
  • a film-like substrate (an example of a base substrate) 122 constituting the tab tape 120 is a polyimide having sprocket holes 122 formed at both ends in the width direction at equal intervals. Made of wood. By engaging with the sprocket, the tab table 120 can be transported in the longitudinal direction. Note that an adhesive is applied to one surface of the base material 122 in advance so that a copper foil described later can be attached to the base material 122.
  • a die for punching the base material 122 is provided in the middle of the transport path of the tab tape 120.
  • the mold has a device hole 1 2 4 inside the substrate 1 2 2 and a slit 1 26 and an outer lead hole 128.
  • FIG. 7B shows a form after forming these holes and slits 126 in the base material 122. Note that, as shown in FIG. 7B, the slit 126 has a form in which the longitudinal direction matches the longitudinal direction of the base material 122.
  • the slits 126 are arranged near the region where the sprocket holes 121 are formed in the substrate 122, that is, on both ends of the substrate 122.
  • a copper foil as a base of the wiring pattern is attached to the surface of the base material 122 (lamination step). After laminating the copper foil on the surface of the base material 122, exposure and etching are performed to form a wiring pattern, and wiring is performed in the wiring pattern area set on the surface of the base material 122. A pattern 130 is formed.
  • the position of the device hole 124 and the position of the slit 126 fluctuate in the subsequent process because the depth hole 124 and the slit 126 are formed at the same time as shown in FIG. never do. Therefore, the wiring pattern 130 can be brought close to the slit 126 up to an error range of the exposure and etching steps for forming the wiring pattern. Therefore, the wiring pattern 130 drawn out from the device hole 124 and set between the slits 126 can be set along the maximum outer shape between the slits 126.
  • FIG. 7C shows the positional relationship between the holes and the pattern region 130.
  • the semiconductor chip 13 2 is attached to the inner lead projecting from the device hole 124 as an extension of the wiring pattern 130. Align the terminals and join them.
  • FIG. 8A shows a state in which the semiconductor chip 132 is accommodated in the device hole 124. After the semiconductor chip 132 is placed in the device hole 124, a resin is applied to the inside of the edge of the device hole 124 (then, the resin is put into a drying step), and the semiconductor chip 132 is made of resin. By sealing, the inside of the device hole 124 is protected.
  • the base material 122 includes a depth hole 124, a slit 126, an outer lead hole 128, and a wiring pattern 130, and the punching which becomes the outer shape of the semiconductor device 134.
  • a virtual line 1 3 6 is set.
  • FIG. 8B shows a setting area of the imaginary punched line 1 36. As shown in FIG. 8B, the imaginary punched line 1 36 overlaps with the slit 1 26, and the slit 1 2 6 is cut by punching the substrate 1 2 2 along the imaginary punched line 1 36.
  • the shape of the slit 126 is partially present in a part of the outer shape of the semiconductor device 134.
  • FIG. 8C shows a semiconductor device 1336 punched from the base material 122.

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Abstract

A flexible printed-circuit substrate (1) includes a base tape (10) and a plurality of wiring patterns (20) formed on the base tape (10). Slits (40) are formed along phantom punching lines (42) o utside the wiring patterns (20) on the base tape (10). The slits (40) define the border of a wide band (16) where the wiring patterns (20) are formed.

Description

明 細 書 可撓性配線基板、 フィルムキャリア、 テープ状半導体装置、 半導体装置及びその 製造方法、 回路基板並びに電子機器  Description Flexible wiring board, film carrier, tape-shaped semiconductor device, semiconductor device and its manufacturing method, circuit board, and electronic equipment
[技術分野] [Technical field]
本発明は、 可撓性配線基板、 フィルムキャリア、 テープ状半導体装置、 半導体 装置及びその製造方法、 回路基板並びに電子機器に関する。  The present invention relates to a flexible wiring board, a film carrier, a tape-shaped semiconductor device, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
[背景技術] [Background technology]
従来、 可撓性配線基板に半導体チップを実装する T A B (Tape Automated Bonding) が知られている。 T A B方式によれば、 半導体チップを可撓性配線基 板に実装した後に、 可撓性配線基板から打ち抜かれて T C P (Tape Carrier Package) が得られるが、 T C Pの打ち抜き位置に誤差が生じることが多かった。 そのため、 正確な外形を得ることが難しく、 外形を基準とした取り扱いができな かった。 また、 可撓性配線基板には、 打ち抜き位置から、 かなり内側に配線パ夕 ーンを形成しなければならなかった。 つまり、 打ち抜き領域として、 誤差を含ま せた比較的広い領域を確保せねばならず、 小型化や配線の引き回し領域の確保に 影響を及ぼしていた。  Conventionally, TAB (Tape Automated Bonding) in which a semiconductor chip is mounted on a flexible wiring board is known. According to the TAB method, after mounting the semiconductor chip on the flexible wiring board, the semiconductor chip is punched from the flexible wiring board to obtain a TCP (Tape Carrier Package), but errors may occur in the TCP punching position. There were many. As a result, it was difficult to obtain an accurate outer shape, and handling based on the outer shape was not possible. Also, the wiring pattern had to be formed considerably inside the flexible wiring board from the punching position. In other words, it was necessary to secure a relatively large area including errors as the punched area, which had an effect on miniaturization and securing a wiring routing area.
[発明の開示] [Disclosure of the Invention]
本発明は、 この問題点を解決するためのものであり、 その目的は、 正確な外形 を得ることができ、 配線の引き回し領域を最大限確保できる可撓性配線基板、 フ イルムキャリア、 テープ状半導体装置、 半導体装置及びその製造方法、 回路基板 並びに電子機器を提供することにある。  The present invention has been made to solve this problem, and an object thereof is to provide a flexible wiring board, a film carrier, and a tape-shape capable of obtaining an accurate external shape and securing a maximum wiring area. An object of the present invention is to provide a semiconductor device, a semiconductor device and a manufacturing method thereof, a circuit board, and an electronic device.
( 1 ) 本発明に係る可撓性配線基板は、 長尺状のベース基板と、 前記ベース基 板上に形成された複数の配線パターンと、 を含み、  (1) A flexible wiring substrate according to the present invention includes: a long base substrate; and a plurality of wiring patterns formed on the base substrate.
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、 A wide portion formed in a wide area in a width direction of the base substrate; And a narrow portion formed in a narrow region in the width direction.
前記べ一ス基板には、 それそれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリッ卜が形成され、  On the base substrate, a slit is formed on a punched imaginary line including each wiring pattern inside,
前記スリッ トは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる。  The slit is formed at least at a position where the outer shape of the wide portion is formed in the shape of punching the base substrate.
本発明によれば、 打ち抜き仮想線上にスリットが形成されているので、 ベース 基板を打ち抜くと、 スリッ トの端部によって、 打ち抜かれた部材の外形の一部が 形 J5¾される。 すなわち、 予め、 スリットによって、 打ち抜かれる部材の外形の一 部が形成されている。 したがって、 配線パターンに対して正確な位置に外形の一 部を形成することができ、 その部分を基準とした取り扱いが可能になる。  According to the present invention, since the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed into a shape J5 by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
また、 打ち抜き位置と配線パターンとの間隔が最も狭くなる位置にスリッ卜が 形成されており、 スリット内で打ち抜きを行えばよいので、 スリッ卜に接近させ て配線パターンを形成することができる。 すなわち、 従来であれば、 誤差を含ま せた比較的広い領域を、 打ち抜き領域として確保せねばならなかったが、 本発明 では、 広い打ち抜き領域が不要になる。 したがって、 打ち抜き位置から、 かなり 内側に配線パターンを形成する必要がなくなり、 配線パターンの設計の自由度が 拡がる。 そして、 半導体装置の小型化が可能になる。  Further, the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
( 2 ) この可撓性配線基板において、  (2) In this flexible wiring board,
前記スリットは、 前記幅広部の外側の外形を形成する位置のみに形成されてい てもよい。  The slit may be formed only at a position forming an outer shape outside the wide portion.
これによれば、 比較的領域に余裕のある幅狭部の外側等にスリットを形成しな いので、 ベース基板の強度の低下を避けられる。  According to this, since no slit is formed outside the narrow portion having a relatively large area, a decrease in the strength of the base substrate can be avoided.
( 3 ) この可撓性配線基板において、  (3) In this flexible wiring board,
前記配線パターン上及び前記ベース基板上であって前記スリットの周辺部を避 けた領域上に、 保護膜が設けられていてもよい。  A protective film may be provided on the wiring pattern and on the base substrate on a region avoiding the peripheral portion of the slit.
これによれば、 保護膜がスリッ卜の周辺部を避けて設けられるので、 スリット を介してベース基板の裏面に保護膜を形成する材料が回り込まないようになる。  According to this, since the protective film is provided so as to avoid the peripheral portion of the slit, the material for forming the protective film on the back surface of the base substrate via the slit is prevented.
( 4 ) 本発明に係るフィルムキャリアは、 ベース基板と、 前記ベース基板上に 形成された配線パターンと、 を含み、 (4) A film carrier according to the present invention comprises: a base substrate; And a formed wiring pattern,
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
前記ベース基板には、 前記配線パターンを内側に含む打ち抜き仮想線上に、 ス リッ トが形成され、  On the base substrate, a slit is formed on an imaginary punched line including the wiring pattern inside,
前記スリットは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる。  The slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
本発明によれば、 打ち抜き仮想線上にスリットが形成されているので、 ベース 基板を打ち抜くと、 スリッ トの端部によって、 打ち抜かれた部材の外形の一部が 形成される。 すなわち、 予め、 スリットによって、 打ち抜かれる部材の外形の一 部が形成されている。 したがって、 配線パターンに対して正確な位置に外形の一 部を形成することができ、 その部分を基準とした取り扱いが可能になる。  According to the present invention, since the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
また、 打ち抜き位置と配線パターンとの間隔が最も狭くなる位置にスリツ卜が 形成されており、 スリット内で打ち抜きを行えばよいので、 スリットに接近させ て配線パターンを形成することができる。 すなわち、 従来であれば、 誤差を含ま せた比較的広い領域を、 打ち抜き領域として確保せねばならなかったが、 本発明 では、 広い打ち抜き領域が不要になる。 したがって、 打ち抜き位置から、 かなり 内側に配線パターンを形成する必要がなくなり、 配線パ夕ーンの設計の自由度が 拡がる。 そして、 半導体装置の小型化が可能になる。  Further, the slit is formed at the position where the interval between the punching position and the wiring pattern is the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
( 5 ) 本発明に係るテープ状半導体装置は、 長尺状のベース基板と、 前記べ一 ス基板上に形成された複数の配線パターンと、 前記ベース基板に搭載されて、 そ れそれの前記配線パターンに電気的に接続された半導体チップと、 を含み、 前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  (5) A tape-shaped semiconductor device according to the present invention includes a long base substrate, a plurality of wiring patterns formed on the base substrate, and a plurality of wiring patterns mounted on the base substrate. A semiconductor chip electrically connected to a wiring pattern, wherein the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction. And
前記ベース基板には、 それそれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリットが形成され、  The base substrate has a slit formed on a punched imaginary line including a wiring pattern inside thereof,
前記スリットは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる。 本発明によれば、 打ち抜き仮想線上にスリットが形成されているので、 ベース 基板を打ち抜くと、 スリットの端部によって、 打ち抜かれた部材の外形の一部が 形成される。 すなわち、 予め、 スリットによって、 打ち抜かれる部材の外形の一 部が形成されている。 したがって、 配線パターンに対して正確な位置に外形の一 部を形成することができ、 その部分を基準とした取り扱いが可能になる。 The slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate. According to the present invention, since the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
また、 打ち抜き位置と配線パターンとの間隔が最も狭くなる位置にスリッ卜が 形成されており、 スリット内で打ち抜きを行えばよいので、 スリットに接近させ て配線パターンを形成することができる。 すなわち、 従来であれば、 誤差を含ま せた比較的広い領域を、 打ち抜き領域として確保せねばならなかったが、 本発明 では、 広い打ち抜き領域が不要になる。 したがって、 打ち抜き位置から、 かなり 内側に配線パ夕―ンを形成する必要がなくなり、 配線ノ ^夕一ンの設計の自由度が 拡がる。 そして、 半導体装置の小型化が可能になる。  In addition, the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern can be increased. Then, the size of the semiconductor device can be reduced.
( 6 ) 本発明に係る半導体装置は、 テープ状半導体装置の前記べ一ス基板を、 前記打ち抜き仮想線で打ち抜いて得られたものである。  (6) The semiconductor device according to the present invention is obtained by punching the base substrate of the tape-shaped semiconductor device by the punching virtual line.
本発明によれば、 ベース基板が打ち抜かれて、 切断されたスリットの端部によ つて形成された部分は、 配線パターンに対して正確な位置にあるので、 その部分 を基準として、 半導体装置を取り扱うことができる。  According to the present invention, since the portion formed by the cut edge of the slit obtained by punching out the base substrate is located at an accurate position with respect to the wiring pattern, the semiconductor device is referred to based on the portion. Can handle.
( 7 ) 本発明に係る半導体装置は、 ベース基板と、 前記ベース基板上に形成さ れた配線パターンと、 前記ベース基板に搭載されて前記配線パターンに電気的に 接続された半導体チップと、 を含み、  (7) The semiconductor device according to the present invention includes: a base substrate; a wiring pattern formed on the base substrate; and a semiconductor chip mounted on the base substrate and electrically connected to the wiring pattern. Including
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
前記べ一ス基板には、 それそれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリツトが形成され、  On the base substrate, a slit is formed on a punched imaginary line including a wiring pattern inside thereof,
前記スリットは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる。  The slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
本発明によれば、 打ち抜き仮想線上にスリットが形成されているので、 ベース 基板を打ち抜くと、 スリットの端部によって、 打ち抜かれた部材の外形の一部が 形成される。 すなわち、 予め、 スリッ トによって、 打ち抜かれる部材の外形の一 部が形成されている。 したがって、 配線パターンに対して正確な位置に外形の一 部を形成することができ、 その部分を基準とした取り扱いが可能になる。 According to the present invention, since the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. It is formed. That is, a part of the outer shape of the stamped member is formed in advance by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
また、 打ち抜き位置と配線パターンとの間隔が最も狭くなる位置にスリッ卜が 形成されており、 スリット内で打ち抜きを行えばよいので、 スリットに接近させ て配線パターンを形成することができる。 すなわち、 従来であれば、 誤差を含ま せた比較的広い領域を、 打ち抜き領域として確保せねばならなかつ'たが、 本発明 では、 広い打ち抜き領域が不要になる。 したがって、 打ち抜き位置から、 かなり 内側に配線パターンを形成する必要がなくなり、 配線パターンの設計の自由度が 拡がる。 そして、 半導体装置の小型化が可能になる。  In addition, the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error has to be secured as a punching area, but in the present invention, a wide punching area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
( 8 ) 本発明に係る回路基板には、 上記半導体装置が電気的に接続されてなる。 (8) The semiconductor device is electrically connected to the circuit board according to the present invention.
( 9 ) 本発明に係る電子機器は、 上記半導体装置を有する。 (9) An electronic apparatus according to the present invention includes the above-described semiconductor device.
( 1 0 ) 本発明に係る半導体装置の製造方法は、 配線パターンが形成され、 か つ、 スリットが形成された可撓性のベース基板に半導体チップを実装し、 前記べ ース基板を前記スリット上を通る仮想線で打ち抜く工程を含み、  (10) A method of manufacturing a semiconductor device according to the present invention, comprising the steps of: mounting a semiconductor chip on a flexible base substrate on which a wiring pattern is formed and having a slit; Including the step of punching with a virtual line passing above,
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
打ち抜かれて残った前記スリットの端部によって、 前記幅広部の外側の外形を 形成する。  The outer shape of the wide part is formed by the end of the slit left after punching.
本発明によれば、 最も正確に打ち抜きたい位置に、 正確な外形を得られる。 す なわち、 従来であれば、 誤差を含ませた比較的広い領域を確保せねばならなかつ た領域に、 スリットによって正確な外形を形成することができる。 したがって、 打ち抜き位置から、 かなり内側に配線パターンを形成する必要がなくなり、 配線 パターンの設計の自由度が拡がる。 そして、 半導体装置の小型化が可能になる。  According to the present invention, an accurate outer shape can be obtained at the position where the most accurate punching is desired. That is, in the past, an accurate outer shape can be formed by a slit in a region where a relatively large region including an error had to be secured. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is increased. Then, the size of the semiconductor device can be reduced.
( 1 1 ) この半導体装置の製造方法において、  (11) In this method of manufacturing a semiconductor device,
前記配線パターン上及び前記ベース基板上であって前記スリッ 卜の周辺部を避 けた領域上に、 保護膜を設ける工程を含んでもよい。  The method may include a step of providing a protective film on the wiring pattern and on the base substrate on a region avoiding a peripheral portion of the slit.
これによれば、 保護膜をスリットの周辺部を避けて設けるので、 スリットを介 してベース基板の裏面に保護膜を形成する材料が回り込むことを避けられる。 ( 1 2 ) この半導体装置の製造方法において、 According to this, since the protective film is provided so as to avoid the peripheral portion of the slit, the protective film is provided through the slit. As a result, the material forming the protective film on the back surface of the base substrate can be prevented from flowing around. (12) In this method of manufacturing a semiconductor device,
前記ベース基板には、 複数の前記配線パ夕―ンが形成され、  A plurality of the wiring patterns are formed on the base substrate;
前記スリットは、 それそれの配線パターンごとに対応して形成され、  The slit is formed corresponding to each wiring pattern,
前記半導体チップを、 それぞれの配線パターンに電気的に接続し、  Electrically connecting the semiconductor chip to each wiring pattern,
それそれの配線パターンを含み、 かつ、 対応する前記スリットを通る領域に、 前記仮想線を設定して、 前記ベース基板を打ち抜いてもよい。  The base line may be punched by setting the virtual line in a region including each wiring pattern and passing through the corresponding slit.
これによれば、 複数の配線パターンのそれそれに半導体チップを電気的に接続 して、 複数の半導体装置を同時又は連続的に製造することができる。  According to this, a plurality of semiconductor devices can be simultaneously or continuously manufactured by electrically connecting the semiconductor chip to each of the plurality of wiring patterns.
[図面の簡単な説明] [Brief description of drawings]
図 1は、 本発明を適用した実施の形態に係る可撓性配線基板を示す図である。 図 2は、 本発明を適用した実施の形態に係るテープ状半導体装置の製造方法を 示す図である。  FIG. 1 is a diagram showing a flexible wiring board according to an embodiment to which the present invention is applied. FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
図 3 A及び図 3 Bは、 本発明を適用した実施の形態に係る半導体装置を示す図 である。  3A and 3B are views showing a semiconductor device according to an embodiment to which the present invention is applied.
図 4は、 本発明を適用した実施の形態に係る回路基板を示す図である。  FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied.
図 5は、 本実施の形態に係る半導体装置を有する電子機器を示す図である。 図 6は、 本実施の形態に係る半導体装置を有する電子機器を示す図である。 図 7 A〜図 7 Cは、 本実施の形態に係る可撓性配線基板の製造方法を示す図で ある。  FIG. 5 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment. FIG. 6 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment. 7A to 7C are diagrams showing a method for manufacturing a flexible wiring board according to the present embodiment.
図 8 A〜図 8 Cは、 本実施の形態に係る半導体装置の製造方法を示す図である。 図 9は、 本発明を適用した実施の形態に係る可撓性配線基板の変形例を示す図 である。  8A to 8C are diagrams illustrating the method for manufacturing the semiconductor device according to the present embodiment. FIG. 9 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
図 1 0は、 本発明を適用した実施の形態に係る可撓性配線基板の変形例を示す 図である。  FIG. 10 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
[発明を実施するための最良の形態] 以下、 本発明を適用した好適な実施の形態について図面を参照して説明するが、 本発明は以下の実施の形態に限定されるものではない。 [Best Mode for Carrying Out the Invention] Hereinafter, preferred embodiments to which the present invention is applied will be described with reference to the drawings, but the present invention is not limited to the following embodiments.
(可撓性配線基板）  (Flexible wiring board)
図 1は、 本実施の形態に係る可撓性配線基板を示す図である。 可撓性配線基板 1は、 ベース基板 1 0と、 複数の配線パターン 2 0 (図 1では 1つのみを示す） と、 を含む。 可撓性配線基板 1は、 図示しないリールに卷き取って取り扱うこと ができる。 可撓性配線基板 1は、 T A B技術が適用される場合には、 T A B用基 板 （フィルムキャリアテープ） であるが、 これに限定されるものではなく、 C O F (Chip On Film) 用基板や、 C O B (Chip On Board) 用基板であってもよ い。  FIG. 1 is a diagram showing a flexible wiring board according to the present embodiment. The flexible wiring substrate 1 includes a base substrate 10 and a plurality of wiring patterns 20 (only one is shown in FIG. 1). The flexible wiring board 1 can be wound on a reel (not shown) and handled. When the TAB technology is applied, the flexible wiring substrate 1 is a TAB substrate (film carrier tape), but is not limited to this, and a COF (Chip On Film) substrate, It may be a substrate for COB (Chip On Board).
ベース基板 1 0は、 長尺状 （テープ状） をなす基材であり、 配線パターン 2 0 の支持部材である。 ベース基板 1 0は、 フレキシブル性を有する。 ベース基板 1 0は、 ポリイミ ド樹脂で形成されることが多いがそれ以外の周知の材料を使用す ることができる。 ベース基板 1 0の幅方向の両端部に、 長さ方向に並ぶ複数のス プロケットホール 1 2を形成すれば、 これに図示しないッメを係合させて可撓性 配線基板 1を送り出すことができる。  The base substrate 10 is a long (tape-shaped) base material, and is a support member for the wiring pattern 20. The base substrate 10 has flexibility. The base substrate 10 is often formed of polyimide resin, but other well-known materials can be used. If a plurality of sprocket holes 12 arranged in the length direction are formed at both ends in the width direction of the base substrate 10, the flexible wiring substrate 1 can be sent out by engaging a hook (not shown) with the sprocket holes 12. Can be.
T A B技術が適用される場合には、 ベース基板 1 0には、 各配線パターン 2 0 について 1つの （全体では複数の） デバイスホール 1 4が形成されている。 デバ イスホール 1 4を介して、 半導体チップと、 それとの電気的接続部 （例えばイン ナーリード） とのボンディングを行うことができる。 デバイスホール 1 4の形状 は特に限定されなず、 半導体チップを完全に収容できる大きさであっても、 一部 を収容するだけの大きさであってもよい。  When the TAB technology is applied, one (a plurality of device holes) 14 are formed in the base substrate 10 for each wiring pattern 20. Via the device hole 14, the semiconductor chip can be bonded to an electrical connection (for example, an inner lead) with the semiconductor chip. The shape of the device hole 14 is not particularly limited, and may be a size that can completely accommodate the semiconductor chip or a size that can partially accommodate the semiconductor chip.
ベース基板 1 0には、 複数の配線パターン 2 0が形成されている。 3層基板の 可撓性配線基板 1では、 配線パターン 2 0が接着剤 （図示せず） を介してベース 基板 1 0に接着されている。 2層基板の可撓性配線基板 1では、 配線パターン 2 0が、 ベース基板 1 0上に直接形成され、 接着剤が介在しない。  A plurality of wiring patterns 20 are formed on the base substrate 10. In the flexible wiring board 1 of the three-layer board, the wiring pattern 20 is bonded to the base board 10 via an adhesive (not shown). In the flexible wiring board 1 of the two-layer board, the wiring pattern 20 is formed directly on the base board 10 without any adhesive.
配線パターン 2 0は、 長尺状のペース基板 1 0の長手方向に並んで形成されて もよいし、 幅方向に並んで形成されてもよいし、 マトリクス状に （長手方向及び 幅方向に並んで） 形成されてもよい。 それぞれの配線パターン 2 0は、 同一の形 状であることが多いが、 異なる形状であってもよい。 例えば、 n種類の形状をな す n個の配線パターン 2 0が並んで構成される配線パターングループを、 繰り返 して形成してもよい。 複数の配線パターン 2 0は、 電気メツキを行うために、 図 示しないメツキリードで電気的に接続されていてもよい。 The wiring patterns 20 may be formed side by side in the longitudinal direction of the long-sized pace substrate 10, may be formed side by side in the width direction, or may be formed in a matrix (in the longitudinal direction and in the longitudinal direction). (Arranged in the width direction). Each of the wiring patterns 20 often has the same shape, but may have different shapes. For example, a wiring pattern group formed by arranging n wiring patterns 20 having n kinds of shapes may be repeatedly formed. The plurality of wiring patterns 20 may be electrically connected by a plating lead (not shown) in order to perform electrical plating.
各配線パターン 2 0は、 複数の配線 2 2、 2 4を有する。 詳しくは、 ベース基 板 1 0の長手方向に沿って、 デバイスホール 1 4の一方の側 （図 1では上側） に 複数の配線 2 2が形成され、 他方の側 （図 1では下側） に複数の配線 2 4が形成 されている。 各配線 2 2、 2 4は、 一方の端部に形成されるインナ一リード 2 6、 2 8と、 他方の端部 3 4、 3 6と、 を含む。  Each wiring pattern 20 has a plurality of wirings 22 and 24. Specifically, a plurality of wirings 22 are formed on one side (the upper side in FIG. 1) of the device hole 14 along the longitudinal direction of the base substrate 10, and on the other side (the lower side in FIG. 1). A plurality of wirings 24 are formed. Each of the wirings 22 and 24 includes an inner lead 26 and 28 formed at one end, and other ends 34 and 36.
ィンナ一リード 2 6、 2 8は、 デバイスホール 1 4内に突出する。 ィンナ一リ ード 2 6同士及びインナーリード 2 8同士は、 平行に形成されており、 ベ一ス基 板 1 0の長手方向に延びて形成されていてもよい。 インナーリード 2 6、 2 8は、 半導体チップ 6 0 (図 2参照） との電気的接続部である。  The leads 26 and 28 project into the device hole 14. The inner leads 26 and the inner leads 28 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10. The inner leads 26 and 28 are electrical connections with the semiconductor chip 60 (see FIG. 2).
端部 3 4、 3 6は、 インナ一リード 2 6、 2 8とは反対側に延設されてなる。 端部 3 4同士及び端部 3 6同士は、 平行に形成されており、 ベース基板 1 0の長 手方向に延びて形成されていてもよい。 端部 3 4、 3 6は、 インナ一リード 2 6、 2 8よりも、 その幅及びピッチの少なくとも一方を広く形成してもよい。 端部 3 4、 3 6は、 他の電気部品と電気的に接続される。 図 1の例では、 配線 2 4の端 部 3 6は、 アウターリードホール 3 8をまたいで形成されており、 端部 3 6のう ち、 アウターリードホール 3 8内の部分はアウターリードである。  The ends 34, 36 extend on the opposite side to the inner leads 26, 28. The ends 34 and the ends 36 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10. The ends 34 and 36 may be formed so that at least one of the width and the pitch is wider than the inner leads 26 and 28. The ends 34, 36 are electrically connected to other electrical components. In the example of FIG. 1, the end portion 36 of the wiring 24 is formed across the outer lead hole 38, and the portion inside the outer lead hole 38 of the end portion 36 is the outer lead. .
配線 2 2の、 インナ一リード 2 6と端部 3 4との間の接続部 3 0は、 隣同士の ィンナ一リード 2 6の間隔を拡げる方向に傾斜して形成されている。 その結果、 配線パターン 2 0は、 複数の接続部 3 0を含んでなる幅広部 1 6を含む。 また、 配線パターン 2 0は、 幅広部 1 6よりも狭い幅狭部 1 8を含む。 図 1に示す幅狭 部 1 8は、 例えば、 インナーリード 2 6から接続部 3 0に至るまでの直線的に延 びる部分である。 図 1に示すように、 配線 2 4が幅広部を有しない場合には、 配 線 2 4の全体も、 幅狭部と称してもよい。 接続部 3 0は、 直線を描いて形成してもよいし、 曲線を描いて形成してもよい。 なお、 図 1に示す配線 2 4の、 インナーリード 2 8と端部 3 6との間の接続部 3 2も、 接続部 3 0と同様に形成してもよい。 The connecting portion 30 between the inner lead 26 and the end portion 34 of the wiring 22 is formed to be inclined in a direction to increase the interval between the adjacent lead 26. As a result, the wiring pattern 20 includes the wide portion 16 including the plurality of connection portions 30. The wiring pattern 20 includes a narrow portion 18 that is narrower than the wide portion 16. The narrow portion 18 shown in FIG. 1 is, for example, a portion extending linearly from the inner lead 26 to the connection portion 30. As shown in FIG. 1, when the wiring 24 does not have a wide portion, the entire wiring 24 may also be referred to as a narrow portion. The connection part 30 may be formed by drawing a straight line or may be formed by drawing a curve. In addition, the connection part 32 between the inner lead 28 and the end part 36 of the wiring 24 shown in FIG. 1 may be formed in the same manner as the connection part 30.
ベース基板 1 0には、 スリット 4 0が形成されている。 スリット 4 0は、 切れ 目であっても長穴であってもよい。 スリット 4 0は、 図 1では、 ベース基板 1 0 の長さ方向に延びて形成されているが、 幅方向に延びていてもよいし、 ベース基 板 1 0の軸に対して斜めに形成されてもよい。 さらに、 スリット 4 0は、 直線で 形成されていてもよいし、 屈曲していてもよいし、 角を形成していてもよい。 スリット 4 0は、 打ち抜きのための仮想線 4 2上に形成されている。 仮想線 4 2は、 各配線パターン 2 0の少なくとも一部を内側に含む。 なお、 仮想線 4 2の 内側には、 少なくとも 1つの穴、 例えば、 デバイスホール 1 4やアウターリード ホール 3 8が形成されている。  A slit 40 is formed in the base substrate 10. The slit 40 may be a cut or an elongated hole. In FIG. 1, the slit 40 extends in the length direction of the base substrate 10, but may extend in the width direction, or may be formed obliquely with respect to the axis of the base substrate 10. You may. Further, the slit 40 may be formed in a straight line, may be bent, or may form a corner. The slit 40 is formed on a virtual line 42 for punching. The virtual line 42 includes at least a part of each wiring pattern 20 inside. At least one hole, for example, a device hole 14 or an outer lead hole 38 is formed inside the virtual line 42.
仮想線 4 2は、 スリット 4 0によって形成される部分を除き、 最終的な製品の 外形の輪郭である。 スリット 4 0内では、 その端部が最終的な製品の外形の一部 となる。 本実施の形態では、 予めスリット 4 0を形成しておくので、 予め最終的 な製品の外形の一部を形成しておくことができる。 スリット 4 0は、 配線パター ン 2 0に対して、 正確な位置に形成することができる。 仮想 4 2の配線パ夕一 ン 2 0との位置が多少ずれても、 スリット 4 0の端部で形成される外形は、 配線 パターン 2 0に対して正確な位置で形成される。  The imaginary line 42 is the contour of the outer shape of the final product except for the portion formed by the slit 40. In the slit 40, the end part becomes a part of the outer shape of the final product. In the present embodiment, since the slits 40 are formed in advance, a part of the final product outer shape can be formed in advance. The slit 40 can be formed at an accurate position with respect to the wiring pattern 20. Even if the position of the virtual 42 and the wiring pattern 20 is slightly shifted, the outer shape formed at the end of the slit 40 is formed at an accurate position with respect to the wiring pattern 20.
なお、 図 1に示すように、 仮想線 4 2を、 配線 2 2、 2 4の端部 3 4、 3 6の 少なくとも一方を切断する位置に設定してもよい。 この場合、 仮想線 4 2の外側 の部分を利用して電気特性の検査を行ってもよい。 電気特性の検査の結果、 端部 3 4、 3 6に傷が付いても、 この部分は切断して除去される部分であるから差し 支えない。  As shown in FIG. 1, the virtual line 42 may be set at a position where at least one of the ends 34, 36 of the wirings 22, 24 is cut. In this case, the inspection of the electrical characteristics may be performed using a portion outside the virtual line 42. Even if the end portions 34 and 36 are damaged as a result of the inspection of the electrical characteristics, this portion may be cut off and removed, so that there is no problem.
本実施の形態では、 打ち抜きのための仮想線 4 2を、 配線パターン 2 0に接近 させても、 その部分にスリッ ト 4 0が形成されていれば、 正確な外形が確保され る。 例えば、 配線パターン 2 0の幅広部 1 6の外側の外形となる位置は、 配線パ ターン 2 0に接近していることが多いが、 この場合にスリット 4 0を形成すれば 配線パターン 2 0の切断を避けられる。 In the present embodiment, even if the virtual line 42 for punching is brought close to the wiring pattern 20, if the slit 40 is formed in that portion, an accurate outer shape is secured. For example, the position of the outer shape outside the wide portion 16 of the wiring pattern 20 is often close to the wiring pattern 20. In this case, if the slit 40 is formed, The cutting of the wiring pattern 20 can be avoided.
スリット 4 0は、 幅広部 1 6の外側の外形となる位置のみに形成し、 それ以外 の領域には形成しないようにしてもよい。 例えば、 幅狭部 1 8の外側の外形のよ うに、 領域に余裕がある位置には、 スリット 4 0を形成しないようにしてもよい。 そうすることで、 スリット 4 0の形成を最小限に抑えて、'ベース基板 1 0の強度 の低下を防止することができる。  The slit 40 may be formed only at a position outside the wide portion 16 and outside the wide portion 16, and may not be formed in other regions. For example, the slit 40 may not be formed at a position where there is room in the region, such as the outer shape of the narrow portion 18. By doing so, it is possible to minimize the formation of the slits 40 and prevent the strength of the base substrate 10 from decreasing.
スリット 4 0は、 図 1に示すように、 幅広部 1 6の長さ （ペース基板 1 0の長 手方向の長さ） よりも短く形成されていても、 スリット 4 0が形成された領域に 関する限り、 スリット 4 0の端部によって外形を形成することができる。 また、 図 9に示すスリット 2 4 0は、 幅広部 1 6の全長にわたって形成されている。 こ うすることで、 幅広部 1 6の外側の外形の全部を、 スリット 2 4 0の端部によつ て形成することができる。 あるいは、 図 1 0に示すように、 幅広部 1 6の外側形 状に沿って、 幅広部 1 6の長さよりも短い複数のスリット 3 4 0を一列に形成し てもよい。  As shown in FIG. 1, even though the slit 40 is formed to be shorter than the length of the wide portion 16 (the length in the longitudinal direction of the pace substrate 10), the slit 40 is formed in the region where the slit 40 is formed. As far as it is concerned, the outer shape can be formed by the end of the slit 40. Further, the slit 240 shown in FIG. 9 is formed over the entire length of the wide portion 16. By doing so, the entire outer shape of the wide portion 16 can be formed by the end of the slit 240. Alternatively, as shown in FIG. 10, a plurality of slits 340 shorter than the length of the wide portion 16 may be formed in a row along the outer shape of the wide portion 16.
スリット 4 0の幅は、 打ち抜きを行う金型の刃の厚みと、 打ち抜き時の誤差と、 の合計以上であってもよい。 この場合、 誤差を考慮しても、 金型の刃がスリット 4 0の内側に位置するので、 常にスリット 4 0内で打ち抜きを行うことができる。 配線パターン 2 0上には、 保護膜 4 4 (図 2参照） を設けてもよい。 保護膜 4 4は、 配線パターン 2 0を酸化等から保護する。 例えば、 ソルダレジスト等の樹 脂で保護膜 4 4を形成してもよい。 保護膜 4 4は、 配線パターン 2 0のうち、 半 導体チップ 6 0 (図 2参照） 等の他の部品と電気的に接続される部分 （インナ一 リード、 外部端子、 アウターリード等） を除いた部分上を覆って設ける。 保護膜 4 4は、 配線パターン 2 0上のみならず、 ベース基板 1 0上にも設けられる。 保 護膜 4 4を、 樹脂等の液状材料から形成する場合には、 ベース基板 1 0上で、 ス リット 4 0の周辺部 （詳しくはスリット 4 0の開口を形成する辺付近の部分） を 避けて、 液状材料を設けることが好ましい。 そうする；とで、 スリット 4 0を介 して、 液状材料がベース基板 1 0の裏面に回り込むことを防止できる。 その結果 形成された保護膜 4 4は、 スリット 4 0の周辺部 （詳しくはスリット 4 0の開口 を形成する辺付近の部分） を避けて設けられる。 The width of the slit 40 may be equal to or greater than the sum of the thickness of the blade of the die for punching and the error during punching. In this case, even if an error is considered, the blade of the mold is located inside the slit 40, so that punching can always be performed in the slit 40. A protective film 44 (see FIG. 2) may be provided on the wiring pattern 20. The protective film 44 protects the wiring pattern 20 from oxidation and the like. For example, the protective film 44 may be formed of a resin such as a solder resist. The protective film 44 is a part of the wiring pattern 20 excluding portions (inner leads, external terminals, outer leads, etc.) that are electrically connected to other components such as the semiconductor chip 60 (see FIG. 2). Provided over the part that was cut. The protective film 44 is provided not only on the wiring pattern 20 but also on the base substrate 10. When the protective film 44 is formed from a liquid material such as a resin, the peripheral portion of the slit 40 (specifically, the portion near the side where the opening of the slit 40 is formed) is formed on the base substrate 10. Preferably, a liquid material is provided. By doing so, it is possible to prevent the liquid material from going around the back surface of the base substrate 10 through the slit 40. As a result, the formed protective film 44 is located at the periphery of the slit 40 (specifically, the opening of the slit 40). In the vicinity of the side forming the edge).
ベース基板 1 0には、 位置決めマーク 5 0が形成されている。 位置決めマーク 5 0は、 配線パターン 2 0と同じ材料で形成することができ、 配線パターン 2 0 と同時に形成してもよい。 例えば、 配線 2 2のからベース基板 1 0の幅方向にォ フセットした領域に、 位置決めマーク 5 0を設ける。 位置決めマーク 5◦の位置 を検出することで配線パターン 2 0と、 これに接続される他の部品に設けられた 端子との位置決めを行ってもよい。  A positioning mark 50 is formed on the base substrate 10. The positioning mark 50 can be formed of the same material as the wiring pattern 20 and may be formed simultaneously with the wiring pattern 20. For example, a positioning mark 50 is provided in a region offset from the wiring 22 in the width direction of the base substrate 10. By detecting the position of the positioning mark 5 °, the wiring pattern 20 may be positioned with respect to the terminal provided on another component connected thereto.
また、 ベース基板 1 0には、 例えば、 デバイスホール 1 4の両側、 すなわちデ バイスホール 1 4からベース基板 1 0の幅方向にオフセットした領域には、 ベ一 ス基板 1 0の外形を打ち抜く際に用いるための位置決め用の穴 5 2、 5 4が形成 されている。 穴 5 2、 5 4は、 丸穴や、 ベース基板 1 0の幅方向に延長された長 穴であってもよい。  Also, for example, when the outer shape of the base substrate 10 is punched on both sides of the device hole 14, that is, in a region offset from the device hole 14 in the width direction of the base substrate 10. Holes 52, 54 for positioning are formed. The holes 52 and 54 may be round holes or elongated holes extending in the width direction of the base substrate 10.
(フィルムキヤリア）  (Film Carrier)
本発明を適用した実施の形態に係るフイルムキヤリァは、 図 1に示す可撓性配 線基板を、 幅方向に示す直線 （図 1に符号 5 6で示す二点鎖線） で切断した形状 をなす。 例えば、 フィルムキャリアは、 上述した可撓性配線基板から切断された 個片のフィルムである。 なお、 可撓性配線基板を切断する位置は特に限定されな い。 図 1に示す例では、 1つの配線パターン 2 0の両側を切断位置としたが、 複 数の配線パターン 2 0の両側を切断位置としてもよい。  The film carrier according to the embodiment to which the present invention is applied has a shape obtained by cutting the flexible wiring board shown in FIG. 1 along a straight line (two-dot chain line indicated by reference numeral 56 in FIG. 1) in the width direction. Eggplant For example, the film carrier is a piece of film cut from the above-described flexible wiring board. The position where the flexible wiring substrate is cut is not particularly limited. In the example shown in FIG. 1, both sides of one wiring pattern 20 are set as the cutting positions, but both sides of a plurality of wiring patterns 20 may be set as the cutting positions.
(テープ状半導体装置）  (Tape semiconductor device)
図 2は、 本発明を適用した実施の形態に係るテープ状半導体装置の製造方法を 説明する図である。  FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
テープ状半導体装置は、 上述した可撓性配線基板 1と、 各配線パターン 2 0に 電気的に接続された複数の半導体チップ 6 0と、 を有する。  The tape-shaped semiconductor device has the above-described flexible wiring board 1 and a plurality of semiconductor chips 60 electrically connected to each wiring pattern 20.
半導体チップ 6 0の平面形状は一般的には矩形であり、 長方形であっても正方 形であってもよい。 半導体チップ 6 0の一方の面に、 複数の電極が形成されてい る。 電極は、 半導体チップの面の少なくとも 1辺 （多くの場合、 2辺又は 4辺） に沿って並んでいる。 半導体チップ 6 0の外形が長方形である場合には、 例えば 液晶駆動用 I Cのように長手方向に電極が配列されてもよいし、 短手方向に電極 が配列されてもよい。 また、 電極は、 半導体チップ 6 0の面の端部に並んでいる 場合と、 中央部に並んでいる場合がある。 各電極は、 アルミニウムなどで薄く平 らに形成されたパッドと、 その上に形成されたバンプと、 からなることが多い。 バンプが形成されない場合は、 パッドのみが電極となる。 電極の少なくとも一部 を避けて半導体チヅプには、 パッシベ一シヨン膜 （図示しない） が形成されてい る。 パッシベーシヨン膜は、 例えば、 S i 02、 S i N、 ボリイミ ド樹脂などで 形成することができる。 The planar shape of the semiconductor chip 60 is generally rectangular, and may be rectangular or square. A plurality of electrodes are formed on one surface of the semiconductor chip 60. The electrodes are arranged along at least one side (often two or four) of the surface of the semiconductor chip. If the outer shape of the semiconductor chip 60 is rectangular, for example, The electrodes may be arranged in the longitudinal direction like a liquid crystal driving IC, or the electrodes may be arranged in the short direction. The electrodes may be arranged at the end of the surface of the semiconductor chip 60 or may be arranged at the center. Each electrode often includes a thin and flat pad made of aluminum or the like, and a bump formed thereon. If no bump is formed, only the pad will be the electrode. A passivation film (not shown) is formed on the semiconductor chip avoiding at least a part of the electrode. Passhibeshiyon film, for example, S i 0 2, S i N, can be formed such as by Boriimi de resin.
半導体チップ 6 0の電極は、 T A B技術を適用して、 デバイスホール 1 4を介 して、 配線パターン 2 0のィンナ一リード 2 6、 2 8にボンディングしてもよい。 あるいは、 デバイスホール 1 4が形成されない可撓性配線基板を使用した場合 には、 半導体チップ 6 0をフェースダウンボンディングしてもよい。 その場合、 可撓性配線基板は、 半導体チップ 6 0の能動面 （電極が形成された面） とベース 基板とが対向した状態で実装される基板、 すなわち C O F (Chip On Film) で あってもよい。 .  The electrodes of the semiconductor chip 60 may be bonded to the inner leads 26 and 28 of the wiring pattern 20 via the device holes 14 by applying the TAB technology. Alternatively, when a flexible wiring board in which the device hole 14 is not formed is used, the semiconductor chip 60 may be face-down bonded. In this case, the flexible wiring substrate is a substrate mounted with the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 and the base substrate facing each other, that is, a COF (Chip On Film). Good. .
ある は、 ワイヤボンディングなどを適用して、 半導体チップ 6 0をフェース アップボンディングしてもよい。 その場合、 可撓性配線基板は、 半導体チップ 6 0の能動面 （電極が形成された面） がベース基板の搭載面と同じ方向を向いて、 例えば金線などのワイヤ （«) にて半導体チップ 6 0の電極と配線パターン 2 0とが接続されるフエ一スァヅプ型の実装基板であってもよい。  Alternatively, the semiconductor chip 60 may be face-up bonded by applying wire bonding or the like. In this case, the flexible wiring board is configured such that the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 faces the same direction as the mounting surface of the base substrate, and the semiconductor chip 60 is connected to the semiconductor chip 60 with a wire («) such as a gold wire. It may be a face-up type mounting substrate in which the electrodes of the chip 60 and the wiring patterns 20 are connected.
テープ状半導体装置は、 シール部 6 2を有してもよい。 シール部 6 2は、 少な くとも半導体チップ 6 0の電極と配線パターン 2 0との電気的接続部 （例えばィ ンナ一リード 2 6、 2 8 ) を封止するものである。 シール部 6 2は、 樹脂で形成 されることが多い。  The tape-shaped semiconductor device may have a sealing portion 62. The seal portion 62 seals at least an electrical connection portion (for example, the inner leads 26 and 28) between the electrode of the semiconductor chip 60 and the wiring pattern 20. The seal portion 62 is often formed of resin.
また、 配線パターン 2 0における保護膜 4 4によって覆われる部分と覆われな い部分との境界では、 シール部 6 2は、 保護膜 4 4の端部と重複することが好ま しい （図 5参照）。 こうすることで、 配線パターン 2 0が露出することを防止で きる。 シール部 6 2は、 ポッティングによって設けてもよいし、 トランスファモ 一ルドによって設けてもよい。 In addition, at the boundary between the portion covered by the protective film 44 and the portion not covered by the protective film 44 in the wiring pattern 20, the seal portion 62 preferably overlaps with the end of the protective film 44 (see FIG. 5). ). By doing so, it is possible to prevent the wiring pattern 20 from being exposed. The sealing portion 62 may be provided by potting, It may be provided by one field.
本実施の形態に係る半導体装置は、 図 2に示すテープ状半導体装置を、 幅方向 に延びる直線で切断した形状をなす。 例えば、 図 2に示すように、 切断ジグ 6 4 (カツ夕やパンチ等） で、 1つの配線パターン 2 0の両側で、 テープ状半導体装 置を切断してもよい。 その切断位置は、 図 1に二点鎖線' 5 6で示す位置であって もよい。  The semiconductor device according to the present embodiment has a shape obtained by cutting the tape-shaped semiconductor device shown in FIG. 2 by a straight line extending in the width direction. For example, as shown in FIG. 2, the tape-shaped semiconductor device may be cut on both sides of one wiring pattern 20 with a cutting jig 64 (such as a cutting tool or a punch). The cutting position may be a position indicated by a two-dot chain line '56 in FIG.
(半導体装置）  (Semiconductor device)
図 3 A及び図 3 Bは、 図 2に示すテープ状半導体装置のベース基板を打ち抜い た形状をなす半導体装置を示す図である。 ベース基板 1 0の打ち抜きの位置は、 図 1に示す仮想線 4 2である。 ベース基板 1 0の打ち抜きは、 穴 5 2、 5 4に位 置決めビンを揷通させ、 ベース基板 1 0の位置決めしてから行ってもよい。 この半導体装置によれば、 スリット 4 0の開口端部が切断されてなる端部 6 6 と、 配線パ夕 ン 2 0との距離 （図中 A寸法） は、 配線パターン 2 0を形成する ための露光とエッチング工程の誤差範囲 （実際には基準寸法に対し ± 0 . 0 5 m m程度） まで狭めることができる。 このため配線パターン 2 0の範囲を大きくす ることができる。  3A and 3B are views showing a semiconductor device having a shape obtained by punching out a base substrate of the tape-shaped semiconductor device shown in FIG. The position where the base substrate 10 is punched is a virtual line 42 shown in FIG. The punching of the base substrate 10 may be performed after the positioning bin is passed through the holes 52 and 54 and the base substrate 10 is positioned. According to this semiconductor device, the distance (A dimension in the figure) between the end 66 formed by cutting the opening end of the slit 40 and the wiring pattern 20 is the same as that for forming the wiring pattern 20. The range of error between the exposure and etching steps (actually, about ± 0.05 mm with respect to the reference dimension) can be reduced. For this reason, the range of the wiring pattern 20 can be enlarged.
(半導体装置及び回路基板）  (Semiconductor devices and circuit boards)
図 4は、 本発明を適用した実施の形態に係る回路基板を示す図である。 図 4に 示すように、 回路基板 7 0には、 本発明を適用した半導体装置 7 2が電気的に接 続されている。 回路基板 7 0は、 例えば液晶パネルであってもよい。 半導体装置 7 2は、 テープ状半導体装置のベース基板 1 0を、 半導体チップ 6 0を囲む輪郭 で打ち抜いた形状なす。  FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied. As shown in FIG. 4, a semiconductor device 72 to which the present invention is applied is electrically connected to a circuit board 70. The circuit board 70 may be, for example, a liquid crystal panel. The semiconductor device 72 is formed by punching a base substrate 10 of a tape-shaped semiconductor device with a contour surrounding the semiconductor chip 60.
回路基板 7 0と、 半導体装置 7 2との位置決めは、 位置決めマーク 5 0を C C Dカメラ等で検出し、 その座標位置を算出するとともに X Yテーブルにこれを伝 達させて行ってもよい。  The positioning between the circuit board 70 and the semiconductor device 72 may be performed by detecting the positioning mark 50 with a CCD camera or the like, calculating the coordinate position thereof, and transmitting this to the XY table.
本実施の形態によれば、 スリット 4 0と配線パターン 2 0との位置精度は高く なっている。 このため図 3 Aに示すように、 位置決め用ブロック 6 8に、 スリツ ト 4 0が切断された形成された端部 6 6を押し付ければ （押付力は図中 F l、 F 2 )、 簡単で精度の高い位置決めが可能となる。 したがって、 半導体装置 7 2と 回路基板 7 0との接続を、 高い位置決め精度と設備の簡略化の下で図ることがで きる。 According to the present embodiment, the positional accuracy between the slit 40 and the wiring pattern 20 is high. For this reason, as shown in FIG. 3A, if the formed end portion 66 from which the slit 40 is cut is pressed against the positioning block 68 (the pressing force is F1, F2 in the figure). 2) Simple and highly accurate positioning is possible. Therefore, the connection between the semiconductor device 72 and the circuit board 70 can be achieved with high positioning accuracy and simplified equipment.
なお、 図 4に示すように、 半導体装置 7 2のベース基板 1 0は、 屈曲させて設 けてもよい。 例えば、 回路基板 7 0の端部の回りにベース基板 1 0を屈曲させて もよい。  As shown in FIG. 4, the base substrate 10 of the semiconductor device 72 may be provided to be bent. For example, the base substrate 10 may be bent around the end of the circuit substrate 70.
(電子機器）  (Electronics)
本発明を適用した半導体装置を有する電子機器として、 図 5には、 携帯電話 8 0が示されている。 この携帯電話 8 0は、 本発明を適用した回路基板 7 0 (液晶 パネル） も有する。 図 6には、 本発明を適用した半導体装置 （図示せず） を有す るノート型パーソナルコンピュータ 9 0が示されている。  As an electronic apparatus having a semiconductor device to which the present invention is applied, a mobile phone 80 is shown in FIG. This mobile phone 80 also has a circuit board 70 (liquid crystal panel) to which the present invention is applied. FIG. 6 shows a notebook personal computer 90 having a semiconductor device (not shown) to which the present invention is applied.
なお、 本発明の構成要件 「半導体チップ」 を 「電子素子」 に置き換えて、 半導 体素子と同様に電子素子 （能動素子か受動素子かを問わない） を、 可撓性配線基 板に実装して電子部品を製造することもできる。 このような電子素子を使用して 製造される電子部品として、 例えば、 光素子、 抵抗器、 コンデンサ、 コイル、 発 振器、 フィル夕、 温度センサ、 サ一ミス夕、 ノ、'リス夕、 ボリューム又はヒューズ などがある。  In addition, the electronic element (whether active element or passive element) is mounted on the flexible wiring board in the same manner as the semiconductor element, replacing the “semiconductor chip” with the “electronic element” of the present invention. To manufacture electronic components. Electronic components manufactured using such electronic devices include, for example, optical devices, resistors, capacitors, coils, oscillators, filters, temperature sensors, summits, nos, squirrels, and volumes. Or a fuse.
以下に、 本発明を適用した実施の形態に係る可撓性配線基板の製造方法を説明 する。  Hereinafter, a method for manufacturing a flexible wiring board according to an embodiment to which the present invention is applied will be described.
図 7 A〜図 8 Cは、 タブテープ （可撓性配線基板の一例） の製造過程を示すェ 程説明図である。 図 7 Aに示すようにタブテープ 1 2 0を構成するフィルム状の 基材 （ベース基板の一例） 1 2 2は、 その幅方向両端にスプロケヅ 卜ホール 1 2 1が等間隔で形成されたポリイミ ド材からなる。 スプロケットと嚙み合わされる ことで、 タブテ一ブ 1 2 0は、 長手方向に沿って搬送可能になっている。 なお、 基材 1 2 2の片側表面にはあらかじめ接着剤が塗布されており、 後述する銅箔を 基材 1 2 2に貼り付け可能にしている。  FIGS. 7A to 8C are process explanatory diagrams showing a manufacturing process of a tab tape (an example of a flexible wiring board). As shown in FIG. 7A, a film-like substrate (an example of a base substrate) 122 constituting the tab tape 120 is a polyimide having sprocket holes 122 formed at both ends in the width direction at equal intervals. Made of wood. By engaging with the sprocket, the tab table 120 can be transported in the longitudinal direction. Note that an adhesive is applied to one surface of the base material 122 in advance so that a copper foil described later can be attached to the base material 122.
タブテープ 1 2 0の搬送経路の途中には、 基材 1 2 2の打ち抜き用の金型が設 けられている。 金型は、 基材 1 2 2の内側にデバイスホール 1 2 4、 スリット 1 2 6及びアウターリードホール 1 2 8を形成するものである。 基材 1 2 2にこれ らホール類ゃスリット 1 2 6を形成した後の形態を図 7 Bに示す。 なお、 スリッ ト 1 2 6は、 図 7 Bに示されるように、 その長手方向を基材 1 2 2の長手方向に 一致させた形態となっている。 スリット 1 2 6は、 基材 1 2 2におけるスプロケ ットホール 1 2 1の形成領域付近、 すなわち基材 1 2 2の両端側に配置される。 基材 1 2 2に、 これらホール類ゃスリット 1 2 6を形成した後は、 基材 1 2 2 の表面に配線パターンの基となる銅箔を貼り合わせる （ラミネート工程）。 そし て基材 1 2 2の表面に銅箔を貼り合わせた後は、 配線パターンを形成するための 露光とエッチングとを行い、 基材 1 2 2の表面上に設定された配線パターン領域 に配線パターン 1 3 0を形成するようにする。 A die for punching the base material 122 is provided in the middle of the transport path of the tab tape 120. The mold has a device hole 1 2 4 inside the substrate 1 2 2 and a slit 1 26 and an outer lead hole 128. FIG. 7B shows a form after forming these holes and slits 126 in the base material 122. Note that, as shown in FIG. 7B, the slit 126 has a form in which the longitudinal direction matches the longitudinal direction of the base material 122. The slits 126 are arranged near the region where the sprocket holes 121 are formed in the substrate 122, that is, on both ends of the substrate 122. After these holes ゃ slits 126 are formed on the base material 122, a copper foil as a base of the wiring pattern is attached to the surface of the base material 122 (lamination step). After laminating the copper foil on the surface of the base material 122, exposure and etching are performed to form a wiring pattern, and wiring is performed in the wiring pattern area set on the surface of the base material 122. A pattern 130 is formed.
あらかじめデパイスホール 1 2 4とスリット 1 2 6とは、 図 7 Bに示すように 同時に形成されていることから、 デバイスホール 1 2 4とスリット 1 2 6との位 置関係はその後の工程で変動することがない。 このため配線パターンを形成する ための露光とエッチング工程の誤差範囲まで配線パターン 1 3 0をスリット 1 2 6に接近させることができる。 したがって、 デバイスホール 1 2 4から引き出さ れスリット 1 2 6の間に設定される配線パターン 1 3 0は、 スリット 1 2 6間の 最大外形に沿って設定することができる。 ホール類とパターン領域 1 3 0との位 置関係を図 7 Cに示す。  As shown in FIG. 7B, the position of the device hole 124 and the position of the slit 126 fluctuate in the subsequent process because the depth hole 124 and the slit 126 are formed at the same time as shown in FIG. Never do. Therefore, the wiring pattern 130 can be brought close to the slit 126 up to an error range of the exposure and etching steps for forming the wiring pattern. Therefore, the wiring pattern 130 drawn out from the device hole 124 and set between the slits 126 can be set along the maximum outer shape between the slits 126. FIG. 7C shows the positional relationship between the holes and the pattern region 130.
このように配線パターン 1 3 0を形成し、 タブテープ 1 2 0とした後は、 デバ イスホール 1 2 4の緣から配線パターン 1 3 0の延長として突出するィンナ一リ ードに半導体チップ 1 3 2の端子を位置合わせし、 両者の接合を行う。  After the wiring pattern 130 is formed as described above and the tab tape 120 is formed, the semiconductor chip 13 2 is attached to the inner lead projecting from the device hole 124 as an extension of the wiring pattern 130. Align the terminals and join them.
デバイスホール 1 2 4に半導体チップ 1 3 2を収容した状態を図 8 Aに示す。 そして半導体チップ 1 3 2をデバイスホール 1 2 4に収めた後は、 デバイスホー ル 1 2 4の縁より内側に樹脂を塗布し （その後に乾燥工程に投入)、 樹脂により 半導体チップ 1 3 2を封止することで、 デバイスホール 1 2 4の内側を保護する ようにしている。  FIG. 8A shows a state in which the semiconductor chip 132 is accommodated in the device hole 124. After the semiconductor chip 132 is placed in the device hole 124, a resin is applied to the inside of the edge of the device hole 124 (then, the resin is put into a drying step), and the semiconductor chip 132 is made of resin. By sealing, the inside of the device hole 124 is protected.
基材 1 2 2には、 デパイスホール 1 2 4、 スリット 1 2 6、 アウターリードホ ール 1 2 8及び配線パターン 1 3 0を含み、 半導体装置 1 3 4の外形となる打ち 抜き仮想線 1 3 6が設定される。 この打ち抜き仮想線 1 3 6の設定領域を図 8 B に示す。 図 8 Bに示すように打ち抜き仮想線 1 3 6は、 スリット 1 2 6と重なつ ており、 打ち抜き仮想線 1 3 6に沿って基材 1 2 2を打ち抜くことでスリット 1 2 6を分断させ、 半導体装置 1 3 4の外形の一部にスリツト 1 2 6の一部の形状 が存在するようにしている。 基材 1 2 2から打ち抜いた半導体装置 1 3 6を図 8 Cに示す。 The base material 122 includes a depth hole 124, a slit 126, an outer lead hole 128, and a wiring pattern 130, and the punching which becomes the outer shape of the semiconductor device 134. A virtual line 1 3 6 is set. FIG. 8B shows a setting area of the imaginary punched line 1 36. As shown in FIG. 8B, the imaginary punched line 1 36 overlaps with the slit 1 26, and the slit 1 2 6 is cut by punching the substrate 1 2 2 along the imaginary punched line 1 36. The shape of the slit 126 is partially present in a part of the outer shape of the semiconductor device 134. FIG. 8C shows a semiconductor device 1336 punched from the base material 122.

Claims

請 求 の 範 囲 The scope of the claims
1 . 長尺状のベース基板と、 前記ベース基板上に形成された複数の配線パ夕一 ンと、 を含み、  1. An elongated base substrate, and a plurality of wiring patterns formed on the base substrate,
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、 '  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction.
前記ベース基板には、 それそれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリッ 卜が形成され、  On the base substrate, a slit is formed on a punched imaginary line including the respective wiring pattern inside,
前記スリットは、 少なくとも、 前記べ一ス基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる可撓性配線基板。  The flexible wiring board, wherein the slit is formed at least in a position where the outer shape of the wide portion is formed in a shape punched out of the base board.
2 . 請求項 1記載の可撓性配線基板において、  2. The flexible wiring board according to claim 1,
前記スリツトは、 前記幅広部の外側の外形を形成する位置のみに形成されてな る可撓性配線基板。  The flexible wiring board, wherein the slit is formed only at a position forming an outer shape outside the wide portion.
3 . 請求項 1又は請求項 2記載の可撓性配線基板において、  3. The flexible wiring board according to claim 1 or claim 2,
前記配線パターン上及び前記ベース基板上であって前記スリットの周辺部を避 けた領域上に、 保護膜が設けられてなる可撓性配線基板。  A flexible wiring substrate, comprising a protective film provided on the wiring pattern and on the base substrate and on a region avoiding a peripheral portion of the slit.
4 . ベース基板と、 前記ベース基板上に形成された配線パターンと、 を含み、 前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  4. A base substrate; and a wiring pattern formed on the base substrate, wherein the wiring pattern is formed in a wide portion formed in a wide region in the width direction of the base substrate, and formed in a narrow region in the width direction. Having a narrow portion and
前記ベース基板には、 前記配線パターンを内側に含む打ち抜き仮想線上に、 ス リッ卜が形成され、  On the base substrate, a slit is formed on a punched imaginary line including the wiring pattern inside,
前記スリットは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなるフィルムキャリア。  The film carrier, wherein the slit is formed at least at a position forming an outer shape outside the wide portion in a shape of punching the base substrate.
5 . 長尺状のベース基板と、 前記ベース基板上に形成された複数の配線パ夕一 ンと、 前記ベース基板に搭載されて、 それそれの前記配線パターンに電気的に接 続された半導体チップと、 を含み、  5. A long base substrate, a plurality of wiring patterns formed on the base substrate, and a semiconductor mounted on the base substrate and electrically connected to each of the wiring patterns. Including a chip and
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
前記ベース基板には、 それぞれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリッ 卜が形成され、 On the base substrate, there is a punched imaginary line including each wiring pattern inside. Then, a slit is formed,
前記スリッ トは、 少なくとも、 前記べ一ス基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなるテープ状半導体装置。  The tape-shaped semiconductor device, wherein the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape of punching the base substrate.
6 . 請求項 5記載のテープ状半導体装置の前記ベース基板を、 前記打ち抜き仮 想線で打ち抜いて得られた半導体装置。  6. A semiconductor device obtained by punching the base substrate of the tape-shaped semiconductor device according to claim 5 by the punching virtual line.
7 . ベース基板と、 前記ベース基板上に形成された配線パターンと、 前記べ一 ス基板に搭載されて前記配線パターンに電気的に接続された半導体チップと、 を 含み、  7. A base substrate; a wiring pattern formed on the base substrate; and a semiconductor chip mounted on the base substrate and electrically connected to the wiring pattern.
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
前記ベース基板には、 それそれの配線パターンを内側に含む打ち抜き仮想線上 に、 スリッ卜が形成され、  On the base substrate, a slit is formed on a punched imaginary line including the respective wiring pattern inside,
前記スリットは、 少なくとも、 前記ベース基板を打ち抜く形状のうち、 前記幅 広部の外側の外形を形成する位置に形成されてなる半導体装置。  The semiconductor device, wherein the slit is formed at least at a position forming an outer shape outside the wide portion in a shape punched out of the base substrate.
8 . 請求項 6記載の半導体装置が電気的に接続された回路基板。  8. A circuit board to which the semiconductor device according to claim 6 is electrically connected.
9 . if求項 7記載の半導体装置が電気的に接続された回路基板。  9. A circuit board to which the semiconductor device according to claim 7 is electrically connected.
1 0 . 請求項 6記載の半導体装置を有する電子機器。  10. An electronic apparatus comprising the semiconductor device according to claim 6.
1 1 . 請求項 7記載の半導体装置を有する電子機器。  11. An electronic apparatus having the semiconductor device according to claim 7.
1 2 . 配線パターンが形成され、 かつ、 スリットが形成された可撓性のベース 基板に半導体チップを実装し、 前記ベース基板を前記スリヅト上を通る仮想線で 打ち抜く工程を含み、  12. A wiring pattern is formed, and a semiconductor chip is mounted on a flexible base substrate in which a slit is formed, and a step of punching the base substrate with a virtual line passing over the slit is included.
前記配線パターンは、 前記ベース基板の幅方向に広い領域に形成された幅広部 と、 幅方向に狭い領域に形成された幅狭部と、 を有し、  The wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
打ち抜かれて残った前記スリットの端部によって、 前記幅広部の外側の外形を 形成する半導体装置の製造方法。  A method of manufacturing a semiconductor device, wherein an outer shape of the wide portion is formed by an end of the slit remaining after punching.
1 3 . 請求項 1 2記載の半導体装置の製造方法において、  13. The method of manufacturing a semiconductor device according to claim 12,
前記配線パターン上及び前記ベース基板上であって前記スリッ卜の周辺部を避 けた領域上に、 保護膜を設ける工程を含む半導体装置の製造方法。 A method of manufacturing a semiconductor device, comprising a step of providing a protective film on the wiring pattern and on the base substrate and on a region avoiding a peripheral portion of the slit.
1 4 . 請求項 1 2又は請求項 1 3記載の半導体装置の製造方法において、 前記べ一ス基板には、 複数の前記配線パターンが形成され、 14. The method for manufacturing a semiconductor device according to claim 12 or claim 13, wherein a plurality of the wiring patterns are formed on the base substrate,
前記スリツトは、 それそれの配線パターンごとに対応して形成され、 前記半導体チップを、 それそれの配線パターンに電気的に接続し、  The slit is formed corresponding to each wiring pattern, and the semiconductor chip is electrically connected to each wiring pattern.
それそれの配線パターンを含み、 かつ、 対応する前記スリットを通る領域に、 前記仮想線を設定して、 前記ベース基板を打ち抜く半導体装置の製造方法。  A method of manufacturing a semiconductor device, wherein the virtual line is set in a region including each wiring pattern and passing through the corresponding slit, and the base substrate is punched.
PCT/JP2000/000552 1999-02-09 2000-02-02 Flexible printed-circuit substrate, film carrier, semiconductor device on tape, semiconductor device, method of semiconductor manufacture, circuit susbstrate, and electronic device WO2000048243A1 (en)

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KR100947587B1 (en) 2003-04-17 2010-03-15 삼성테크윈 주식회사 A Substrate For A Semiconductor Package
US7282389B2 (en) 2003-11-14 2007-10-16 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
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US7323365B2 (en) 2003-11-14 2008-01-29 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
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JP2006191111A (en) * 2005-01-04 2006-07-20 Samsung Electronics Co Ltd Original sheet for flexible printed circuit board with cutting pattern formed, and display including flexible printed circuit board having the same cut
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