WO2000041397A1 - Systeme informatique de multiplexage statistique de flux binaires - Google Patents

Systeme informatique de multiplexage statistique de flux binaires Download PDF

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Publication number
WO2000041397A1
WO2000041397A1 PCT/US2000/000245 US0000245W WO0041397A1 WO 2000041397 A1 WO2000041397 A1 WO 2000041397A1 US 0000245 W US0000245 W US 0000245W WO 0041397 A1 WO0041397 A1 WO 0041397A1
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Prior art keywords
video
stat
sub
mux
encoder
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PCT/US2000/000245
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English (en)
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WO2000041397A8 (fr
Inventor
Ravi Krishnamurthy
Sriram Sethuraman
Xiaobing Lee
Tihao Chiang
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Sarnoff Corporation
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Priority claimed from US09/478,128 external-priority patent/US6754241B1/en
Priority claimed from US09/478,127 external-priority patent/US6665872B1/en
Application filed by Sarnoff Corporation filed Critical Sarnoff Corporation
Publication of WO2000041397A1 publication Critical patent/WO2000041397A1/fr
Publication of WO2000041397A8 publication Critical patent/WO2000041397A8/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H04N21/2365—Multiplexing of several video streams
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/115—Selection of the code volume for a coding unit prior to coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H04N19/14—Coding unit complexity, e.g. amount of activity or edge presence estimation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H04N19/15—Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H04N19/152—Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
    • H04N19/159—Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/177—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/179—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scene or a shot
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H04N21/2365—Multiplexing of several video streams
    • H04N21/23655—Statistical multiplexing, e.g. by controlling the encoder to alter its bitrate to optimize the bandwidth utilization
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4347—Demultiplexing of several video streams

Definitions

  • the quality of service depends on the fidelity and uniformity of the video playback, where collectively high fidelity and high uniformity typical mean (1) uniform, full frame rates and (2) uniform high image quality both within each frame and between consecutive frames.
  • the end-to-end latency involved in the processing is of less importance.
  • the primary concern of bandwidth managers for conventional statistical multiplexing schemes involving conventional applications is to ensure that there will always be sufficient data in the receiver buffer at each user node to provide high fidelity, uniform video playback to each user. High levels of latency, however, are not acceptable for all applications.
  • the present invention is directed to computer systems designed to support statistical multiplexing schemes that do take into account the corresponding latency requirements of different video/audio applications (in addition to other factors such as uniformity and fidelity of video playback) when managing the bandwidth of shared communication channels.
  • the computer systems support statistical multiplexing that takes latency into account to provide (a) traffic control (i.e., the control of how the data for multiple compressed bitstreams is transmitted over each shared communication channel) as well as (b) some level of control over the actual compression processing used to generate those bitstreams for the different video/audio applications.
  • the present invention is a computer system, comprising (a) a plurality of encoding sub-systems, each encoding sub-system having (1) an input port configured to receive an input data stream; and (2) an output port configured to transmit a corresponding compressed bitstream generated by the encoder from the input data stream; and (b) a statistical multiplexing (stat- mux) sub-system having (1) a plurality of input ports, each input port configured directly to the output port of a corresponding encoding sub-system to receive the corresponding compressed bitstream; and (2) an output port configured to transmit data generated as a result of the stat-mux sub-system performing statistical multiplexing on the plurality of compressed bitstreams.
  • stat- mux statistical multiplexing
  • Fig. 1 shows a block diagram of a video processing system, according to one embodiment of the present invention
  • Fig. 2 shows an assumed piecewise linear cost function based on latency
  • FIG. 1 shows a block diagram of a video processing system 100, according to one embodiment of the present invention.
  • Video processing system 100 compresses multiple video streams corresponding to different video applications for transmission over a single shared communication channel 116.
  • the different video applications may include any suitable combination of different type of video applications including video conferencing, interactive video games having different levels of sophistication, web browsing, and electronic mail.
  • the shared communication channel may be any suitable transmission path that supports the concurrent transmission of multiple data streams, such as Ethernet, TCP/IP, Broadband networks, satellite, cable transmission, ADSL, DSL, and cable modem.
  • Class 2 encoders 110 provide slightly lower levels of video compression processing power than
  • Class 1 encoders 108 but higher levels of external control over their internal video compression processing.
  • Class 2 video encoders which are typically high-end software encoders, are suitable for (a) video applications requiring slightly lower bandwidth and/or slightly higher latency, such as video streaming applications and low-end interactive video games.
  • Coarse video compression control signals correspond to relatively high-level control over video compression processing and may include frame rates, target numbers of bits per frame, and/or average quantization levels over a frame.
  • Fine video compression control signals correspond to relatively low-level control over video compression processing and may include target numbers of bits per slice within a frame, average quantization levels per slice or even per macroblock within a frame. Other types of fine video compression control signals will be described later in this specification.
  • Video processing system 100 also has an off-line profiling tool 122, which analyzes, in non-realtime, typical sets of video sequences corresponding to different types of video applications and stores the results of those analyses in an application profiles server 124.
  • the service admission manager 104 accesses information in the application profiles server 124 in order (1) to determine whether to admit a particular new video application and, if so, (2) to determine to which video encoder to assign the newly admitted video application.
  • controller 114 also accesses information in the application profiles server 124 in order to (1) determine an acceptable level of buffering for at least one video application and (2) order packets of data from different video applications.
  • the controller can attempt to maintain this constraint on all the encoders.
  • region of interest information is available, and slice level MQUANT setting is possible, the controller can intelligently trade-off and change the MQUANT over a frame. Similar control for frame- rate and spatial resolution is also possible.
  • video processing system 100 corresponds to three different generic functions: (1) off-line application profiling for content classification (implemented by off-line profiling tool 122), (2) service admission processing (implemented by service admission manager 104), and (3) traffic and compression control (implemented by controller 114). Each of these three functions is described in further detail in the following sections.
  • off-line profiling tool 122 analyzes, in non-real-time, typical sets of video sequences corresponding to different types of video applications and stores the results of those analyses in application profiles server 124.
  • the profiling is semi-automatic and each video application is characterized according to the following parameters: (a) Level of interactivity (related to latency tolerance); (b) Extent of frame-to- frame motion (both peak and average);
  • service admission manager 104 will admit the new application, if and only if both of the following two rules would be satisfied after admitting the new application:
  • Traffic and Compression Control Multiplexer and traffic controller 114 handles the following tasks:
  • a one-frame bit buffer is used for Class C3 applications.
  • the encoders encode a new frame only after all the bits for the frame that was encoded before the last frame have been transmitted by controller 114.
  • This on-demand encoding eliminates the possibility of congestion due to Class C3 services.
  • Other strategies to tune the encoding to suit the application's demands are discussed in the following section.
  • the allocation decisions for all applications are made at the slice level. After all the bits for a slice in each encoder arrive at controller 114, the allocation is made based on the buffer fullness and the latency requirement for the application. This can be done in two steps: (1) each application in Classes Cl and C2 is allocated a bandwidth that is the minimum of the buffer occupancy and the slice-level bit rate used by service admission manager 104, and (2) the remaining bandwidth, if any, is then distributed among all the applications, in turn, to meet their latency requirements.
  • Class Cl applications take precedence over Class C2
  • Class C2 takes precedence over Class C3.
  • Class C3 bits are transmitted only when bits remain in an allocation after the latency requirement for Classes C 1 and C2 are met.
  • the buffer occupancy is maintained below the maximum allowed buffer delay for a service during normal operation. The exceptions (i.e., when the requirement for Classes Cl and C2 cannot be met) are handled under the pathological cases.
  • o Simple Profile Encoding Since B pictures lead to re-ordering delays, in order to maintain low latency, encoding is performed with only I and P pictures. In addition, using dual-prime motion vectors can result in improved compression efficiency for IP-only encoding.
  • o Pipelining the encoder Computational pipelining refers to performing all the encoding tasks on a minimum unit of encoding, e.g., macroblock, slice. Typical hardware encoders use hierarchical motion search and cannot be pipelined entirely.
  • Pre-processing The final output display device is interlaced, even though the encoded material is progressive. Further, field picture coding modes are proposed to reduce latency. Thus, suitable pre- processing by vertical filtering, etc. is essential for good display quality.
  • Motion estimation complexity can be reduced by exploiting the knowledge about the graphics commands. Intercepted graphics commands can be used to quickly and accurately estimate motion without going through the complete search process. Again, this may lead to significant computational savings.
  • Computer systems in accordance with the present invention avoid PCI bus delay by using the built-in multi-channel Synchronized Serial Interface (SSI) ports of multiple Digital Signal Processors (DSPs), where each DSP performs video and audio encoder control, PES/TS layer multiplexing, and computation of statistical measurements of its corresponding video stream payload.
  • the DSPs' on-chip memories may also eliminate the need for bitstream First-In, First-Out (FIFO) chips and some common SDRAM (Synchronized Dynamic Random Access Memory) chips.
  • Fig. 3 shows a system-level block diagram of computer system 300, according to one embodiment of the present invention.
  • Computer system 300 is a PCI bus-based industrial PC (Personal Computer) enclosure with multiple PCI boards.
  • CPU Central Processing Unit
  • Stat-mux statistical multiplexing
  • Stat-mux board 308 has a PCI bus interface 330 and four DSP chips 332, where each DSP chip 332 has a six-channel SSI DMA (Direct Memory Address) 334 with six SSI ports 336, SRAMs 338, two DSP cores 340, and an ASI/TAXITM chip set from Advanced Micro Devices, Inc., of Sunnyvale, California, and, in block 342, a DHEI (Digital High-speed Expansion Interface) I/O port from General Instrument Corporation (GI) of Horsham, Pennsylvania, for GFs modulator and CA (Conditional Access) equipment. As such, stat-mux board 308 can support up to 24 channels of low-delay MPEG2 video/audio input bitstreams.
  • SSI DMA Direct Memory Address
  • SRAMs 338 Serial Memory Address
  • ASI/TAXITM chip set from Advanced Micro Devices, Inc., of Sunnyvale, California
  • DHEI Digital High-speed Expansion Interface
  • I/O port from General Instrument Corporation
  • PCI bus 302 is used for power supply and system control for each PCI board.
  • a DSP chip on each encoder board 306 will directly transfer low-delay MPEG2 bitstreams to a corresponding DSP on stat-mux board 308.
  • each low-delay MPEG2 video/audio bitstream will be directly transmitted from the SSI port 328 of the corresponding encoder board 306 to an SSI port 336 on stat- mux board 308.
  • the associated delay can be controlled to correspond to as few as four transport packet delays, with a two-packet delay in the encoder DSP 326, a one-packet delay at an input port 336 of stat-mux board 308, and a one-packet delay at an output port 342 of stat-mux board 308.
  • PCI bus 302 can be used to transmit additional MPEG2 video/audio bitstreams that do not have low-latency requirements.
  • these high-latency bitstreams may be generated by video/audio encoders implemented in software within the central processor on CPU board 304.
  • Fig. 4 shows a board-level block diagram of each encoder board 306 of computer system 300 of Fig. 3, according to one embodiment of the present invention.
  • Encoder board 306 comprises an internal board bus 402 configured with an input interface module 318, an MPEG2 video encoder 320, an AC3 or MP3 audio encoder module 322, a DSP controller 326 with PES/TS-layer multiplexing firmware, and 27-MHz SCR/PCR circuits 408, where SCR is the System Clock Reference in an MPEG video decoder and PCR is the Program Clock Reference in an MPEG transport decoder.
  • Input interface module 318 can support both SDI and ASI circuits with a 270-MHz or 180-MHz line-coded clock, respectively.
  • the SDI or ASI signals can be customized to interlace the uncompressed digital video data and multi-channel audio data.
  • MPEG2 video encoder 320 can be any suitable single-chip encoder, such as those supplied by IBM, C-Cube, or Philips, with supporting SDRAM, SRAM, and/or flash memories 404 and necessary glue logic circuits.
  • the glue logic can be combined within the input CPLD firmware.
  • Audio encoder 322 can be any suitable off-shelf DSP-based sub-system that can support either the AC3 or MP3 encoding function depending on the DSP software.
  • audio encoder 322 can be combined with DSP controller 326, shared memories 406, and the PES/TS multiplexing firmware for less board area and lower integration costs.
  • DSP 326 may be a TMS320c5402 DSP from Texas Instruments. DSP 326 will provide of video encoder control, audio encoder control, the SCR/PCR time-base controls, and the overall board-level controls. It will also perform the PES/TS multiplexing of compressed video and audio bitstreams, and the statistical parameter measurements of the video stream. It will also execute the commands of statistical multiplexing controls received from PCI bus 302 of Fig. 3.
  • DSP on-chip SSI output port 328 can be directly connected to an SSI input port of a DSP on stat-mux board 308 of Fig. 3.
  • the on-chip DMA will automatically move data from the TS output buffer of on-chip memory to the serial output port.
  • the TMS320c5410 DSP has 128 Kbytes of on-chip memory and a DMA-controlled host interface port, such that external SRAM and FIFO devices may be eliminated.
  • video encoder 320 is an IBM39 MPEGS422 video encoder chip
  • the video encoder can directly write its compressed video data into the TMS320c5410 on-chip SRAM with a simple CPLD to emulate the FIFO signals.
  • the PES/TS MUX delay can be within transmitting two TS packets of video streams, such as 2 x 188 x 8 * video_rate delay.
  • DSP on-chip timer 408 can also be programmed for the 27-MHz SCR PCR time-base by incorporating on-chip PLL (Phase-Locked Loop) circuits. All of the 27-MHz clocks will be derived from the same 27-MHz clock on stat-mux board 308 through the clocks of the SSI ports connected to all of the encoder boards 306.
  • PLL Phase-Locked Loop
  • Each SSI serial input port 336 has three wires carrying a clock signal (sclk), a data signal (sdat), and a frame signal. All 24 clock signals sclk should be configured as the input clock signals and connected to an on-board 27-MHz clock oscillator 504. 27-MHz clock 504 will also be used as the DSP clock, and on-chip PLL circuits will generate a 90-MHz DSP clock. In that case, on-chip timers can be used for the PCR time-base corrections.
  • the frame signals will indicate whether or not the data signal sdat carries meaningful data.
  • the data signals sdat are burst with a maximum rate of 27 Mbps.
  • the frame signals can also be programmed in a "multi-channel mode" to send multiple packets into assigned on-chip buffers for transmitting the individual encoders' statistical parameters.
  • ASI interface 506 uses a TAXI transmitter chip with parallel interface from Advanced Micro Devices, such that there are FIFO and CPLD control circuits to handle the TAXI interface and ASI controls.
  • a DHEI interface 508 from GI will need additional PLL circuits to generate the output clock, if there is no available input clock signal from DHEI port 510.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

L'invention concerne un ordinateur de type PC qui comporte un bus système (par exemple, un bus PCI) configuré au moyen d'une carte unité centrale, d'une carte de multiplexage statistique, et d'une pluralité de cartes de codage vidéo/audio, chacune étant configurée pour recevoir et comprimer un flux vidéo/audio correspondant. La carte de multiplexage statistique réalise un multiplexage statistique sur les différents flux binaires comprimés de façon à transmettre des flux binaires multiples sur des voies de communication partagées. Bien que chacune des cartes soit configurée pour le bus système, chaque carte de codage comporte un processeur de signaux numériques (DSP) muni d'un port de sortie d'interface série synchronisée (SSI), directement connecté à un port d'entrée SSI du processeur de signaux numériques (DSP) de la carte de multiplexage statistique (qui, dans un mode de réalisation, comporte quatre DSP, chacun comprenant six ports de sortie SSI). De cette façon, des flux binaires vidéo/audio comprimés (jusqu'à 24), générés sur les différentes cartes de codage, peuvent être transmis directement à la carte de multiplexage statistique sans avoir à passer par le bus système. Le système informatique peut ainsi réaliser un multiplexage statistique de flux binaires vidéo/audio à faible temps d'attente sans devoir subir les temps d'attente de traitement, caractéristiques des transmissions classiques via des systèmes bus PCI.
PCT/US2000/000245 1999-01-06 2000-01-06 Systeme informatique de multiplexage statistique de flux binaires WO2000041397A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US11484299P 1999-01-06 1999-01-06
US11483499P 1999-01-06 1999-01-06
US60/114,842 1999-01-06
US60/114,834 1999-01-06
US17088399P 1999-12-15 1999-12-15
US60/170,883 1999-12-15
US09/478,128 US6754241B1 (en) 1999-01-06 2000-01-05 Computer system for statistical multiplexing of bitstreams
US09/478,127 US6665872B1 (en) 1999-01-06 2000-01-05 Latency-based statistical multiplexing
US09/478,128 2000-01-05
US09/478,127 2000-01-05

Publications (2)

Publication Number Publication Date
WO2000041397A1 true WO2000041397A1 (fr) 2000-07-13
WO2000041397A8 WO2000041397A8 (fr) 2001-06-21

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