WO2000022522A1

WO2000022522A1 - Method for detecting equivalent instruction sequences

Info

Publication number: WO2000022522A1
Application number: PCT/RU1998/000324
Authority: WO
Inventors: Mikhail Figurin; Mikhail Okrugin; Dmitry Barmenkov
Original assignee: Motorola Inc.
Priority date: 1998-10-13
Filing date: 1998-10-13
Publication date: 2000-04-20

Abstract

In an optimizer (100), a method (300) is applied to detect equivalent instruction sequences in a software program (500) written in assembly language. The optimizer (100) loads the program (310), establishes a tree structure (320) and identifies isomorphic Single-Entry-Single-Exit (SESE) structures (330). SESEs are isomorphic when they have: (a) equal level within the tree and (b) an equal number of sub-SESEs. Then, the optimizer (100) assigns alphabet elements (130, e.g., 'a', 'b', 'c') to program instructions (550) and lists the elements according to their occurrences (140). In repetitions, optimizer (100) detects multiple occurring elements combinations (e.g., (a, b)) and skips uniquely occurring elements. The multiple occurring elements combinations represent the equivalent instruction sequences and form the input information for further modifying the program (350).

Description

METHOD FOR DETECTING EQUIVALENT INSTRUCTION SEQUENCES

Field of the Invention

The present invention generally relates to computer programming, and, more particularly, to a method for detecting and eliminating equivalent instructions sequences in a program.

Background of the Invention

The optimization of software programs is important to save memory space, to speed up program execution and for verification and testing. For example, instructions or data with different coding but substantial equal contents can be identified so that the program can be simplified. Such and other optimization features are known in the art as, for example, common subexpression elimination (CSE), Register reallocation, Movement of Invariant Code, Branch Elimination, Branch Fusion and Loop Jamming. Some optimization tasks are explained in: [1] Bowen Alpern, Mark N. Wegman, Kenneth Zadeck: "Detecting Equality of Variables in Programs", Proceedings of the Fifteenth Annual ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, San Diego, California (January 1988).

Software developers can benefit from Computer-Aided Software Engineering (CASE) software. Among them, optimization tools support high-level programming languages, such as, e.g., C, FORTRAN or PASCAL. However, optimization tools do often not support assembly language or machine code. Code written in assembly language is often less structured than high-level language code. Also, assembly code often uses more global variables than local variables. Therefore, traditional analysis is time and memory space consuming. This is especially important if a program has many branches which are conditionally executed. Other references are:

[2] Robert S. Boyer, J Strother Moore: "A Fast String Searching Algorithm", Communications of the ACM, October 1977, volume 20, Number 10, pages 762-772;

[3] Cliff Click: "Global Code Motion, Global Value Numbering", 1995 ACM SIGPLAN, pages 246-257; [4] John Cocke: "Global Common Subexpression Elimination", SIGPLAN, July O 00/22522

2

[5] Alfred V. Aho, Margaret J. Corasick: "Efficient String Matching: An Aid to Bibliographic Search", Communications of the ACM, June 1975, Volume 18, Number 6, pages 333-340;

[6] Alfred V. Aho, John E. Hopcroft, Jeffrey D. Ullman: "The Design and Analysis of Computer Algorithms". Addison-Wesley Publishing Company, 1994, ISBN 0-201-00029-6; and

[7] Alfred V. Aho, John E. Hopcroft, Jeffrey D. Ullman: "Data Structures and Algorithms", Addison-Wesley Publishing Company, 1983, ISBN 0-201-00023-7.

There is, among others, the technical task to provide efficient computer methods for common subexpression elimination (CSE) in branched programs written in assembly language. The present invention seeks to avoid or mitigate disadvantages and limitations of the prior art.

Brief Description of the Drawings

FIG. 1 illustrates a simplified block diagram of a program optimizer according to the present invention; FIG. 2 is a simplified flow chart diagram of a program which is analyzed according to a method of the present invention; FIG. 3 illustrates a simplified flow chart diagram of an optimization method according to the present invention; FIG. 4 is a simplified diagram illustrating a determining step of the method of FIG. 3 by an instruction sequence, an event table, an alphabet sequence, an instruction- event correspondence table, and combination graphs; FIG. 5 is a simplified diagram illustrating mapping from an instruction set to an alphabet set and further to an combination set; and FIGS. 6A-6B are simplified flow chart diagrams of a program portion to illustrate method steps of the method of FIG. 3.

Detailed Description of a Preferred Embodiment

Some portions of this description are presented in graphical and programming language representations. Such representations are used by persons skilled in data processing to more effectively convey the substance of their work to other persons. Such representations and terms such as, for example, "tree", "line" , "point", etc., or, for example, "begin", "end", "jump", etc., are to be associated with the appropriate operation of a machine optimizer and are merely convenient labels. For convenience, a summary of notation is provided prior to the claims.

Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in any of the operations described herein which form part of the present invention.

FIG. 1 illustrates a simplified block diagram of program optimizer 100 (hereinafter optimizer 100) according to the present invention. For example, optimizer 100 can be realized by an all-purpose computer having memory 150, data and address busses 126, 127 and processor 125. Other components, such as peripherals for data input/output are not shown for simplicity. Conveniently, memory 150 of optimizer 100 stores program 500 (cf. FIG. 2) and optimization software 301 which executes the method of the invention (cf. method 300 of FIG. 3). According to method 300 (cf. FIG. 3) of the present invention, optimizer 100 analyses and modifies program 500 by identifying equivalent instruction sequences ("common subexpressions"). A definition for

"equality" is not important for the present invention and depends only on optimization requirements. An example is given in connection with FIG. 4. The term "sequence" is used herein for one or more instructions of program 500 that are consecutively stored in memory 150. It is an advantage of the present invention, that program 500 can be supplied to optimizer 100 in assembly language or in a similar low-level programming language. This feature makes the present invention especially useful for programs 500 of embedded applications. Preferably, optimizer 100 does not execute program 500. Resources of program 500 are accessed during execution of program 500 by the application. The present invention does not depend on the details of the machine for which the instruction sequence has been written.

These features make the present inventions suitable to optimize code for embedded systems of, for example, processors and memory on a single chip. Saving memory space improves the performance of the embedded system in terms of, among other things, power consumption, execution time and reliability.

FIG. 2 is a simplified, exemplary, flow chart diagram of program 500 which is analyzed according to the method of FIG. 3. Such a flow chart is known as "control- flow graph". Program 500 has branch points 51 1-515 illustrated by query symbols (diamonds) and non-branch blocks 531-539 ("basic blocks") identified by circles. Branch points 51 1-515 and basic blocks 531-539 are collectively referred to as

"nodes". Assume for convenience of explanation, that branch points 51 1 -515 are conditions and that the program flow follows THEN for compliance or ELSE for non- compliance. Blocks 531-539 each comprise K > 1 instructions 550 ("expressions") which are executed consecutively. FIG. 2 illustrates instructions 550 by • symbols.

As used herein, an instruction is a command which can be executed in a single processor step. For example, instruction 550 can be a single line of assembly code (e.g., "STAA varl"). Blocks 531-539 should not have instructions to jump out of the block. Lines ("edges") such as start line 501 and end line 502 having arrows indicate a preferred program flow of program 500. Some of the lines have join points 521 -525 which mark the first instruction 550 in a block (points 521 , 524) or mark a branch point (e.g., points 512, 515). As explained later in connection with FIG. 6, portion 505 (dashed frame between lines 503 and 504) can be modified. Portion 505 comprises branch point 512, blocks 533 and 534 and join point 522. In language representation, program 500 can be expressed as follows:

02 begin program 500 (line 501) (1)

04 if condition 511 then 06 begin point 521 A B

08 block 531 A B

10 block 532 A B G F

12 line 503

14 if condition 512 then block 534 A B G I 16 else block 533 A B G J

18 point 522, line 504 A B G

20 if condition 513 then jump to 521 A B

22 end A B

24 else 26 begin block 536 A C

28 if condition 514 then block 538 A D H

30 else A D

32 begin point 524 A D

34 block 537 A D 36 , end

38 point 525

40 if condition 515 then jump to 524 A D

42 block 539 A E

44 end A 46 point 523

48 ^"block 535

50 end program 500 (line 502)

The two-digit line numbers 02 to 50 on the left side are provided for convenience of further explanation, but do not belong to the program. The notations "line" and "point" referring to FIG. 2, are also not instructions. For example, block 536 can have the following k = 1 to K = 10 instructions 550:

LDAA #1 k = l (2)

STAA varl k = 2 STAA varl k = 3

LDAA #2 k = 4

LDAA #1 = 5

STAA varl k = 6

LDAA #2 k = 7 LDAA #2 k = 8

LDAA #1 k = 9

STAA varl k = 10

Program 500 is now discussed in a top-down view with "SESE" and "isomorphic structures". Uppercase letters A to J (dashed frames in FIG. 2 and on the right side of representation (1) identify single-entry-single-exit (SESE) structures. A SESE (e.g., G) has only one start instruction (e.g., condition 512) and a single end instruction or multiple end instructions (e.g., in SESE G, the last instructions of blocks 534 and 533 at point 522) followed by one and the same instruction (e.g., condition 513) In other words, a SESE is a plurality of expressions which: (a) do not have an instruction which is a target of any other instruction outside this plurality and (b) do not have jump expressions pointing to further expressions outside the expression plurality. This definition includes that jump instructions (e.g., THEN of 515) inside a SESE (e.g., D) are allowed. For example, block 536 forms SESE C which starts with "LDAA #1", ends with "STAA varl" and does not have a jump-out instruction. Or, block 537 which can be started by condition 514 ELSE or by condition 515 THEN is not a SESE. Block 535, is not a SESE because it either follows condition 513 ELSE or block 539. Some SESE comprise further, depending SESE ("sub"). A SESE ("parent") can optionally have one or more sub-SESE ("child" or "children") which do not overlap. For example, SESE A (lines 06-44) with sub-SESEs B, C, D and E (3)

SESE G (lines 10-18) with sub-SESEs I and J (4)

SESE D (28-40) with sub-SESE H (5)

SESE B (06-22) with sub-SESEs F and G (6)

SESE G (10-18) with sub-SESEs I and J (7) Some of the sub-SESEs can also have one or more sub-SESE ("grandchild"). For example, sub-SESE B with sub-sub-SESEs F and G (8) sub-SESE D with sub-sub-SESE H (9) sub-sub SESE G with sub-sub-sub-SESEs I and J (10) Conveniently, levels lev (...) for each SESE are defined. SESE which do not have any sub-SESE should have lev (...) = 1 as, for example: lev ( C )= 1, (11) lev ( E ) = 1, lev ( F ) = 1, lev ( I ) = 1, lev ( J ) = 1, lev ( H ) = 1. The levels of the other SESEs ("parents", "grandparents", etc.) depend on the maximum level of the child SESEs. In general, the level is the maximum value ("max") of the levels of its sub-SESE plus "one", that is: lev (...) = { max [ lev of sub-SESEs ] + 1 } (12) lev (G) = { max [ lev (I), lev(J) ] + 1 } (13) lev(G) = { max [ 1,1 ] + 1 } lev (G) = 2 lev (D) = { max [ lev (H) ] + 1 } (14) lev (D) = 2 lev (B) = { max [ lev (F), lev (G) ] + 1 } (15) lev(B) = { max [ 1,2] + 1 } lev (B) = 3 lev (A) = { max [ lev (B), lev (C), lev (D), lev (E) ] + 1 } (16) lev(A) = { max [3, 1,2, 1 ]+ 1 } lev (A) = 4

Now, program 500 is discussed in terms of isomorphic structures. Conveniently, pairs [lev, nc] can be used to describe each SESE. In the pair, lev stand for the above mentioned level; and nc stands for a total number of sub-SESE plus 1. SESEs without sub-SESE have conveniently nc (SESE) = 1. The pairs for SESEs C, E, F, I, J, and H have, for example: nc (C) = nc (E) = nc (F) = nc (I) = nc (J) = nc (H) = 1 (17)

[lev, nc]_{c E F} , , _H = [1,1]. (18)

The nc-values for the other SESE are conveniently obtained as the sum of the nc-values of their sub-SESE, that is: nc (SESE) = sum of nc(sub-SESEs) (19)

For example, nc (G) = nc (I) + nc (J) = 1 + 1 +1 =3 (20)

[lev, nc]_G = [2,3] nc (D) = nc (H) + 1 = 1 + 1 =2 [lev, nc]_D = [2, 2] nc (B) = nc (G) + nc (F) +1 =3+ 1 + 1 =5

[lev, nc]_B = [2, 5] nc (A) = nc (B) + nc (C) + nc (D) + nc (E) + 1 = 5 + 1 + 2 + 1 + 1 = 10

[lev, nc]_A = [4, 10]

As used herein a SESE α and a SESE β are isomorphic if the following conditions are both satisfied: (l) lev (α) = lev (β) (21)

(2) nc (α) = nc (β) (22)

In other words, SESE α and a SESE β are isomorphic when their pairs are equal:

[lev, nc]_α = [lev, nc]_β (23)

For example, SESE I and SESE J are isomorphic. FIG. 3 illustrates a simplified flow chart diagram of an optimization method 300 according to the present invention. Method 300 comprise loading step 310, establishing tree step 320, parsing step 330, determining step 340. and modifying step 350. It is an advantage of the present invention, that steps 310-350 can be performed in one pass without iterations. In loading step 310, optimizer 100 loads program 500 into memory 150. In establishing tree step 320, optimizer 100 provides a tree structure of program 500 and assigns levels for SESE structures as illustrated in FIG. 2. In parsing step 330, optimizer 100 finds isomorphic SESEs within program 500. Preferably, non- isomorphic SESEs are marked such that they are not considered in further steps. In determining step 340, optimizer 100 identifies equivalent instructions and instructions sequences in the isomorphic SESEs found in parsing step 330. This is an important advantage of the present invention. Optimizer 100 does not need to check the complete program 500 for equivalent instruction sequences. Instead, the search for equivalent instruction sequences is limited beforehand to some program portions selected in step 330. A preferred implementation of determining step 340 is explained in connection with FIGS. 4-5 by an example. In modifying step 350, optimizer 100 limits the number of equivalent instruction sequences, by for example, code hoisting. Modifying techniques which change equivalent instruction sequences are known in the art.

In other words, optimizer 100 first analyzes the program structure of program 500 in a top-down approach. Optimizer 100 identifies isomorphic SESEs and stores variable values at the entries of these SESEs. Then, optimizer 100 identifies equivalent instruction sequences within single basic blocks or between multiple basis blocks (e.g., blocks 533, 534) of isomorphic SESEs. Preferably, optimizer 100 identifies equivalent instruction sequences by using an alphabet representation of instructions. Method 300 can also be expressed as follows: (1) Identify SESEs (e.g., A, B, C, D, E, F, G, H, I, J); (2) Assign SESE-levels lev and determine the number of sub-SESEs nc; (3) Identify isomorphic SESEs; (4) Identify equivalent instruction sequences in the isomorphic SESEs; and(5) Modify the isomorphic SESEs. FIG. 4 is a simplified diagram illustrating determining step 340 of method 300 by instruction sequence 1 10 ("INSTRUCTION"), event table 120 ("EVENT"), alphabet sequence 130 ("ALPHABET"), an instruction-event correspondence table 140 ("CORRESPOND"), updated correspondence table 140', and combination graphs 151-155. Instruction sequence 1 10 comprises instructions in assembly code, such as, for example the K = 10 instructions of block 536 explained above.

The instructions have (i) labels (e.g., "LDAA", "STAA") representing instruction commands and (ii) arguments (e.g., operands "#1", "varl") representing resources. Arguments can be, for example, numbers, variables, or constants well known in the art. As used herein, two instructions are equivalent when (a) both instructions have equal instruction commands and (b) both instructions use the same resource. The conditions (a) and (b) are conjunctively related ("and") and must be in compliance at the same time. Resources can be, for example, variables, absolute or relative constants, and numerical values stored in registers.

Event table 120 illustrates events by Arabic incrementing numbers: 1, 2, 3, 4, ... corresponding here to counter k. Conveniently, the events are timeslots, but this is not limited thereto. Alphabet sequence 130 comprises alphabet elements, e.g., "a" (131), "b" (132), "c" (133). The term "alphabet element" is intended to include any means for conveniently labeling instructions. Event table 120 can be considered as maintenance table which indicates the occurrence of instructions in time. Instruction-event correspondence table 140 comprises element "a" for events 1 , 5, and 9; element "b" for events 2, 3, 6, and 10; element "c" for events 4, 7, and 8. Table 140 is a sorted list (e.g., a, b, c order) which represents instruction occurrences within the structure. For example, the instructions "LDAA #1" (represented by element "a") and "LDAA #2" (element "c") each occur 3 times (each 3 "nodes" in table 140); and instruction "STAA varl" occurs 4 times.

Updated correspondence table 140' comprises element combinations (a,b) for event 2, (b,c) for event 4, (a,b) for event 6, (c,c) for event 8, and (a,b) for event 8. Table 140' is obtained by mapping which is explained in connection with FIG. 5. Optionally, "unique" combinations of alphabet element which occur, for example, only once in table 140 of table 140', can be neglected or disregarded in further analysis. For example, (b,c) and (c,c) occur only once (each one "node" in table 140'). This is an important feature and saves memory space. Short equivalent instruction sequences (e.g., (a,b) ) of equivalent instructions are detected at an early stage. This is an important advantage of the invention which limits complexity in computation time and space needed by the computer system.

The instructions are classified into a first set of multiple occurring sequences (e.g., a,b) and a second set of uniquely occurring instructions sequences (e.g., (b,c), (c,c) ). The uniquely occurring sequences are not considered later.

FIG. 5 is a simplified diagram illustrating mapping from instruction set 210 to alphabet set 220 and further to combination set 230. Instruction set 210 comprises all possible instructions which are defined for a given assembly language in all its combination. For simplicity, FIG. 5 illustrates instructions set 210 only with instructions "LDAA #1", STAA varl", "LDAA #2", and "LDB #3".

Alphabet set 220 comprises all alphabet elements, for example, "a", "b", "c" to "z". The use of a limited number of lowercase letters (e.g., 26 letters) is convenient for explanation, but not essential for the present invention. Alphabet set 220 can comprise more elements than illustrated. In reference to combination set 230, alphabet set is also referred to as 1 -tuple set. For convenience, alphabet elements "a", "b", and "c" which are used in the example of FIGS. 4-5 are illustrated bold. As illustrated by arrows 215, instruction set 210 maps to alphabet set 220. In reference to the example of FIG. 4, representative arrows 215 have plain lines, while others have dashed lines. Each instructions in set 210 is mapped to a single alphabet element in set 220.

Equivalent instructions in set 210 are mapped to the same alphabet element. For example, instruction "LDAA #1" is mapped to element "a"; instruction "STAA varl" is mapped to element "b"; instruction "LDAA #2" is mapped to element "c"; and instruction "LDB #3" is mapped to element "z". By further mapping (arrows 225), the alphabet elements are combined. For example, elements "a", "b", and "c" can be combined to 2-tuples (a,a), (a,b), (a,c), (b,a), (b,b), (b,c), (c,a), (c,b), and (c,c). Repetitions, for example (a,a), are allowed. Combination set 230 and 240 comprise pluralities of combinations of 2 or more alphabet elements, the n-tuples. Combination set 230 comprises 2-tuples, for example (a,b) and combination set 240 comprises 3-tuples, for example (a,b,a). The order of elements within the tuples is important. For example, 2-tuple (a,b) is different from 2-tuple (b,a). By further mapping (arrows 235), the 2-tuples of set 230 and the elements of set 220 are combined to 3-tuples of set 240. Or, in general, n-tuples and 1 -tuples are combined to (n+l)-tuples. In reference to the example of FIG. 4, "a" and "b" are mapped to (a,b); "b" and "c" are mapped to (b,c); and (a,b) and "c" are mapped to (c,a,b). Once equivalent instruction sequences have been detected (method 300), program modifications can be performed. As an example not intended to be limiting, code hoisting in portion 505 (SESE G) is explained.

FIGS. 6A-6B are a simplified flow chart diagrams of program portions 505 and 505', respectively, to illustrate method steps 340 and 350. Portion 505 is SESE G of FIG. 6 having entry line 503, exit line 504 at join point 522, branch point 512 and blocks 533 and 534. Block 534 comprises instructions "STAA varl" and "ADD varl, var2"; and block 533 comprises "STAA var2" and "ADD varl , var2". In step 340 of method 300, optimizer 100 detects "ADD varl, var2" as equivalent instructions in blocks 534 and 533. Optimizer 100 can modify portion 505 by hoisting "ADD varl , var2" after join point 522. Modified portion 505' comprises branch point 512 as before, modified block 534' with "STAA varl", modified block 533' with "STAA var2", join point 522', and new block 540 with "ADD varl , var2". Modified portion 505' is SESE G' which behaves like SESE G. For convenience of explanation, the example for portions 505 and 505' are explained in programming language. Assume that branch point 512 is controlled by variable x. Variable x is a data flow variable. For x > 0, block 534 is executed

(THEN) and for x < 0, block 533 is executed (ELSE). The other variables varl and var2 are not data flow variables. Portion 505 can be expressed as: begin portion 505 (line 503) (24)

601 if x < 0 jump to 605 (point 512) 602 STAA varl (begin of block 534) 603 ADD varl , var2 604 goto 606 (end of block 534 at line 522) 605 STAA var2 (begin of block 533) 606 ADD varl, var2 (end of block 533) end portion 505 (line 504)

Number 601-606 represent address lines. In determining step 340, optimizer 100 assigns alphabet elements to the instructions: begin portion 505 ( line 503 ) (25)

601 $ 602 b 603 c 604 $ 605 b 606 c end portion 505 ( line 504 )

Preferably, optimizer 100 assigns a special element (e.g., "$") to the branch points

(in lines 601 and 604) which are not checked for equivalency. Instruction sequence "ADD varl , var2" at address lines 603 and 606 is equivalent in blocks 534 and 533.

Once, the equivalent instruction sequences are detected, persons of skill in the art are able to modify portion 505. Modified portion 505' can have the following instructions: begin portion 505' (line 503) (26)

601: if x < 0 jump to 604 (point 512)

602: STAA varl (begin and end of block 534')

603: goto 605 604: STAA var2 (begin and end of block 533')

605: ADD varl, var2 (after point 522') end portion 505' (line 504)

Modified portion 505' has only 5 address lines 601-605 compared to 6 address lines 601-606 of portion 505. Having described the invention in connection with FIGS. 1-6, the present invention, can also be described as a method (e.g., method 300) for detecting equivalent instruction sequences when analyzing a program (e.g., program 500) with pluralities of branches (e.g., 51 1-515). Method steps are: • identifying single-entry- single-exit (SESE) structures in program 500; • identifying SESE-levels (lev) and identifying total numbers (nc) of sub-SESEs in the SESE-structures (cf. establishing tree step 320); • scanning SESE structures (cf. parsing step 330 and determining step

340) which have equal SESE-levels and equal total numbers of sub-SESEs for equivalent instruction sequences ("equal pairs") by

(a) assigning alphabet elements (e.g., 131 -133) to instructions wherein equal instruction receive equal alphabet elements;

(b) providing a sorted list of alphabet elements (e.g., table 140) which represents instruction occurrences in the SESE-structures;

(c) combining consecutive alphabet elements to n-tuples (cf. table 140') with initially n = 1 ; (d) with incrementing n (e.g., in FIG. 4 up to n = 2), providing further sorted lists, wherein multiple occurring n-tuples (e.g., (a,b) ) represent the equivalent instruction sequences (LDAA #1 , STAA varl).

Further, the present invention can also be described as a computer aided software engineering process (e.g., method 300 in optimizer 100) adapted to identify equivalent expression sequences in program 500 of assembly language expressions 550. The process comprises the steps of:

(a) establishing first structure representations in which jump expressions point only to further expressions inside the first structure representations (e.g., SESE structures);

(b) establishing further structures within the first structure (e.g., sub-SESEs); (c) repeating steps (a) and (b) to establish a hierarchical tree of structures (cf.

FIG. 2. SESE A of program 500) and sub-structures (e.g., SESE B to J) and assigning levels (lev) to each structure and sub-structure and determining the number (nc) of sub-structures for each structure; (c) scanning two or more structures having equal number of sub-structures and having equal levels for equivalent expression ("isomorphic structures") by

• in repetition, mapping expressions to alphabet elements and combination of alphabet elements (cf. FIGS. 4-5); • detecting combinations of equal alphabet elements as the equivalent expression sequences.

Still further, the present invention can be described as method to identify equivalent instructions in programs having the steps of: (a) establishing in a computer system 100 with which the program 500 in development is being analyzed, a tree representation (cf. FIG. 2) of program 500; (b) identifying first and second isomorphic structures (e.g., I and J) in the tree representation; and (c) determining equivalent instructions which belong to the first and second isomorphic structures (I and J) by replacing instructions of the instruction sequences by alphabet elements (e.g., "b" and "c"), providing event table 120, and mapping consecutively equivalent instructions to alphabet combinations in correspondence table 140. Compared to the prior art, the present invention has a series of advantages. For example, optimization can be performed without substantially recalculating data flow variables (such as x). Sequences which are compared can comprise branch instructions.

It is also an advantage, that data flow recalculation (i.e., data confirmation by checking data samples) is not required. During the transformation (sequence 1 10 to 130), the data represented by instructions themselves are not considered.

Since the meaning of instruction labels (e.g., STAA varl , LDAA #1) is ignored, the present invention can be applied to any assembly program and is independent from hardware platforms. The present invention has the advantage that optimization can be performed in the assembly language level, without the need to rewrite source code. The present invention can be used, for example, to optimize software for embedded systems. Method 300 of the present invention can optimize programs (e.g., program 500) on an application or file level. This is a convenient feature for the user. Also, program code which was originally generated for processors can be optimized for the use in embedded systems without looking at details.

Thus, while the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of program structure used in the practice of the invention which are particularly adapted for specific environments and operating requirements without departing from those principles. While the invention has been described in terms of particular structures, devices and methods, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow.

Summary of Notation

Address Line: A pointer indicating the location of an instruction in memory.

Alphabet Element: A representation for a single instruction. Alphabet Set: Plurality of alphabet elements. Basic Block: A series of instructions which are consecutively executed and which do not comprise jump instructions.

Control Variable: A variable acting on branches. Equivalent Instructions: Two or more instructions having equal command and resource. Equivalent Sequences: Two or more sequences in which all instructions are equivalent.

Expression: Synonym to Instruction. Instruction: Command which can be executed by a single processor cycle, an instructions having a command and a resource. Instruction Sequence: A series of > 1 instructions which are stored in consecutive memory line. Instructions of a sequence can be jump instructions so that the instruction can be executed at different times.

Instruction set: Plurality of all instructions including these occurring in the program, and all other combinations of commands and resources.

Join Point: In the graphical representation, the place where two or more different instructions meet; in the language representation, where two or more different instructions have common ends.

Jump: Change of a program flow from a current, first address line to second address line. Level: Number indicating the dependencies of SESEs within the program. Optimizer: The apparatus according to the invention which optimizes the program. Program: The software which is optimized. SESE: Sequence with Single-Entry-Single-Exit.

Tree: Graphical representation of the program.

Tuple: A series of alphabet elements.

Variable: A resource.

Claims

1. A method for detecting equivalent instruction sequences when analyzing a program with pluralities of branches, said method comprising the following steps: identifying single-entry-single-exit (SESE) structures in said program;

• identifying SESE-levels;

• identifying total numbers of sub-SESEs in said SESE-structures;

• scanning SESE structures which have equal SESE-levels and equal total numbers of sub-SESEs for equivalent instruction sequences by (a) assigning alphabet elements to instructions wherein equal instruction receive equal alphabet elements;

(b) providing a sorted list of said alphabet elements, said sorted list representing instruction occurrences in said SESE-structures;

(c) combining consecutive alphabet elements to n-tuples with initially n = 1 ; (d) with incrementing n, providing further sorted lists, wherein multiple occurring n-tuples represent said equivalent instruction sequences.

2. A computer aided software engineering process adapted to identify equivalent expression sequences in a program of assembly language expressions, the process comprising the steps of:

(a) establishing first structure representations in which jump expressions point only to further expressions inside said first structure representations;

(b) establishing further structures within said first structure;

(c) repeating steps (a) and (b) to establish a hierarchical tree of structures and sub-structures and assigning levels to each structure and sub-structure and determining the number of sub-structures for each structure; (c) scanning two or more structures having equal number of sub-structures and having equal levels for equivalent expression by

• in repetition, mapping expressions to alphabet elements and to combinations of alphabet elements;

• detecting combinations of equal alphabet elements as said equivalent expression sequences.

3. The process of claim 2 wherein in said mapping step, equivalent expressions are mapped to the same alphabet element.

4. The process of claim 2 wherein in said mapping step, uniquely occurring alphabet elements are disregarded.

5. A method for transforming a first basic block of instructions to a second basic block of instructions, said method having the step of: assigning single alphabet elements to each instruction of said first basic block, wherein equal alphabet elements are assigned to equal instructions; providing a correlation table of alphabet elements and instruction execution time, in said table, identifying strings of alphabet elements for consecutive execution time, wherein multiple occurring strings identify equivalent instruction sequences; and hoisting equivalent instruction sequences and obtain said second block.

6. The method of claim 5 wherein in said identifying step, said strings are initially n = 2 elements long.

7. A method to identify equivalent instructions in programs, the method comprising the steps of: establishing in the computer system with which the program in development is being analyzed, a tree representation of the program; identifying first and second isomorphic structures in the tree representation; and determining equivalent instructions which belong to said first and second isomorphic structures by replacing instructions of said instruction sequences by alphabet elements, providing an event table, and mapping consecutively equivalent instructions to alphabet combinations.