WO1999050894A1

WO1999050894A1 - Thin oxide film for augmenting anti-reflectivity and eliminating resist footing

Info

Publication number: WO1999050894A1
Application number: PCT/US1999/006050
Authority: WO
Inventors: Subash Gupta; Bhanwar Singh; Gurjeet Bains
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1998-03-27
Filing date: 1999-03-19
Publication date: 1999-10-07

Abstract

An anti-reflective coating structure includes a TiN layer (12) disposed on top of a metal interconnect layer (22), and an oxide layer (42) disposed on top of the TiN layer (12). The presence of the oxide layer (42) cuts down the reflectivity of the metal interconnect (22) to less than 5 %, and suppresses the formation of footings on the photoresist pattern (30). The oxide layer (42) also functions as a mask during the etching of the metal interconnect, because oxide has good etch selectivity with respect to metal in Cl2 plasma. Further, the oxide layer (42) improves the wafer reworking process, because it prevents any oxidation of the TiN layer (12) during stripping of the photoresist pattern (32) by ashing.

Description

THIN OXIDE FILM FOR AUGMENTING ANTI-REFLECTIVITY AND ELIMINATING RESIST FOOTING

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to process integration of integrated circuits (ICs) and more particularly to an anti-reflective coating structure and process that permit sub-0.4 micron patterning of an interconnect metal layer.

2. Description of the Related Art

Patterning of an interconnect metal layer employs optical lithography techniques. In this technique, a photoresist layer is deposited on top of the interconnect metal layer and patterned by passing light through a mask containing the interconnect pattern. Light reflections from the metal layer beneath the photoresist layer can, however, destroy the pattern resolution on the photoresist. Aluminum, which is typically employed as the material for the interconnect metal layer, is highly reflective, and tends to destroy the pattern resolution on the photoresist.

Therefore, for submicron patterning, an anti-reflective coating (ARC) is necessary. The ARC that is conventionally used is titanium nitride (TiN) . TiN reduces the reflectivity of the underlying interconnect metal. In the case of Al, the reduction is from 80-90% to 25-30%. For sub-0.4 micron patterning, however, a reflectivity of 25-30% is still too high to give reproducible images. Moreover, deep ultraviolet (DϋV) photoresist, e.g., Apex, that is used for sub-0.4 micron patterning is prone to react with the nitrogen (N) in the TiN layer and form "resist footings." This effect is commonly known as "resist poisoning." Figure 1A illustrates the conventional ARC structure, which includes a TiN layer 10 disposed on top of a metal layer 20 which is to be patterned. Figure 1A also illustrates a photoresist 30 deposited on top of the TiN layer 10. The photoresist 30 is shown with resist footings 40 that form when the photoresist 30 reacts with the N in the TiN layer 10 during exposure and development of the photoresist layer.

For patterning of the metal layer 20, the structure shown in Figure 1A is etched. During this process, the footings 40 formed at the photoresist 30 translate downwards to cause footings 41 to be formed at the metal layer 20 (see Figure IB) . These footings 41 destroy interconnect pattern resolution and make the conventional process unsuitable for sub-0.4 micron patterning of the metal layer 20.

Bencher et al., in "Dielectric antireflective coatings for DUV lithography," Solid State Technology, March 1997, pp. 109-114, propose a SiO_xN_y layer 11 to be used as the ARC material in lieu of TiN. See Figure 2. However, the dielectric constant of this layer, which is about 6-7, is high, and thus not desirable to leave over the metal layer 20, especially in logic technologies. Additionally, the etch selectivity of SiO_xN_y used as ARC layers with respect to Al in Cl₂ plasma, which is about 4-5, is not very good and, as a consequence, thinning of the photoresist is not possible.

The conventional ARC structure also poses problems during reworking of the wafer. In the conventional process, when it is discovered that the pattern of the photoresist 30 is not desirable, the photoresist 30 is stripped and a new layer is spin-coated to be patterned once again using optical lithography techniques. The stripping of the photoresist 30 is carried out by ashing, i.e., exposure to 0₂ plasma. However, ashing may partially oxidize the surface of TiN layer 10 and cause adhesion problems between the new layer of photoresist and the TiN layer 10. Further, the step of etching to form the interconnect pattern on the metal layer 20 becomes more difficult, because it is harder to etch a partially oxidized TiN layer 10. SUMMARY OF THE INVENTION

An object of this invention is to provide an anti- reflective coating structure that reduces the reflectivity of the interconnect metal sufficiently such that sub-0.4 micron geometries can be patterned on the interconnect metal layer with optical lithography techniques.

Another object of this invention is to provide an anti-reflective coating structure that eliminates the resist footing problem.

Still another object of this invention is to provide an anti-reflective coating structure that has a relatively low dielectric constant.

Still another object of this invention is to provide an anti-reflective coating structure that functions as a mask during etching of the metal interconnect layer.

Still another object of this invention is to provide an anti-reflective coating structure that facilitates reworking of the wafer. Still another object of this invention is to provide a method of patterning the metal interconnect layer having sub-0.4 micron geometries with an anti-reflective coating structure with a relatively low dielectric constant. The above and other objects of the invention are accomplished with an anti-reflective coating structure having a TiN layer disposed on top of an Al interconnect layer and an oxide layer disposed on top of the TiN layer. The presence of the oxide layer cuts down the reflectivity of Al to as low as 2-3%. The photoresist layer is deposited on top of the oxide layer, but no resist footing is formed by a reaction between the photoresist and TiN because the oxide layer isolates the photoresist layer from the TiN layer.

The oxide layer is further advantageous because it functions as a mask during the etching of the metal interconnect, because oxide has good etch selectivity with respect to metal in Cl₂ plasma. The etch selectivity of oxide with respect to Al in Cl₂ plasma is about 10-15. By comparison, the etch selectivity of SiO_xN_y with respect to Al in Cl₂ plasma is only about 4-5. Therefore, a thinner photoresist can be provided with the invention than in the prior art. Finally, the dielectric constant of the resulting structure is only about 4, compared to about 6-7 when SiO_xN_y is used as an ARC layer.

The oxide layer also provides benefits during reworking of the wafer. With the invention, the reworking process is improved because the oxide layer deposited on top of the TiN layer prevents any oxidation of the TiN layer during the stripping of the photoresist 30. As a result, adhesion problems of a newly spin-coated layer of photoresist and etching complications are prevented. Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in detail herein with reference to the drawings in which:

Figure 1A illustrates a first conventional anti- reflective coating structure; Figure IB illustrates a metal interconnect pattern formed from the first conventional anti-reflective coating structure;

Figure 2 illustrates a second conventional anti- reflective coating structure; Figure 3 illustrates an anti-reflective coating structure according to the invention;

Figures 4A-4F illustrate the process steps of patterning the interconnect metal using the anti-reflective coating structure according to the invention; and Figure 5 shows how, in the anti-reflective coating according to the invention, the reflectivity of the metal layer varies with respect to the thickness of the oxide layer .

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred exemplary embodiments of the invention, and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As illustrated in Figure 3, an anti-reflective coating structure according to the invention includes an ARC layer 12 disposed on top of a conductive layer 22 to be patterned, and an oxide layer 42 disposed on top of the ARC layer 12. Figures 4A-4F illustrate the process steps of patterning the conductive layer 22 using the anti-reflective coating structure according to the invention.

Figure 4A illustrates the ARC layer 12 disposed on top of the conductive interconnect layer 22. The ARC layer 12 is deposited on top of the conductive layer 22 by conventional methods. The ARC layer 12 is preferably TiN and has a thickness of 1100 A. The conductive layer 22 is preferably Al and has a thickness of 5000 A.

Figure 4B illustrates the oxide layer 42 disposed on top of the ARC layer 12. Preferably, the oxide layer 42 is tetraethyl orthosilicate (TEOS) and deposited on top of the ARC layer 12 by chemical vapor deposition (CVD) to a thickness range between 300 A and 400 A. Although the preferred thickness range is between 300 A and 400 A, the invention also covers a thickness range between 175 A and 500 A.

Figure 4C illustrates a layer of photoresist 32 disposed on top of the oxide layer 42. For patterning sub- 0.4 micron geometries, DUV photoresist UV05 is used. The DUV photoresist is spin coated on top of the oxide layer 42 to a thickness of about 8300 A. The photoresist 32 is then

5 patterned by (i) exposing light through a mask 50 shown in Figure 4D, and (ii) developing the photoresist 32. The patterned photoresist 32 is illustrated in Figure 4E.

The patterned photoresist 32 is then examined for resolution quality. If the resolution quality is determined to be poor, then the wafer is reworked. The reworking process includes the steps of (i) stripping the patterned photoresist 32 by ashing, i.e., exposure to 0₂ plasma, (ii) spin-coating a new layer of photoresist on top of the oxide layer 42, (iii) exposing the new photoresist layer through a mask, and (iv) developing the new photoresist layer. The examination for resolution quality of the new photoresist pattern is carried out again and the reworking process is repeated until the resolution quality is found to be acceptable . After patterning of the photoresist 32, the oxide layer 42 is first etched. Then, the ARC layer 12 and the conductive layer 22 are etched in Cl₂ plasma, and the photoresist 32 is stripped. The resulting structure is illustrated in Figure 4F. When the conductive layer 22 is Al, Cl₂ plasma is selected as the etching medium for the ARC layer 12 and the conductive layer 22, because the etch selectivity between the oxide layer 42 and Al in Cl₂ plasma, about 10-15, is good.

Sub-0.4 micron geometries can be patterned by the above-described process for the following reasons. First, the presence of the oxide layer augments the anti- reflectivity of the ARC layer. In the case of a TEOS layer of a thickness between 175 A and 500 A, the reflectivity of the underlying conductive layer can be reduced to about 20% or less. In the preferred thickness range between 300 A and 400 A, the reflectivity of the underlying conductive layer can be reduced to as low as about 2-3%. See Figure 5.

Second, the anti-reflective coating structure according to the invention has no interface between the photoresist 32 and the ARC layer 12. As a result, when TiN is used as the ARC layer 12, no resist footing is formed by a reaction between the photoresist 32 and TiN.

Third, oxide has good etch selectivity with respect to Al in Cl₂ plasma, about 10-15. By comparison, the etch selectivity of SiO_xN_y with respect to Al in Cl₂ plasma is only about 4-5. Therefore, a thinner photoresist can be provided with the anti-reflective coating structure according to the invention. The thinner photoresist permits the design of even finer geometries.

Fourth, during the photoresist stripping step of the reworking process, the TiN layer 12 is not exposed to the 0₂ plasma used for the photoresist stripping because of the presence of the oxide layer 42. Therefore, any oxidation of the TiN layer 12 is suppressed, and the adhesion and etching problems associated with the conventional ARC structure are prevented. While particular embodiments according to the invention have been illustrated and described above, it will be clear that the invention can take a variety of forms and embodiments within the scope of the appended claims.

Claims

WE CLAIM :

1. A semiconductor structure for reducing reflectivity of a conductive layer (22) to be patterned, comprising: an anti-reflective coating layer (12) disposed on top of the conductive layer (22); and an oxide layer (42) disposed on top of the anti- reflective coating layer (12) .

2. The semiconductor structure as recited in claim

1, wherein the anti-reflective coating layer (12) comprises TiN.

3. The semiconductor structure as recited in claim

2, wherein the oxide layer (42) comprises TEOS.

4. The semiconductor structure as recited in claim 3, wherein the oxide layer (42) has a thickness of about 175 - 500 A.

5. The semiconductor structure as recited in claim

3, wherein the oxide layer (42) has a thickness of about 300 - 400 A.

6. A semiconductor structure comprising: an anti-reflective coating layer (12) disposed on top of a conductive layer (22) to be patterned; an oxide layer (42) disposed on top of the anti- reflective coating layer (12) ; and a photoresist layer (32) disposed on top of the oxide layer (42) .

7. The semiconductor structure as recited in claim

6, wherein the anti-reflective coating layer (12) comprises TiN .

8. The semiconductor structure as recited in claim

7, wherein the oxide layer (42) has a thickness of about 175

- 500 A.

9. The semiconductor structure as recited in claim

7, wherein the oxide layer (42) has a thickness of about 300

- 400 A.

10. The semiconductor structure as recited in claim

6, wherein the photoresist (32) is separated from the anti- reflective coating layer (12) by the oxide layer (42).

11. A method of patterning a conductive layer, said method comprising the steps of: depositing an anti-reflective coating layer (12) on top of the conductive layer (22); depositing an oxide layer (42) on top of the anti-reflective coating layer (12); depositing photoresist (32) on top of the oxide layer (42) ; patterning the photoresist (32) ; and etching portions of the oxide layer (42), the anti-reflective coating layer (12), and the conductive layer (22).

12. The method as recited in claim 11, wherein the step of depositing the oxide layer (42) includes the step of depositing TEOS to a thickness of about 300 - 400 A.

13. The method as recited in claim 11, wherein the step of patterning the photoresist (32) includes the steps of: exposing the photoresist (32) through a mask (50) ; and developing and chemically removing the exposed portions of the photoresist (32) .

14. The method as recited in claim 11, wherein the step of etching includes the steps of: etching the oxide layer (42); selecting an etching medium with an etch selectivity between the oxide layer (42) and the conductive layer (22) that is equal to or better than about 10; and etching the anti-reflective coating layer (12) and the metal layer (22) using the selected etching medium.

15. The method as recited in claim 11, wherein the step of patterning the photoresist (32) includes the step of determining whether the photoresist pattern is acceptable.

16. The method as recited in claim 15, wherein, if the photoresist pattern is determined not to be acceptable, stripping the photoresist pattern, spin-coating a new layer of photoresist on top of the oxide layer (42), exposing the new photoresist layer through a mask, developing the new photoresist layer to form a new photoresist pattern, and determining whether the new photoresist pattern is acceptable .

17. The method of augmenting anti-reflectivity of an anti-reflective coating layer (12) that is disposed on top of a conductive layer (22) to be patterned, said method comprising the step of depositing an oxide layer (42) on top of the anti-reflective coating layer (12) prior to the step of patterning the conductive layer (22) .

18. The method as recited in claim 17, further comprising the step of patterning the conductive layer (22) wherein the step of patterning the conductive layer (22) includes the steps of: disposing a photoresist (32) on top of the oxide layer (42);

10 patterning the photoresist (32); etching the oxide layer (42) ; and etching the anti-reflective coating layer (12) and the conductive layer (22) .

19. The method as recited in claim 17, wherein the step of disposing the photoresist (32) includes the step of disposing the photoresist (32) on top of the oxide layer (42) and to be separate from the anti-reflective coating layer (12) .

20. The method as recited in claim 17, further comprising the step of selecting an etching medium with an etch selectivity between the oxide layer (42) and the conductive layer (22) that is equal to or better than about 10, wherein the step of patterning the conductive layer (22) includes the step of etching the conductive layer (22) in the selected etching medium.

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