WO1999015908A1 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Method for manufacturing semiconductor integrated circuit device Download PDF

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Publication number
WO1999015908A1
WO1999015908A1 PCT/JP1998/004226 JP9804226W WO9915908A1 WO 1999015908 A1 WO1999015908 A1 WO 1999015908A1 JP 9804226 W JP9804226 W JP 9804226W WO 9915908 A1 WO9915908 A1 WO 9915908A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
manufacturing
solder
Prior art date
Application number
PCT/JP1998/004226
Other languages
French (fr)
Japanese (ja)
Inventor
Hideo Arima
Kenichi Yamamoto
Akio Hasebe
Kenichiro Morinaga
Kunihiko Nishi
Masanori Shibamoto
Kazuma Miura
Yuji Wada
Susumu Kasukabe
Koji Serizawa
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP51880899A priority Critical patent/JP3741222B2/en
Publication of WO1999015908A1 publication Critical patent/WO1999015908A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to an electronic component, a connection terminal, a socket, and a board capable of electrically contacting and separating with an electronic circuit in a manufacturing technology of a semiconductor integrated circuit device, and particularly to an inspection and a test of an electronic component and a circuit of a fine pitch.
  • the present invention relates to connection technology for connection terminals, sockets, and boards that can be connected at a fine pitch for performing such operations.
  • Yada's Japanese Patent Application Laid-Open No. 8-304446 discloses that tin, an alloy thereof, an indium bump and the like are formed on a nickel plating layer on a printed wiring such as copper and a pad portion further formed with a gold plating layer.
  • a contact burn-in method is disclosed.
  • a CSP Chip Size Package
  • CSP is a type of BGA (Ball Grid Array) in which the terminals are formed in an area array, and has a finer pitch than normal BGA.
  • BGA Bit Grid Array
  • products with a 0.5 mm pitch have begun to appear on the market, but this pitch is in the trend of becoming even finer.
  • the method implemented by BGA etc. uses Au A large number of wires are buried in a certain direction, and the connection between the solder balls, which are the terminals of the CSP, and the pads of the circuit board placed under the silicone rubber sheet is secured through this silicone rubber sheet. .
  • This method has the following four disadvantages.
  • the low-molecular silicone resin adheres to the solder balls, etc., because the CSP solder balls that make up the product are in direct contact with the silicone rubber.
  • high-temperature treatment such as burnin is performed, a large amount of low-molecular silicone resin adheres to the solder ball surface. This causes a connection failure when the CSP is mounted on a substrate or the like.
  • the object of the present invention is to (1) improve the alignment accuracy, (2) reduce the cost, (3) can be used repeatedly, and (4) prevent contamination of the connection part even when used at a high temperature. That is.
  • connection terminal structure that has a structure in which conductive particles are fixed to the conductor surface of the terminal with solder or brazing material, and secures electrical connection by contact.
  • the terminal is composed of a plurality of terminals arranged in a plane, and the terminal and the wiring from the terminals form a planar circuit board, and the terminal to be connected is formed on the circuit board.
  • It has a socket structure that mounts the parts or circuits it has and holds it on the circuit board. Further, the socket was mounted on a large circuit board to form a board.
  • it has a structure in which conductive particles are fixed to the conductor surface of the terminal with solder or brazing material, and a connection terminal structure that ensures electrical connection by contact. With this structure, the rubber sheet containing the wire is not interposed between the terminal and the connected terminal, or the solder ball in the CSP, and the positioning accuracy between the connected terminal and the connector is improved.
  • the conductive particles do not spread between the terminals other than the terminals compatible with the solder or brazing material, so that no short circuit occurs between the terminals. Since the conductive particles need only be fixed with solder or the like as a terminal, there is no need for a complicated operation of arranging wires in a certain direction at high density in the rubber, so that connection can be secured at low cost. Further, since the connector has a strong structure in which the conductive particles are fixed by solder or the like, the connector can be used semipermanently repeatedly. In addition, there is no substance between the terminal and the contact element that pollutes the contact element, and it can be used even at high temperatures. Also, in the case of sockets and boards, terminals with these characteristics are used, as in the above, high alignment accuracy, low cost, repetitive use, and contamination at high temperatures even at high temperatures. There will be no sockets and boards.
  • a method for manufacturing a semiconductor integrated circuit device including the following steps;
  • a semiconductor integrated circuit chip or a chip-lead complex for example, a part excluding a solder hole BGA package body, that is, a solder ball
  • a main part of the semiconductor integrated circuit device for example, a chip or a package body including the chip.
  • Solder bumps for example, eutectic solder balls formed on the electrodes
  • the bump formation part for example, bump forming electrodes provided on the lower surface of the chip lead composite
  • the method of manufacturing a semiconductor integrated circuit device according to the present invention wherein the metal particles have a main area (For example, the main body, that is, a part except a surface coat, etc.) is made of nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum, or an alloy containing at least one of these as a main component. is there.
  • the metal coating layer (for example, a plating layer having a thickness of about 0.1 ⁇ ) may be formed of rhodium, gold, silver, tin, lead, indium, white gold, or the like. Or palladium or an alloy containing at least one of these as a main component.
  • the average particle diameter of the metal particles is 3 ⁇ m to 50 ⁇ m.
  • the chip lead composite is a CSP package (for example, micro BGA, WPP, etc.).
  • the wiring board is a film-shaped wiring board or a film wiring sheet.
  • the metal particles have a main region made of nickel or an alloy containing nickel as a main component.
  • the metal coating layer is made of rhodium or an alloy containing rhodium as a main component.
  • the average particle diameter of the metal particles is from 10 ⁇ m to 40 ⁇ m.
  • a method for manufacturing a semiconductor integrated circuit device including the following steps;
  • solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are placed on the first main surface of the film wiring board.
  • (C) a step of determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
  • the metal particles have a main area of nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum, or at least one of them. It is composed of an alloy as a main component.
  • the metal coating layer comprises rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of them as a main component. It is made of an alloy that has
  • a method for manufacturing a semiconductor integrated circuit device including the following steps;
  • solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are provided on the first main surface of the wiring board;
  • the main area of the metal particles is nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum. It is made of den or an alloy containing at least one of them as a main component. 19. The method for manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a metal coating layer on the surface thereof, which is less likely to react with the solder of the solder bumps than the components constituting the main region. .
  • the metal coating layer may include rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of them as a main component. It is made of an alloy that has
  • connection terminal has a structure in which conductive particles are fixed to the conductor surface of the connection terminal with solder or brazing material. The electrical connection is ensured by contact with the device.
  • the base material of the conductive particles is at least one of Ti, Cr, Co, Ni, Fe, Cu, W, and Mo. It consists of one or more types.
  • the method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of:
  • the conductive particles have an average particle size of 50 ⁇ m or less and 3 ⁇ m or more.
  • connection terminal may be configured such that conductive particles are fixed to a conductor surface of the connection terminal with solder or brazing material, and the connection is performed while leaving a tip of the conductive particle.
  • the surface of the terminal is covered with an insulating film.
  • the socket may include a connection terminal and a connected terminal to be connected to the connection terminal, the connection terminal being overlapped with the socket, and a pressure applied between the two connection terminals. And a mechanism.
  • An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which realizes an improvement in alignment accuracy and a reduction in cost.
  • Still another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can be used repeatedly and does not contaminate a connection portion even when used at a high temperature.
  • FIG. 1 is a plan view and a sectional view showing the structure of the connection terminal according to the first embodiment of the present invention
  • FIG. 2 is a plan view and a sectional view showing the structure of the connection terminal according to the second embodiment of the present invention
  • FIG. FIG. 4 is a plan view showing the structure of a connection terminal according to a third embodiment of the present invention
  • FIGS. 4 to 7 are configuration diagrams of an embodiment of a socket having the connection terminal according to the present invention
  • FIG. Fig. 9 is a plan view showing the structure of the burn-in board provided.
  • Fig. 9 is a cross-sectional view of an embodiment in which a BGA semiconductor package using solder balls is connected to the board via connection terminals.
  • Fig. 10 shows the use of solder balls.
  • FIG. 9 is a cross-sectional view of an embodiment in which a BGA semiconductor package using solder balls is connected to the board via connection terminals.
  • Fig. 10 shows the use of solder balls.
  • FIG. 11 is a cross-sectional structure diagram of an embodiment in which the BGA semiconductor package is connected to a board via connection terminals.
  • FIG. 11 is a plan view showing a structure of a module according to an embodiment including connection terminals and a socket of the present invention.
  • Fig. 12 shows the connection terminals and socket of the present invention.
  • FIG. 13 is a plan view and a cross-sectional view showing the structure of the module according to the embodiment
  • FIG. 13 is a schematic cross-sectional view showing details of the terminal connection structure of the present invention
  • FIG. Fig. 5 is a schematic cross-sectional view showing the basic structure of a fan-out type CSP that is the subject of the present invention.Fig.
  • FIG. 16 is a schematic cross-sectional view showing the basic structure of the WPP, that is, the wafer process package, that is the subject of the present invention.
  • Figure 17 is a schematic cross-sectional view showing the basic structure of bare chip mounting that is the subject of the present invention
  • Figure 18 is the BGA, that is, the Micro-Bal 1 Grid Array that is the subject of the present invention. It is a schematic cross section which shows the basic structure of. BEST MODE FOR CARRYING OUT THE INVENTION
  • the number of elements (including the number, numerical value, amount, range, etc.) ) Is not limited to the specified number, except where it is explicitly stated or limited in principle to a specific number, and may be more than or less than the specified number.
  • constituent elements are not necessarily essential unless otherwise specified or considered to be essential in principle. Needless to say.
  • semiconductor integrated circuit device refers not only to a device formed on a silicon wafer, but also to a device formed on another substrate such as a TFT liquid crystal, unless otherwise specified. Shall be included.
  • wafer or semiconductor wafer is not limited to a single-crystal silicon wafer or the like, but may be used for manufacturing an insulating substrate on which a semiconductor integrated circuit device is integrated or a partial semiconductor substrate integrated circuit. It also includes a substrate and the like.
  • burn-in test in the present application includes not only an accelerated test by heating and a screening test, but also an aging test and the like for examining a product for potential defects by applying stress.
  • wiring board used in the present application includes not only a board made of glass epoxy, ceramic or the like but also having a wiring pattern equivalent thereto, or a board having a wiring pattern such as a copper film arranged on a polyimide film. .
  • chip-lead complex refers to not only an assembly including a semiconductor integrated circuit chip and a group of leads separated from a lead frame electrically connected thereto but also various CSPs. It also includes an assembly structure including a chip and a lead electrode electrically connected to the chip, such as a wafer process package.
  • solder in the present application includes not only lead-tin eutectic solder but also tin-gold solder, high-temperature solder, tin solder, and other brazing metal alloys having a melting point of 450 ° C or less. .
  • binder layer includes not only a solder layer but also an organic resin such as an epoxy resin adhesive layer.
  • FIG. 1 shows a plan view and a sectional view showing the structure of the connection terminal.
  • the cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view.
  • Lead 1 is a copper lead with eutectic solder applied.
  • a copper powder having an average particle size of 50 ⁇ was fixed with solder to form a connection terminal 2. This is done by immersing the tip of the lead 1 in a paste containing a mixture of copper powder and flat powder of a predetermined depth, heating the lead with the copper particles attached, and applying a plurality of copper particles to the tip of the lead 1 by heating. Fixed.
  • These leads 1 were put into a mold mold and resin was injected to form a lead fixing resin frame 3.
  • connection terminal 2 At the time of molding, the lead 1 is formed into a predetermined shape.
  • the fixing screw 4 has a component holding plate 5.
  • a semiconductor package 6 having, for example, solder balls 7 as terminals to be connected is placed inside the lead fixing resin frame 3, and the back surface of the package is fixed with four component holding plates 5 for use.
  • the connection terminal 2 By employing the connection terminal 2 having this structure, the connection terminal 2 can be realized at a lower cost than the conventional connection terminal using a pin containing a panel.
  • FIG. 2 shows a plan view and a sectional view showing the structure of another connection terminal.
  • the cross-sectional view shows a cross-sectional structure of a portion ⁇ —A ′ in the plan view.
  • the connection terminal 2 is formed on an alumina substrate 8.
  • the formation method was the same as that of the lead-out wiring 9 and the lead-out terminal 10 by using a thick film printing technique. Specifically, it was manufactured as follows. An alumina substrate 8 having four fixing holes 12 for fixing a ceramic package 13 to be measured was used. On this, lead-out wiring 9, connection terminal 2, and lead-out terminal 10 are formed by screen printing technique using silver-palladium paste. The lead terminals 10 are further overcoated with gold paste. This was heated at 900 ° C using a belt furnace. Baking.
  • tin-silver particles, gold-plated tungsten powder with an average particle size of 30 / m, flux resin particles, and a paste made by mixing a solvent are overcoated on the connection terminals 2 and In a 800 ° C. belt furnace, the tungsten particles were fixed with a tin-silver brazing filler metal. Finally, a ceramic guide 11 was fixed with a ceramic adhesive.
  • connection terminal 2 is used by mounting the ceramic package 13 to be measured at the mounting position 16 of the component to be measured, placing the lead 14 of the ceramic package 13 on the connection terminal 2, Fix the lead using two copper holding rods 15 and screws inserted into the fixing holes 12.
  • connection terminal 2 By using the connection terminal 2, it was possible to evaluate various characteristics including the reliability of the ceramic package 13 to be measured up to 20 ° C. This realizes a connection terminal 2 that has low cost, high durability, high reliability, and can be used semi-permanently by replacing the device under test, compared to the conventional connection terminal that uses a pin containing a panel. did it.
  • connection terminals 2 were also formed by using molybdenum, titanium, and chromium powders in addition to the tungsten powder. In these cases, the same characteristics as in the case of the tungsten powder can be obtained.
  • FIG. 3 is a plan view showing the structure of another connection terminal.
  • the connection terminal 2 is formed on a flexible tape circuit 17 of about 45 mm square.
  • the fabrication was performed using the same photolithography technology as that of a normal flexible printed circuit (FPC).
  • the insulating film material of the circuit was polyimide, and the lead-out wiring 9, the lead-out terminal 10, and the connection terminal 2 were formed of copper.
  • the lead terminal 10 was further plated with nickel and gold on copper. Nickel particles with an average particle size of 25 ⁇ m, which were rhodium-plated with eutectic solder, were fixed on the copper of connection terminal 2.
  • a resist film was coated on the lead wiring 9.
  • the connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 152 terminals.
  • a solder ball terminal of a 152-pin BGA semiconductor package is connected on the connection terminal 2 at a pitch of 0.5 mm.
  • the BGA is located at position 16 Mount and fix to tape circuit 17 with a total weight of 300 g.
  • the lead terminals 10 arranged on the outer periphery of the tape have a width of 0.5 mm, a length of 2 mm, and a pitch of 1.0 mm.
  • FIG. 4 shows a cross-sectional view of the socket 25 using the connection terminal 2 of FIG. Place the flexible tape circuit 17 on which the connection terminal 2 is formed on the socket base 18 and fix it. Place the package guide 19 of the socket 25 on this tape circuit and fix it with the guide bin 24. There, a BGA type semiconductor package 6 with solder balls 7 to be connected is mounted. A socket cover 22 to which the package retainer 20 is fixed with the press panel 21 is put thereon. Specifically, the guide bin 24 is inserted into the guide bin hole 23 formed in the socket lid 22 and fixed.
  • connection resistance value between them could be set to 0.2 ⁇ at the maximum. This has facilitated the measurement of the characteristics of fine pitch BGA, which was conventionally difficult to evaluate.
  • the socket 25 on which the connection terminal 2 on the tape circuit is mounted can carry out burn-in of BGA.
  • the temperature was raised to about 130 ° C including the tape circuit 17, and the operation was continued for about 8 hours.
  • thermal deformation of the BGA solder ball occurred, but the connection resistance value between the connection terminal 2 and the BGA solder ball could all be maintained at 0.5 ⁇ or less.
  • the connection terminal 2 has high durability, high reliability, and a connection terminal that can be used semi-permanently by replacing the device under test.
  • connection terminal 2 was formed using cobalt powder or iron powder in addition to nickel powder. In these cases, the same characteristics as those of the nickel powder could be obtained as described above.
  • connection terminal 2 portion of the tape circuit 17 in FIG. 3 was further coated with an epoxy resin, and the connection terminal 2 was manufactured by applying pressure and heating from above.
  • the connection terminal 2 has a structure in which nickel particles are fixed with resin in addition to solder. The head of the nickel particles appears in the table because the resin moves to the side during pressurization. (Embodiment 5)
  • a socket similar to that shown in FIG. 4 and having an elastic film having a thickness of 0.3 mm formed under the flexible tape circuit 17 was manufactured.
  • the total power of BGA was 200 g.
  • connection resistance value between the connection terminal 2 and the BGA solder terminal at room temperature could be at most 0.2 ⁇ .
  • the temperature was raised to about 130 ° C, including the tape circuit 17 and socket 25, and the device was operated continuously for about 8 hours. At this time, there was almost no thermal deformation of the BGA solder ball, and all the connection resistance values between the connection terminal 2 and the BGA solder ball were able to secure 0.5 ⁇ or less.
  • connection terminal 2 has high durability and high reliability, and the connection terminal 2 that can be used semi-permanently by replacing an object to be measured can be realized.
  • nickel-plated nickel particles were applied to the connection terminals 2, but in addition to gold-plated, silver, tin, lead, indium, rhodium, platinum, and palladium The resistance value was about the same as the gold plating. As a result, it was confirmed that not only gold plating but also silver, tin, lead, indium, rhodium, platinum, and palladium can be applied as plating.
  • FIG. 5 shows a cross-sectional view and a plan view illustrating the structure of a socket 25 having another connection terminal.
  • the cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view.
  • the socket 25 has a structure in which four BGA type semiconductor packages 6 as components to be measured can be mounted.
  • connection terminal 2 is formed on a flexible tape circuit 17 of about 70 mm square. Fabrication was performed using the same photolithography technology as that of a normal flexible printed circuit (FPC).
  • the insulating film material of the circuit was polyimide, and the outgoing wiring 9, the outgoing terminal 10, and the connecting terminal 2 were formed of copper.
  • the lead terminal 10 was further plated with nickel and gold on copper. Eutectic is on the copper of connection terminal 2 Nickel particles having an average particle size of 25 / zm attached to rhodium were fixed.
  • a resist film was coated on the lead-out wiring 9.
  • the connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, and are arranged in two rows, with a total of 152 pieces for one BGA and a total of 608 pieces for four BGAs. is there.
  • connection terminal 2 On this connection terminal 2, four solder ball terminals of a 152-pin BGA semiconductor package with a pitch of 0.5 mm are connected.
  • the BGA is mounted on the component to be measured mounting position 16 and fixed to the tape circuit 17 with a total weight of 800 g.
  • the opening and closing of the socket lid 22 is integrated with the package guide 19 and the hinge 26, and the lid 22 can be fixed with the lock 27 when the lid 22 is closed. It has a structure. Further, in this socket 25, an elastic film 28 was provided below the tape circuit 17 as in the fifth embodiment.
  • connection terminal 2 formed on this tape circuit By using the connection terminal 2 formed on this tape circuit, all the connection resistance values between the BGA solder ball 7 and the connection terminal 2 could be secured, and the maximum value was 0.2. This has made it easier to measure the characteristics of fine pitch BGA, which was difficult to evaluate in the past.
  • the connection terminal 2 on this tape circuit was also able to perform BGA burn-in. During burn-in, the temperature was raised to about 130 ° C, including the tape circuit 17, and operation was continued for about 8 hours. At this time, although the solder ball 7 of the BGA was thermally deformed, the connection resistance value between the connection terminal 2 and the solder ball 7 of the BGA could all be kept below 0.5 ⁇ .
  • connection terminal 2 has high durability and high reliability, and has realized a connection terminal 2 that can be used semi-permanently by replacing an object to be measured.
  • FIG. 6 shows a cross-sectional view and a plan view illustrating the structure of a socket having another connection terminal.
  • the cross-sectional view shows the cross-sectional structure taken along the line AA ′ in the plan view.
  • the socket 25 has a structure in which one tape circuit 17 has four sets of package guides 19, a package holder 20, and a socket cover 22. BGA can be mounted.
  • the connection terminal 2 is formed on a flexible tape circuit 17 having a width of about 45 mm and a length of about 280 mm.
  • the formation method is the same as a normal flexible printed circuit (FPC). It was manufactured using a similar photolithography technique.
  • the insulating film material of the circuit was polyimide, and the lead wiring 9, the lead terminal 10 and the connection terminal 2 were formed of copper.
  • the lead terminal 10 was further plated with nickel and gold on copper. Nickel particles having an average particle size of 25 / xm fixed to rhodium with eutectic solder were fixed on the copper of the connection terminal 2.
  • the lead film 9 was covered with a resist film.
  • the connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, and are arranged in two rows, a total of 15 2 with one 80, and a total of 60 with 4 BGAs. There are eight.
  • connection terminal 2 On this connection terminal 2, a solder ball terminal of a 152-pin BGA semiconductor package is connected at a pitch of 0.5 mm.
  • Each BGA is mounted on the component to be measured mounting position 16 and fixed to the tape circuit 17 by applying a weight of 200 g.
  • connection terminals 2 formed on the tape circuit By using the connection terminals 2 formed on the tape circuit, all the connection resistance values between the BGA solder balls and the connection terminals 2 could be secured, and the maximum value was 0.2 ⁇ . This makes it easy to measure the characteristics of fine pitch BGA, which was difficult to evaluate in the past.
  • the connection terminal 2 on this tape circuit was able to carry out BGA burn-in. In the burn-in, it was raised to about 13 including the tape circuit 17 and operated continuously for about 8 hours. At this time, the solder ball 7 of BGA was thermally deformed, but the connection resistance value between the connection terminal 2 and the solder ball 7 of BGA was all less than 0.5 ⁇ . As a result, burn-in of fine pitch BGA, which was difficult in the past, can be performed at the mass production level.
  • the connection terminal 2 has high durability and high reliability, and the connection terminal 2 that can be used semi-permanently by replacing the device under test can be realized.
  • FIG. 7 shows a cross-sectional view and a plan view illustrating the structure of a socket 25 having another connection terminal.
  • the cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view.
  • the basic structure of this socket 25 is similar to that of the seventh embodiment. The differences are the following two points.
  • the external shape of the socket 25 including the tape circuit 17 is about 45 mm square, one socket 25 has a structure that can mount one BGA, and the drawer terminal of the tape circuit 17
  • Reference numeral 10 denotes a point bent and fixed to the back surface of the socket, and a structure similar to that of the connection terminal 2 is provided on the surface of the lead terminal 10.
  • connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 1 52 BGAs.
  • the number of the lead-out terminals 10 is 0.5111111, the length is 2111111, the pitch is 1.0 mm, and the total number is 152 as in the case of the connection terminal 2.
  • the lead-out terminal 10 is used to overlap the board connection terminal 30 at the same position on the board 29.
  • a solder ball terminal of a 152-pin BGA type semiconductor package 6 having a 0.5 mm pitch is connected to the connection terminal 2.
  • Each BGA is mounted at the mounting position 16 of the component to be measured, and is fixed to the tape circuit 17 with a weight of 200 g.
  • connection terminals 2 formed on the tape circuit By using the connection terminals 2 formed on the tape circuit, all the connection resistance values between the BGA solder balls 7 and the connection terminals 2 could be secured, and the maximum value was 0.2 ⁇ . This has facilitated the measurement of the characteristics of fine pitch BGA, which was difficult to evaluate in the past.
  • FIG. 8 is a plan view showing the structure of the burn-in board 31.
  • 16 sockets 25 of FIG. 7 are mounted.
  • resistors, capacitors, ICs, etc. are mounted on the board, but they are omitted because they are complicated.
  • At the end of the board there is a board terminal 32 for connecting to a burn-in device at the time of burn-in, and the number of terminals is about 120.
  • connection terminal 2 has high durability, high reliability, and has realized a connection terminal 2 that can be used semi-permanently by replacing an object to be measured.
  • the BGA type semiconductor package 6 is mounted with 0.52 mm pitch 152 pins.
  • the above effects are not dependent on the number of pins, component outer shape, and pitch. Clearly not.
  • FIG. 9 shows a cross-sectional structure diagram in which a BGA type semiconductor package 6 using a solder ball 7 as a connected terminal is connected to a board 29 via a connection terminal 2.
  • connection terminals 2 for connecting to the BGA are provided at corresponding positions.
  • the connection terminal 2 was plated with eutectic solder on the same copper as the wiring, and nickel particles having an average particle size of 25 / xm and fixed to rhodium were fixed.
  • the connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 152 BGAs per BGA.
  • the lead terminals 10 have a width of 0.5 mm, a length of 2 mm, a pitch of 1.0 mm, and a total of 15 2 terminals as with the connection terminal 2.
  • the lead-out terminal 10 can be used by overlapping with the connection terminal 2 at the same position on the board 29.
  • a weight of about 200 g was placed on the BGA.
  • the function of the board 29 was measured electrically.
  • the epoxy resin 33 was injected into the lower surface of the semiconductor package 6 with the weight placed thereon, and then the resin was solidified at 150 ° C.
  • connection terminal 2 of the present invention the components are fixed after the characteristics of the mounted components are confirmed, so that only non-defective products can be mounted.
  • the entire board can be regarded as a defective product, and waste that has been discarded or partially reworked can be eliminated.
  • FIG. 10 shows a cross-sectional structure diagram in which a semiconductor package 6 which is a BGA using a solder ball 7 as a connected terminal is connected to a board 29 via a connection terminal 2.
  • the basic structure is the same as that of the ninth embodiment, but a metal frame 36 having elasticity and an elastic body 35 are used for fixing the semiconductor package 6 which is a BGA and the board 29.
  • the through holes 34 for fixing the feet of the metal frame 36 are provided at four places near the corners of the portion of the board 29 where the BGA is mounted.
  • the elastic body 35 is placed in the metal frame 36, and the semiconductor package 6 which is BGA is further placed. This is Mau
  • the metal frame 36 is mounted on the board so that the foot of the metal frame 36 enters the through hole 34 of the board 29.
  • the foot of the metal frame 36 has a structure in which the tip opens after the penetration hole is inserted.
  • the fixed semiconductor foot 6 and the compressed elastic body 35 allow the semiconductor package 6 to have solder balls.
  • connection terminal 2 of the present invention, it is easy to confirm the characteristics of the mounted components and to replace the components.Therefore, the entire board is conventionally discarded or partially reworked as a defective product. Waste can be omitted.
  • FIG. 11 is a plan view showing the structure of the module 37.
  • six SRAM38s are mounted on the board.
  • At the end of the board there are board terminals 32 for connecting to the body of the personal computer, and the number of terminals is about 50.
  • FIG. 12 shows a plan view showing the structure of the module 37 and a cross-sectional view of the section A--A.
  • the function of the module 37 is the same as the module described in the embodiment 11.
  • board terminals 32 for connecting to the main body of the personal computer, and the number of terminals is about 50.
  • a personal computer could be assembled.
  • the size of the module itself can be reduced to about 1 to 2 in area as compared with the module of the embodiment 11.
  • a weight is applied to the function test to check the function, if the semiconductor chip is defective, it is easy to immediately replace it with a good one.
  • defective modules are discarded after assembly. The cost was reduced compared to the case where
  • a semiconductor chip for example, silicon single crystal
  • a chip lead composite 51 has a bonding pad or a bump forming pad 52 on its lower surface.
  • a solder ball 7 for example, a solder bump 7 (see FIG. 12) or a solder bump 53 (for example, a diameter of 0.25 mm and a pitch of 0.5 mm) is formed.
  • an elastic member sheet 58 for example, a thickness of 300 ⁇
  • an elastomer is disposed in a concave portion on a relatively rigid insulating substrate 57 so that good contact (burn-in) can be obtained during burn-in. (Preferably, contact resistance of 2 ⁇ or less).
  • a wiring board 56 having a wiring pattern of a copper film or the like (for example, a thickness of 18 ⁇ ) corresponding to the type is arranged on the wiring board 57.
  • a metal coating layer 59 made of a metal or an alloy that is less reactive with the solder of the bumps than the metal constituting the main region is formed.
  • the metal coating layer 59 is made of a material that is less oxidizable than the core material. When used, it has the effect of preventing surface oxidation of the core material such as nickel and improving electrical contact.
  • solder material for forming the solder bump 53 examples include eutectic solder (for example, composition 62 Sn Z95 Pb, melting point of 18 degrees Celsius) and tin silver solder (for example, composition 96.5 Sn The most suitable is 3.5 Ag, melting point of 211 degrees Celsius, or high-temperature solder (for example, composition 5 Sn / 95 Pb, melting point of about 310 degrees Celsius).
  • solder material for forming the above solder layer 55 examples include tin solder by plating (for example, composition 100% Sn, melting point of 23 degrees Celsius), high-temperature solder (for example, composition 5Sn 95 Pb, melting point). Optimum is about 310 degrees Celsius, tin-silver solder (for example, composition 96.5 Sn Z 3.5 Ag, melting point 22 degrees Celsius).
  • the burn-in test is performed at a temperature of about 125 degrees Celsius, for example, by supplying a power supply voltage that is about 10% higher than usual (with some kind of stress).
  • a heat cycle, etc. may be applied as necessary.
  • the integrated circuit package to be inspected and the inspection device side pad are mechanically separated. That is, the electrical contact is released by removing the adhesive for mechanical pressing or temporary bonding. At this time, the damage to the bumps is smaller than when they are physically fused by heating, so that the bumps can be mounted as they are or after a proper recovery process as final products.
  • the metal in the main region of the metal particles that is, as a core material, for example, nickel, titanium, chromium, cono-colt, iron, copper, tungsten, or molybdenum, or an alloy containing at least one of these as a main component is used. can do.
  • the material of the metal coating layer 59 rhodium, gold, silver, tin, lead, indium, platinum, palladium, or an alloy containing at least one of these as a main component can be used. .
  • the semiconductor chip 60 is fixed on the upper surface of the wiring sheet 62, and each terminal of the semiconductor chip 60 and the wiring sheet 6 are reinforced by a peripheral frame 61. Solder bumps 53 electrically connected via 2 are formed.
  • each terminal 63 on the device forming surface of the semiconductor chip 60 is electrically connected to an external pad 65 via a polyimide multilayer wiring 64, and on each external pad 65. Has solder bumps 53 formed thereon.
  • solder bump 53 is formed on each terminal 66 on the device forming surface of the semiconductor chip 60.
  • a semiconductor chip 60 is fixed on the upper surface of the multilayer wiring board 69 with the device side up, and each terminal 66 on the device formation surface of the semiconductor chip 60 (see FIG. 17). Are electrically connected to the multilayer wiring board 69 via bonding wires 68 and the like, and further electrically connected to the solder bumps 53 formed on the corresponding external pads via the multilayer wiring board 69. It is connected to the.
  • the semiconductor chip 60 and the bonding wires 68 are sealed with a resin 67.
  • the burn-in process of the present invention is applicable to all semiconductor integrated circuit devices in which at least the external terminals are made of ball-shaped metal terminals that are easily oxidized like solder bumps 53 as described above. Furthermore, it is particularly effective when applied to fine pitch products whose ball pitch (bump pitch) is around lmm to 0.5mm or less.
  • Embodiments 1 to 15 of the invention As described above, the invention made by the inventor has been specifically described based on Embodiments 1 to 15 of the invention.However, the invention is not limited to Embodiments 1 to 15 of the invention. Needless to say, various changes can be made without departing from the gist of the invention.
  • the burn-in board 31 shown in Fig. 8 the case where 16 sockets 25 are mounted has been described.
  • the number of mounted sockets is not limited to 16 but may be 1 or 16 Any number other than the above may be used. Industrial applicability
  • connection terminal and the magnifying circuit are integrated, and the positioning accuracy is improved compared to the case where the terminal of the conventional measurement system and the conductor on the film are separated. In this case, when they are separated, they need to be aligned. Also, if a film or the like is used, the film itself may be displaced or deformed. Accuracy is greatly reduced. Furthermore, when temperature is applied like burn-in, even if there is no misalignment at the time of setting, if there are many components, misalignment occurs due to the difference in thermal expansion. Therefore, by adopting this configuration, it is possible to cope with BGA and CSP with a fine pitch of 0.5 mm pitch or less, which has been conventionally regarded as the limit.
  • connection terminals Since metal particles that are harder than solder etc. are used for the connection terminals, the corners of the particles break the oxide film on the solder ball surface when they come into contact with the solder ball, and the new surface and the metal particles come into contact with each other. Reliable electrical connection can be ensured. In addition, because of the high positional accuracy of the connection part for the reason (1) above, an open or short circuit is unlikely to occur at the connection part during burn-in, so that electrical contact with the solder ball can be ensured.
  • connection terminals and the expansion circuit are integrated, and the other pressurizing sections and guide sections are configured separately.
  • the electrical part such as the magnifying circuit
  • the circuit can be formed by the conventional high exposure and development method with high productivity.
  • the pressurizing section and the like can be manufactured by the conventional molding technology with high productivity.
  • the connection part of the present invention can also be manufactured by a printing technique with high productivity. For this reason, the manufacturing cost can be reduced as compared with the case where the electrical part and the mechanical part are conventionally manufactured in a complicated manner. If the number of terminals, shape, etc. are different, conventional sockets that have been manufactured individually can be easily accommodated, for example, if the terminal pitch is the same, the same enlarged circuit can be used. On the other hand, since there is no need to manufacture individual sockets, the cost of sockets can be easily reduced.
  • connection reliability can be improved by setting the average particle size of the metal particles to 3 ⁇ to 50 ⁇ (more preferably, 10 ⁇ m to 40 / zm). In other words, if the average particle size is less than 3 / zm, oxidation of the surface of the solder bumps etc. used for the connected terminals The effect of breaking the film is reduced, and the connection reliability with the connected terminal deteriorates. If the average particle size exceeds 50 ⁇ , a short circuit between the connection terminals is likely to occur. It goes without saying that metal particles with an average particle diameter exceeding 50 ⁇ can be used with great care and care.

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Abstract

A method for manufacturing semiconductor integrated circuit device by which connection terminals (2), a socket (25), and a board (29) which can be produced at low cost, aligned with each other with high precision, and used repetitively and do not contaminate a connection section even when used at high temperature can be provided. The socket (25) is a combination of a structure in which the connection terminals (2) are formed integrally with an expansion circuit, and a structure in which a pressurizing section and a guide section are constituted separately, so that the socket can be adaptive to various kinds of BGAs and CSPs. The terminals (2) are formed directly on the terminals of the expansion circuit, and metal particles are fixed to the surfaces of the terminals (2) with solder or a brazing material. The metal particles ensure reliable electrical connection to solder balls (7) by breaking oxide films on the surfaces of solder balls (7) when the particles come into contact with the solder ball terminals of a BGA, CSP, or the like. Therefore fine-pitch BGAs and CSPs of pitches of below 0.5 mm can be inspected and burnt in. In addition, the cost of the socket (25) can be lowered.

Description

明 細 書 半導体集積回路装置の製造方法  Description Method of manufacturing semiconductor integrated circuit device
技術分野 Technical field
本発明は、 半導体集積回路装置の製造技術における電子部品、 電子回路との電 気的接触及び分離が可能な接続用端子、 ソケット、 及びボードに関し、 特に微細 ピツチの電子部品や回路の検査、 試験等を実施するための微細ピッチ接続が可能 な接続用端子、 ソケット、 及びボードを対象とした接続技術に関する。 背景技術  The present invention relates to an electronic component, a connection terminal, a socket, and a board capable of electrically contacting and separating with an electronic circuit in a manufacturing technology of a semiconductor integrated circuit device, and particularly to an inspection and a test of an electronic component and a circuit of a fine pitch. The present invention relates to connection technology for connection terminals, sockets, and boards that can be connected at a fine pitch for performing such operations. Background art
間瀬等の日本特開平 1一 2 0 1 9 3 1号公報及ぴ山崎等の日本特開平 2— 3 7 7 3 5号公報には、 銀、 パラジウム銀合金、 白金、 錫、 ニッケル、 チタン、 モリ ブデンその他の金属粉末を含むペーストによる印刷配線上に、 はんだバンプ等を 接触させるようにエポキシ榭脂によって接合するチップの実装方法が開示されて いる。  Japanese Patent Application Laid-Open No. 1-12031 by Mase and Japanese Patent Application Laid-Open No. 2-377735 by Yamazaki et al. Include silver, palladium-silver alloy, platinum, tin, nickel, titanium, There is disclosed a method of mounting a chip in which a solder bump or the like is brought into contact with a printed wiring made of a paste containing molybdenum or other metal powder using an epoxy resin so as to be in contact therewith.
更に、 矢田の特開平 8— 3 0 4 4 6 2号公報には、 銅等の印刷配線上のニッケ ルメツキ層上に、 更に金メッキ層を形成したパッド部に錫、 その合金、 インジュ ゥムバンプ等を接触させるバーンイン方法が開示されている。  Further, Yada's Japanese Patent Application Laid-Open No. 8-304446 discloses that tin, an alloy thereof, an indium bump and the like are formed on a nickel plating layer on a printed wiring such as copper and a pad portion further formed with a gold plating layer. A contact burn-in method is disclosed.
発明の開示 Disclosure of the invention
微細ピッチ部品の一例として C S P (Chip Size Package)接触端子について述 ベる。  As an example of a fine pitch component, a CSP (Chip Size Package) contact terminal is described.
C S Pは端子をエリアアレイ状に形成する B G A (Ball Grid Array) の一種で あり、 通常の B G Aと比較してピッチが微細なものを言う。 C S Pでは現在 0. 5 mmピッチの製品が出回りはじめた段階であるが、 このピッチは更に微細化する 動向にある。  CSP is a type of BGA (Ball Grid Array) in which the terminals are formed in an area array, and has a finer pitch than normal BGA. At the current stage of CSP, products with a 0.5 mm pitch have begun to appear on the market, but this pitch is in the trend of becoming even finer.
現在の 0. 5 mmピッチの製品での特' 試験やバーンィンを行う上では B G A等 で実施している方式を利用している。 この方式はシリコーンゴムの中に A uめつ きしたワイヤを一定方向に多数埋め込み、 このシリコーンゴムシートを介して C S Pの端子であるはんだボールとシリコーンゴムシートの下に配置してある回路 板のパッドとの間の接続を確保するものである。 To perform special tests and burn-in on the current 0.5 mm pitch products, the method implemented by BGA etc. is used. This method uses Au A large number of wires are buried in a certain direction, and the connection between the solder balls, which are the terminals of the CSP, and the pads of the circuit board placed under the silicone rubber sheet is secured through this silicone rubber sheet. .
この方式では、 下記の 4つの欠点がある。  This method has the following four disadvantages.
( 1 ) 位置合わせ精度が劣る。 これは、 厚いゴムシートを介し、 しかも介在する ワイヤが斜めに入っているため、 C S Pのはんだボールと回路基板のパッドとの 正確な接続が確保しにくいためである。  (1) Poor alignment accuracy. This is because it is difficult to ensure accurate connection between the CSP solder balls and the pads on the circuit board because the wires intervene obliquely through the thick rubber sheet.
( 2 ) コス トが高レ、。 シート自体が A uめっきワイヤを高密度にゴム中に埋め込 む複雑な構成を取っているため、 その製造コストが高いものとなる。  (2) High cost. Since the sheet itself has a complicated structure in which Au plated wires are embedded in rubber at a high density, the manufacturing cost is high.
( 3 ) 繰り返し使用回数が少ない。 高密度化の上で細いワイヤを使用しており、 繰り返し使用により、 ワイヤが折れる。 このため、 繰り返し使用回数が少ない。  (3) The number of repeated use is small. Fine wires are used for higher density, and the wire breaks due to repeated use. Therefore, the number of times of repeated use is small.
( 4 ) 被接続端子等への汚染。 製品となる C S Pのはんだボールが直接シリコ一 ンゴムに接するため、 低分子シリコーン榭脂がはんだボール等に付着する。 特に バーンィン等の高温処理をするとはんだボール表面に低分子のシリコ一ン榭脂が 多く付着する。 これが、 C S Pを基板等に実装する際に接続不良を発生させるこ とになる。 (4) Contamination of connected terminals. The low-molecular silicone resin adheres to the solder balls, etc., because the CSP solder balls that make up the product are in direct contact with the silicone rubber. In particular, when high-temperature treatment such as burnin is performed, a large amount of low-molecular silicone resin adheres to the solder ball surface. This causes a connection failure when the CSP is mounted on a substrate or the like.
本発明での課題は、 （1 ) 位置合わせ精度を向上し、 （2 ) 低コスト化し、 （3 ) 繰り返し使用ができ、 （4 ) 高温での使用でも接続部に汚染を与えない様にする ことである。  The object of the present invention is to (1) improve the alignment accuracy, (2) reduce the cost, (3) can be used repeatedly, and (4) prevent contamination of the connection part even when used at a high temperature. That is.
上記の課題を解決するために、 端子の導体表面に導電性粒子をはんだ、 あるい はろう材で固定した構造を持ち、 接触により電気的接続を確保する接続用端子構 造とした。  In order to solve the above problems, a connection terminal structure that has a structure in which conductive particles are fixed to the conductor surface of the terminal with solder or brazing material, and secures electrical connection by contact.
また、 この接続用端子において、 端子が面状に配置した複数の端子から成り、 それらの端子とそれら端子からの配線とで面状の回路板を形成し、 この回路板上 に被接続端子を持つ部品あるいは回路を搭載し、 これを上記回路板に押さえるソ ケットの構造とした。 更にそのソケットを大形回路基板上に搭載しボードとした。 また、 端子の導体表面に導電性粒子をはんだ、 あるいはろう材で固定した構造 を持ち、 接触により電気的接続を確保する接続用端子構造とした。 この構造により、 端子と被接続端子、 C S Pでははんだボールとの間にワイヤ 入りゴムシートを介在させないことになり、 被接続端子と接続子との位置合わせ 精度が向上する。 また、 はんだやろう材で固定するとはんだやろう材となじむ端 子以外の端子間には導電粒子が広がらないため端子間の短絡は生じない。 端子と して導電粒子をはんだ等で固定すれば良いため、 一定方向のワイヤを高密度にゴ ム中に並べるという複雑な操作を必要としないため、 低コストで接続を確保する ことができる。 また接続子は導体粒子がはんだ等で固定された強固な構造を有し ているため、 半永久的に繰り返し使用することができる。 また、 端子と被接触子 の間には、 被接触子等を汚す物質は無く、 高温でも使用する事が可能である。 また、 ソケットやボードの場合も、 この様な特徴を持つ端子を用いるため、 上 記同様、 高位置合わせ精度、 低コストで、 繰り返し使用可能で、 高温での使用で も接続部に汚染を与えないソケット及びボードとなる。 Further, in this connection terminal, the terminal is composed of a plurality of terminals arranged in a plane, and the terminal and the wiring from the terminals form a planar circuit board, and the terminal to be connected is formed on the circuit board. It has a socket structure that mounts the parts or circuits it has and holds it on the circuit board. Further, the socket was mounted on a large circuit board to form a board. In addition, it has a structure in which conductive particles are fixed to the conductor surface of the terminal with solder or brazing material, and a connection terminal structure that ensures electrical connection by contact. With this structure, the rubber sheet containing the wire is not interposed between the terminal and the connected terminal, or the solder ball in the CSP, and the positioning accuracy between the connected terminal and the connector is improved. In addition, when fixed with solder or brazing material, the conductive particles do not spread between the terminals other than the terminals compatible with the solder or brazing material, so that no short circuit occurs between the terminals. Since the conductive particles need only be fixed with solder or the like as a terminal, there is no need for a complicated operation of arranging wires in a certain direction at high density in the rubber, so that connection can be secured at low cost. Further, since the connector has a strong structure in which the conductive particles are fixed by solder or the like, the connector can be used semipermanently repeatedly. In addition, there is no substance between the terminal and the contact element that pollutes the contact element, and it can be used even at high temperatures. Also, in the case of sockets and boards, terminals with these characteristics are used, as in the above, high alignment accuracy, low cost, repetitive use, and contamination at high temperatures even at high temperatures. There will be no sockets and boards.
本願の主要な発明の概要を項分けして以下に示す。  The outline of the main invention of the present application is divided and shown below.
1 . 以下の工程を含む半導体集積回路装置の製造方法；  1. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部 （たとえばチップ又はチップを含むパッケージ 本体等） を構成する半導体集積回路チップ又はチップリード複合体 （たとえばマ ィク口 B G Aパッケージ本体すなわちはんだボールを除いた部分等） の外部接続 バンプ形成部 （たとえばチップリード複合体の下面に設けられたバンプ形成用電 極等） に設けられたはんだバンプ （たとえば電極上に作られた共晶はんだボール 等） を、 配線板 （たとえばフレキシブルテープ回路等） の第 1の主面上に設けら れ、 前記はんだバンプよりも硬い金属から成る複数の金属粒子がはんだ層に埋め 込まれた測定側電極パッド部 （すなわち接続端子等） に接触させる工程、 (a) A semiconductor integrated circuit chip or a chip-lead complex (for example, a part excluding a solder hole BGA package body, that is, a solder ball) constituting a main part of the semiconductor integrated circuit device (for example, a chip or a package body including the chip). External connection) Solder bumps (for example, eutectic solder balls formed on the electrodes) provided on the bump formation part (for example, bump forming electrodes provided on the lower surface of the chip lead composite) are connected to the wiring board. (E.g., a flexible tape circuit or the like) provided on the first main surface, and a plurality of metal particles made of a metal harder than the solder bumps and embedded in the solder layer on the measurement-side electrode pad portion (that is, a connection terminal or the like) ) Contacting the
(b) 前記はんだバンプを、 前記複数の金属粒子と接触するように前記測定側電極 パッド部に押し当てた状態で前記半導体集積回路チップ又はチップリード複合体 中の半導体集積回路チップに対して、 バーンインテストを実行する工程、(b) in a state where the solder bump is pressed against the measurement-side electrode pad portion so as to be in contact with the plurality of metal particles, with respect to the semiconductor integrated circuit chip in the semiconductor integrated circuit chip or the chip lead composite; The process of performing a burn-in test,
(c) 前記バーンインテストの結果に基づいて、 半導体集積回路装置の良否又は等 級 （良否のみ又は等級のみを判断しても好いことは言うまでもない） を決定する 工程。 (c) a step of determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test (it goes without saying that it is acceptable to judge only the quality or only the grade).
2 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その主要領域 (たとえばその本体すなわち表面のコート等を除いた部分等） がニッケル、 チタ ン、 クロム、 コバルト、 鉄、 銅、 タングステン、 又はモリブデン、 或いはこれら の少なくとも一つを主要成分とする合金からなるものである。 2. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a main area (For example, the main body, that is, a part except a surface coat, etc.) is made of nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum, or an alloy containing at least one of these as a main component. is there.
3 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その表面に前 記主要領域を構成する成分よりも前記はんだバンプのはんだと反応しにくレ、金属 被覆層を有するものである。  3. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a metal coating layer on the surface thereof, which is more difficult to react with the solder of the solder bumps than the components constituting the main region. It is.
4 . 本発明の半導体集積回路装置の製造方法は、 上記金属被覆層 （たとえば厚さ 0 . 数 μ πι程度のメツキ層等） は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白 金、 又はパラジウム、 或いはこれらの少なくとも一つを主要成分とする合金から なるものである。  4. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the metal coating layer (for example, a plating layer having a thickness of about 0.1 μπι) may be formed of rhodium, gold, silver, tin, lead, indium, white gold, or the like. Or palladium or an alloy containing at least one of these as a main component.
5 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子の平均粒径は 3 μ m力 ら 5 0 μ mである。  5. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the average particle diameter of the metal particles is 3 μm to 50 μm.
6 . 本発明の半導体集積回路装置の製造方法は、 上記チップリード複合体は C S Pパッケージ （たとえばマイクロ B G A、 W P P等） である。  6. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the chip lead composite is a CSP package (for example, micro BGA, WPP, etc.).
7 . 本発明の半導体集積回路装置の製造方法は、 上記配線板はフィルム状配線板 又はフィルム配線シートである。  7. In the method for manufacturing a semiconductor integrated circuit device of the present invention, the wiring board is a film-shaped wiring board or a film wiring sheet.
8 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その主要領域 がニッケル或いはニッケルを主要成分とする合金からなる。  8. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the metal particles have a main region made of nickel or an alloy containing nickel as a main component.
9 . 本発明の半導体集積回路装置の製造方法は、 上記金属被覆層は、 ロジウム或 いはロジウムを主要成分とする合金からなる。  9. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the metal coating layer is made of rhodium or an alloy containing rhodium as a main component.
1 0 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子の平均粒径は 1 0 μ m力 ら 4 0 μ mである。  10. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the average particle diameter of the metal particles is from 10 μm to 40 μm.
1 1 . 以下の工程を含む半導体集積回路装置の製造方法；  11. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部を構成する半導体集積回路チップ又はチップリ ード複合体の外部接続バンプ形成部に設けられたはんだバンプを、 フィルム状配 線板の第 1の主面上に設けられ、 前記はんだバンプよりも硬い金属から成る複数 の金属粒子がバインダ層 （たとえば共晶はんだ層等） に埋め込まれた測定側電極 パッド部に接触させる工程、  (a) The solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are placed on the first main surface of the film wiring board. A step of bringing a plurality of metal particles made of a metal harder than the solder bumps into contact with a measurement-side electrode pad portion embedded in a binder layer (for example, a eutectic solder layer or the like);
(b) 前記はんだバンプを、 前記複数の金属粒子と接触するように前記測定側電極 パッド部に押し当てた状態で前記半導体集積回路チップ又はチップリ一ド複合体 中の半導体集積回路チップに対して、 バーンインテストを実行する工程、 (b) the measurement-side electrode so that the solder bump is in contact with the plurality of metal particles; Performing a burn-in test on the semiconductor integrated circuit chip or the semiconductor integrated circuit chip in the chip-read composite while being pressed against the pad portion;
(C) 前記バーンインテストの結果に基づいて、 半導体集積回路装置の良否又は等 級を決定する工程。 (C) a step of determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
1 2 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その主要領 域がニッケル、 チタン、 クロム、 コバルト、 鉄、 銅、 タングステン、 又はモリブ デン、 或いはこれらの少なくとも一つを主要成分とする合金からなるものである。 12. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a main area of nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum, or at least one of them. It is composed of an alloy as a main component.
1 3 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その表面に 前記主要領域を構成する成分よりも前記はんだバンプのはんだと反応しにくい金 属被覆層を有するものである。 13. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a metal coating layer on the surface thereof, which is less likely to react with the solder of the solder bumps than the components constituting the main region. .
1 4 . 本発明の半導体集積回路装置の製造方法は、 上記金属被覆層は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又はパラジウム、 或いはこれらの少なくと も一つを主要成分とする合金からなるものである。  14. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal coating layer comprises rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of them as a main component. It is made of an alloy that has
1 5 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子の平均粒径は 3 /X m力 ら 5 0 μ mである。  15. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the average particle diameter of the metal particles is 50 μm from 3 / X m force.
1 6 . 本発明の半導体集積回路装置の製造方法は、 上記チップリード複合体は C S Pパッケージである。  16. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the chip-lead complex is a CSP package.
1 7 . 以下の工程を含む半導体集積回路装置の製造方法；  17. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部を構成する半導体集積回路チップ又はチップリ ード複合体の外部接続バンプ形成部に設けられたはんだバンプを、 配線板の第 1 の主面上に設けられ、 前記はんだバンプよりも硬い金属から成る複数の金属粒子 がはんだ層に埋め込まれた測定側電極パッド部に接触させる工程、  (a) solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are provided on the first main surface of the wiring board; A step of contacting a plurality of metal particles made of a metal harder than the solder bump with the measurement-side electrode pad portion embedded in the solder layer;
(b) 前記はんだバンプを、 前記複数の金属粒子と接触させた状態で前記半導体集 積回路チップ又はチップリード複合体中の半導体集積回路チップに対して、 バー ンインテストを実行する工程、  (b) performing a burn-in test on the semiconductor integrated circuit chip or the semiconductor integrated circuit chip in the chip-lead composite in a state where the solder bumps are in contact with the plurality of metal particles;
(c) 前記バーンインテストの結果に基づいて、 半導体集積回路装置の良否又は等 級を決定する工程。  (c) a step of determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
1 8 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その主要領 域がニッケル、 チタン、 クロム、 コバルト、 鉄、 銅、 タングステン、 又はモリブ デン、 或いはこれらの少なくとも一つを主要成分とする合金からなるものである。 1 9 . 本発明の半導体集積回路装置の製造方法は、 上記金属粒子は、 その表面に 前記主要領域を構成する成分よりも前記はんだバンプのはんだと反応しにくい金 属被覆層を有するものである。 18. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the main area of the metal particles is nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum. It is made of den or an alloy containing at least one of them as a main component. 19. The method for manufacturing a semiconductor integrated circuit device according to the present invention, wherein the metal particles have a metal coating layer on the surface thereof, which is less likely to react with the solder of the solder bumps than the components constituting the main region. .
2 0 . 本発明の半導体集積回路装置の製造方法は、 上記金属被覆層は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又はパラジウム、 或いはこれらの少なくと も一つを主要成分とする合金からなるものである。 20. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the metal coating layer may include rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of them as a main component. It is made of an alloy that has
更に、 本願のその他の発明の概要を項分けして以下に示す。  Further, the outlines of other inventions of the present application are shown below by dividing them into sections.
1 . 本発明の半導体集積回路装置の製造方法は、 接続端子が、 この接続端子 の導体表面に導電性粒子をはんだ、 あるいはろう材で固定した構造を持ち、 該導 電性粒子と被接続端子との接触により電気的接続を確保するものである。  1. The method for manufacturing a semiconductor integrated circuit device according to the present invention is characterized in that the connection terminal has a structure in which conductive particles are fixed to the conductor surface of the connection terminal with solder or brazing material. The electrical connection is ensured by contact with the device.
2 . 本発明の半導体集積回路装置の製造方法は、 前記導電性粒子の母材が、 T i、 C r、 C o、 N i、 F e、 C u、 W、 または M oの中の少なくとも 1種類 以上から成るものである。  2. The method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the base material of the conductive particles is at least one of Ti, Cr, Co, Ni, Fe, Cu, W, and Mo. It consists of one or more types.
3 . 本発明の半導体集積回路装置の製造方法は、 前記導電性粒子の表面に、 3. The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of:
A u、 A g、 S n、 P b、 I n、 R h、 P t、 または P dを被覆したものである。 Au, Ag, Sn, Pb, In, Rh, Pt, or Pd.
4 . 本発明の半導体集積回路装置の製造方法は、 前記導電性粒子の平均粒径 を 5 0ミクロンメーター以下で 3ミクロンメーター以上とするものである。  4. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the conductive particles have an average particle size of 50 μm or less and 3 μm or more.
5 . 本発明の半導体集積回路装置の製造方法は、 接続端子が、 この接続端子 の導体表面に導電性粒子をはんだ、 あるいはろう材で固定して、 該導電性粒子の 先端を残して前記接続端子の表面を絶縁膜で被覆したものである。  5. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the connection terminal may be configured such that conductive particles are fixed to a conductor surface of the connection terminal with solder or brazing material, and the connection is performed while leaving a tip of the conductive particle. The surface of the terminal is covered with an insulating film.
6 . 本発明の半導体集積回路装置の製造方法は、 ソケットが、 接続端子と、 この接続端子に接続する相手の被接続端子を重ねた状態で、 これらの両接続端子 間に圧力を加える加圧機構とを備えたものである。  6. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the socket may include a connection terminal and a connected terminal to be connected to the connection terminal, the connection terminal being overlapped with the socket, and a pressure applied between the two connection terminals. And a mechanism.
本発明の目的は、 位置合わせ精度の向上と低コスト化とを実現する半導体集積 回路装置の製造方法を提供することにある。  An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which realizes an improvement in alignment accuracy and a reduction in cost.
さらに、 本発明の他の目的は、 繰り返して使用ができ、 高温での使用において も接続部に汚染を与えない半導体集積回路装置の製造方法を提供することにある。 本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。 図面の簡単な説明 Still another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can be used repeatedly and does not contaminate a connection portion even when used at a high temperature. The above and other objects and novel features of the present invention will be described in the present specification and appended. It will be clear from the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の実施の形態 1の接続端子の構造を表す平面図と断面図、 図 2は 本発明の実施の形態 2の接続端子の構造を表す平面図と断面図、 図 3は本発明の 実施の形態 3の接続端子の構造を表す平面図、 図 4〜図 7は本発明の接続端子を 備えたソケットの実施の形態の構成図、 図 8は本発明の接続端子、 ソケットを備 えたバーンィンボードの構造を表す平面図、 図 9ははんだボールを用いた B G A 半導体パッケージを接続端子を介して、 ボードに接続した実施の形態の断面構造 図、 図 1 0ははんだボールを用いた B G A半導体パッケージを接続端子を介して、 ボードに接続した実施の形態の断面構造図、 図 1 1は本発明の接続端子、 ソケッ トを備えた実施の形態のモジュールの構造を表す平面図、 図 1 2は本発明の接続 端子、 ソケットを備えた実施の形態のモジュールの構造を表す平面図、 および断 面図、 図 1 3は本発明の端子接続構造の詳細を示す模式断面図、 図 1 4はその部 分拡大模式断面図、 図 1 5は本発明の対象となるファンアウト型 C S Pの基本的 構造を示す模式断面図、 図 1 6は本発明の対象となる WPPすなわちウェハプロセ スパッケージ (Wafer Process Package) の基本的構造を示す模式断面図、 図 1 7 は本発明の対象となるベアチップ実装の基本的構造を示す模式断面図、 図 1 8は 本発明の対象となる B G Aすなわちマイクロボ一ルグリッドアレ一 （Micro- Bal 1 Grid Array)の基本的構造を示す模式断面図である。 発明を実施するための最良の形態  FIG. 1 is a plan view and a sectional view showing the structure of the connection terminal according to the first embodiment of the present invention, FIG. 2 is a plan view and a sectional view showing the structure of the connection terminal according to the second embodiment of the present invention, and FIG. FIG. 4 is a plan view showing the structure of a connection terminal according to a third embodiment of the present invention; FIGS. 4 to 7 are configuration diagrams of an embodiment of a socket having the connection terminal according to the present invention; FIG. Fig. 9 is a plan view showing the structure of the burn-in board provided. Fig. 9 is a cross-sectional view of an embodiment in which a BGA semiconductor package using solder balls is connected to the board via connection terminals. Fig. 10 shows the use of solder balls. FIG. 11 is a cross-sectional structure diagram of an embodiment in which the BGA semiconductor package is connected to a board via connection terminals. FIG. 11 is a plan view showing a structure of a module according to an embodiment including connection terminals and a socket of the present invention. Fig. 12 shows the connection terminals and socket of the present invention. FIG. 13 is a plan view and a cross-sectional view showing the structure of the module according to the embodiment, FIG. 13 is a schematic cross-sectional view showing details of the terminal connection structure of the present invention, FIG. Fig. 5 is a schematic cross-sectional view showing the basic structure of a fan-out type CSP that is the subject of the present invention.Fig. 16 is a schematic cross-sectional view showing the basic structure of the WPP, that is, the wafer process package, that is the subject of the present invention. Figure, Figure 17 is a schematic cross-sectional view showing the basic structure of bare chip mounting that is the subject of the present invention, and Figure 18 is the BGA, that is, the Micro-Bal 1 Grid Array that is the subject of the present invention. It is a schematic cross section which shows the basic structure of. BEST MODE FOR CARRYING OUT THE INVENTION
以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原 則として繰り返さない。  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless necessary.
更に、 以下の実施の形態では便宜上その必要があるときは、 複数のセクション または実施の形態に分割して説明するが、 特に明示した場合を除き、 それらはお 互いに無関係なものではなくなく、 一方は他方の一部または全部の変形例、 詳細、 補足説明等の関係にある。  Further, in the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not unrelated to each other, unless otherwise specified. Some or all of the other modifications, details, supplementary explanations, etc. are present.
また、 以下の実施の形態において、 要素の数等 （個数、 数値、 量、 範囲等を含 む） に言及する場合、 特に明示した場合及び原理的に明らかに特定の数に限定さ れる場合等を除き、 その特定の数に限定されるものではなく、 特定の数以上でも 以下でも良いものとする。 In the following embodiments, the number of elements (including the number, numerical value, amount, range, etc.) ) Is not limited to the specified number, except where it is explicitly stated or limited in principle to a specific number, and may be more than or less than the specified number. And
更に、 以下の実施の形態において、 その構成要素 （要素ステップ等を含む） は、 特に明示した場合及び原理的に明らかに必須であると考えられる場合等を除き、 必ずしも必須のものではないことはいうまでもない。  Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be essential in principle. Needless to say.
同様に、 以下の実施の形態において、 構成要素等の形状、 位置関係等に言及す るときは、 特に明示した場合及び原理的に明らかにそうでないと考えられる場合 等を除き、 実質的にその形状等に近似または類似するもの等を含むものとする。 このことは上記数値及び範囲についても同様である。  Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and in cases where it is considered that the principle is clearly not in principle, etc. It shall include those that are similar or similar to the shape and the like. This is the same for the above numerical values and ranges.
以下、 本発明の実施の形態を図面に基づいて詳細に説明する。 なお、 実施の形 態を説明するための全図において、 同一の機能を有する部材には同一の符号を付 し、 その繰り返しの説明は省略する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
また、 本願で 「半導体集積回路装置」 と言うときは、 シリコンウェハ上に作ら れるものだけでなく、 特にそうでない旨明示された場合をのぞき、 T F T液晶等 の他の基板上に作られるもの等も含むものとする。  In this application, the term "semiconductor integrated circuit device" refers not only to a device formed on a silicon wafer, but also to a device formed on another substrate such as a TFT liquid crystal, unless otherwise specified. Shall be included.
更に、 本願において 「ウェハ又は半導体ウェハ」 と言うときは、 全部が単結晶 のシリコンウェハ等に限定されず、 その上に半導体集積回路装置を集積する絶縁 基板、 部分的半導体基板集積回路製造用の基板等も含むものとする。  Further, in the present application, the term “wafer or semiconductor wafer” is not limited to a single-crystal silicon wafer or the like, but may be used for manufacturing an insulating substrate on which a semiconductor integrated circuit device is integrated or a partial semiconductor substrate integrated circuit. It also includes a substrate and the like.
更に、 本願において 「バーンインテス ト」 と言うときは、 加熱による加速試験、 スクリーニング試験の外、 ストレスを加えて製品の潜在的欠陥を調べるエージン グその他の試験等も含むものとする。  Further, the term “burn-in test” in the present application includes not only an accelerated test by heating and a screening test, but also an aging test and the like for examining a product for potential defects by applying stress.
更に、 本願において 「配線板」 と言うときは、 ガラスエポキシ、 セラミック等 の基板に同等で配線をパターニングしたものの外、 ポリイミ ドフィルム上に銅フ イルム等の配線パターンを配置したもの等も含むものとする。  Further, the term "wiring board" used in the present application includes not only a board made of glass epoxy, ceramic or the like but also having a wiring pattern equivalent thereto, or a board having a wiring pattern such as a copper film arranged on a polyimide film. .
更に、 本願において 「チップリード複合体」 と言うときは、 半導体集積回路チ ップとそれに電気的に接続されたリードフレームから切り離されたリ一ド群を含 む組立体の外、 各種の C S Pやウェハプロセスパッケージのごとくチップとそれ と電気的に接続された引き出し電極を含む組立構造体等も含むものとする。 更に、 本願において 「はんだ」 と言うときは、 鉛錫系の共晶はんだの外、 錫金 はんだ、 高温はんだ、 錫はんだその他摂氏 4 5 0度以下の融点を有するろう付け 用金属合金等も含むものとする。 Further, in this application, the term “chip-lead complex” refers to not only an assembly including a semiconductor integrated circuit chip and a group of leads separated from a lead frame electrically connected thereto but also various CSPs. It also includes an assembly structure including a chip and a lead electrode electrically connected to the chip, such as a wafer process package. Further, the term “solder” in the present application includes not only lead-tin eutectic solder but also tin-gold solder, high-temperature solder, tin solder, and other brazing metal alloys having a melting point of 450 ° C or less. .
更に、 本願において 「バインダ層」 と言うときは、 はんだ層の外、 エポキシレ ジン系接着剤層等有機系のものも含むものとする。  Furthermore, in the present application, the term “binder layer” includes not only a solder layer but also an organic resin such as an epoxy resin adhesive layer.
(実施の形態 1 )  (Embodiment 1)
図 1に接続端子の構造を表す平面図と断面図を示す。 断面図は、 平面図中の A - A ' 部分の断面構造を示す。 リード 1は、 銅リードに共晶はんだをめつきした ものである。 リード 1の先端には平均粒径 5 0 μ ιηの銅粉末をはんだで固定し接 続端子 2を作成してある。 これは、 リード 1の先端を所定深さの銅粉末とフラッ タスを混ぜたペースト中に漬け、 リード先端に銅粒子を付けた状態で、 加熱する ことにより複数の銅粒子をリード 1の先端に固定した。 これらのリード 1をモ一 ルド型に入れ榭脂を注入して、 リード固定樹脂枠 3を作成した。 モールド時にリ ード 1は所定の形状に成形される。 この接続端子を利用する際には、 榭脂枠 3の 4隅にある穴にネジを固定ネジ 4を 4個で基板等に固定する。 固定ネジ 4には部 品押さえ板 5がついている。 このリード固定樹脂枠 3内部にたとえば被接続端子 であるはんだボール 7を持つ半導体パッケージ 6を入れ、 パッケージ裏面を 4枚 の部品押さえ板 5で固定して使用する。 この構造の接続端子 2を採用することに より、 従来のパネを入れたピンを用いる接続端子の場合より、 低コストの接続端 子 2を実現できた。  FIG. 1 shows a plan view and a sectional view showing the structure of the connection terminal. The cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view. Lead 1 is a copper lead with eutectic solder applied. At the tip of the lead 1, a copper powder having an average particle size of 50 μιη was fixed with solder to form a connection terminal 2. This is done by immersing the tip of the lead 1 in a paste containing a mixture of copper powder and flat powder of a predetermined depth, heating the lead with the copper particles attached, and applying a plurality of copper particles to the tip of the lead 1 by heating. Fixed. These leads 1 were put into a mold mold and resin was injected to form a lead fixing resin frame 3. At the time of molding, the lead 1 is formed into a predetermined shape. When using these connection terminals, fix the screws to the holes at the four corners of the resin frame 3 and fix them to the board or the like with four fixing screws 4. The fixing screw 4 has a component holding plate 5. A semiconductor package 6 having, for example, solder balls 7 as terminals to be connected is placed inside the lead fixing resin frame 3, and the back surface of the package is fixed with four component holding plates 5 for use. By employing the connection terminal 2 having this structure, the connection terminal 2 can be realized at a lower cost than the conventional connection terminal using a pin containing a panel.
(実施の形態 2 )  (Embodiment 2)
図 2に別の接続端子の構造を表す平面図と断面図を示す。 断面図は、 平面図中 の Α— A ' 部分の断面構造を示す。 接続端子 2はアルミナ基板 8の上に形成して レ、る。 形成方法は引き出し配線 9、 引き出し端子 1 0と同様に厚膜印刷技術で形 成した。 具体的には、 次の様にして製造した。 アルミナ基板 8には被測定部品で あるセラミックパッケージ 1 3を固定するための固定穴 1 2が 4個開いているも のを用いた。 この上に銀一パラジウムペーストを用いてスクリーン印刷技術で引 き出し配線 9、 接続端子 2及び引き出し端子 1 0を形成する。 引き出し端子 1 0 の上には更に金ペーストを用いて上塗りする。 これをベルト炉を用いて 9 0 0 °C で焼成する。 その後、 錫一銀粒子、 金めつきした平均粒径 3 0 / mのタンダステ ン粉末、 フラックス用榭脂粒子、 更に溶剤を混ぜペース ト状にしたものを接続端 子 2上に上塗りし、 これを 8 0 0 °Cのベルト炉で、 タングステン粒子を錫一銀の ろう材で固定した。 最後にセラミック製のガイ ド 1 1をセラミック接着剤で固定 した。 FIG. 2 shows a plan view and a sectional view showing the structure of another connection terminal. The cross-sectional view shows a cross-sectional structure of a portion Α—A ′ in the plan view. The connection terminal 2 is formed on an alumina substrate 8. The formation method was the same as that of the lead-out wiring 9 and the lead-out terminal 10 by using a thick film printing technique. Specifically, it was manufactured as follows. An alumina substrate 8 having four fixing holes 12 for fixing a ceramic package 13 to be measured was used. On this, lead-out wiring 9, connection terminal 2, and lead-out terminal 10 are formed by screen printing technique using silver-palladium paste. The lead terminals 10 are further overcoated with gold paste. This was heated at 900 ° C using a belt furnace. Baking. After that, tin-silver particles, gold-plated tungsten powder with an average particle size of 30 / m, flux resin particles, and a paste made by mixing a solvent are overcoated on the connection terminals 2 and In a 800 ° C. belt furnace, the tungsten particles were fixed with a tin-silver brazing filler metal. Finally, a ceramic guide 11 was fixed with a ceramic adhesive.
この接続端子 2の使用法は、 被測定部品であるセラミックパッケージ 1 3を被 測定部品搭載位置 1 6に搭載し、 その接続端子 2上には、 セラミックパッケージ 1 3のリード 1 4を乗せ、 そのリード部を銅製の押さえ棒 1 5を 2本用いて、 固 定穴 1 2にさしたネジで固定する。  This connection terminal 2 is used by mounting the ceramic package 13 to be measured at the mounting position 16 of the component to be measured, placing the lead 14 of the ceramic package 13 on the connection terminal 2, Fix the lead using two copper holding rods 15 and screws inserted into the fixing holes 12.
この接続端子 2を用いると、 被測定部品であるセラミックパッケージ 1 3の 2 0 o °c迄の信頼性を含む各種の特性評価を実施することができた。 これは、 従来 のパネを入れたピンを用いる接続端子の場合より、 低コス卜でしかも高い耐久性 を持ち、 信頼性が高く、 また、 被測定物を取り替え半永久的に使える接続端子 2 を実現できた。  By using the connection terminal 2, it was possible to evaluate various characteristics including the reliability of the ceramic package 13 to be measured up to 20 ° C. This realizes a connection terminal 2 that has low cost, high durability, high reliability, and can be used semi-permanently by replacing the device under test, compared to the conventional connection terminal that uses a pin containing a panel. did it.
尚タングステン粉末の他にモリブデン、 チタン、 クロム粉末を用いても接続端 子 2を形成した。 これらの場合もタングステン粉末の場合と同様の特性を得るこ とができる。  The connection terminals 2 were also formed by using molybdenum, titanium, and chromium powders in addition to the tungsten powder. In these cases, the same characteristics as in the case of the tungsten powder can be obtained.
(実施の形態 3 )  (Embodiment 3)
図 3に別の接続端子の構造を表す平面図を示す。 接続端子 2は約 4 5 mm角の フレキシブルテープ回路 1 7の上に形成している。 形成方法は通常のフレキシブ ルプリント回路 （F P C ) と同様のフォトリソグラフィ技術を用いて製造した。 回路の絶縁フィルム材はポリイミ ドであり、 引き出し配線 9、 引き出し端子 1 0、 及び接続端子 2は銅で形成した。 引き出し端子 1 0は銅の上に更に二ッケル及び 金でめっきした。 接続端子 2の銅の上には共晶はんだでロジウムめつきした平均 粒径 2 5 μ mのニッケル粒子を固定した。 引き出し配線 9の上には、 レジスト膜 を被覆した。 接続端子 2は、 直径 0 . 3 mmの大きさであり、 そのピッチが 0 . 5 mm、 2列配列で、 総数 1 5 2個である。  FIG. 3 is a plan view showing the structure of another connection terminal. The connection terminal 2 is formed on a flexible tape circuit 17 of about 45 mm square. The fabrication was performed using the same photolithography technology as that of a normal flexible printed circuit (FPC). The insulating film material of the circuit was polyimide, and the lead-out wiring 9, the lead-out terminal 10, and the connection terminal 2 were formed of copper. The lead terminal 10 was further plated with nickel and gold on copper. Nickel particles with an average particle size of 25 μm, which were rhodium-plated with eutectic solder, were fixed on the copper of connection terminal 2. A resist film was coated on the lead wiring 9. The connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 152 terminals.
この接続端子 2の上には、 0 . 5 mmピッチで 1 5 2ピンの B G A半導体パッ ケージのはんだボール端子が接続される。 B G Aは、 被測定部品搭載位置 1 6に 搭載し、 総加重 3 0 0 gを掛けてテープ回路 1 7に固定する。 また、 テープ外周 に配置している引き出し端子 1 0は、 幅 0 . 5 mmで長さ 2 mmであり、 ピッチ 1 . 0 mmで形成してある。 A solder ball terminal of a 152-pin BGA semiconductor package is connected on the connection terminal 2 at a pitch of 0.5 mm. The BGA is located at position 16 Mount and fix to tape circuit 17 with a total weight of 300 g. The lead terminals 10 arranged on the outer periphery of the tape have a width of 0.5 mm, a length of 2 mm, and a pitch of 1.0 mm.
図 3の接続端子 2を用いたソケット 2 5の断面図を図 4に示す。 接続端子 2を 形成したフレキシブルテープ回路 1 7をソケット台 1 8上に乗せ、 固定する。 こ のテープ回路上にソケット 2 5のパッケージガイド 1 9を乗せ、 ガイドビン 2 4 で固定する。 そこに、 被接続端子であるはんだボール 7の付いた B G Aタイプの 半導体パッケージ 6を搭載する。 その上にパッケージ押さえ 2 0を加圧用パネ 2 1で固定したソケット蓋 2 2を被せる。 具体的には、 ソケット蓋 2 2に形成した ガイドビン用穴 2 3にガイドビン 2 4を差し、 固定する。  FIG. 4 shows a cross-sectional view of the socket 25 using the connection terminal 2 of FIG. Place the flexible tape circuit 17 on which the connection terminal 2 is formed on the socket base 18 and fix it. Place the package guide 19 of the socket 25 on this tape circuit and fix it with the guide bin 24. There, a BGA type semiconductor package 6 with solder balls 7 to be connected is mounted. A socket cover 22 to which the package retainer 20 is fixed with the press panel 21 is put thereon. Specifically, the guide bin 24 is inserted into the guide bin hole 23 formed in the socket lid 22 and fixed.
この様にして、 接続端子 2に半導体パッケージ 6のはんだボール 7を接触させ ることにより、 その間の接続抵抗値は最大でも 0 . 2 Ωとすることができた。 こ れにより、 従来特性評価が難しかった微細ピッチの B G Aの特性測定が容易にな つた。  In this way, by bringing the solder ball 7 of the semiconductor package 6 into contact with the connection terminal 2, the connection resistance value between them could be set to 0.2 Ω at the maximum. This has facilitated the measurement of the characteristics of fine pitch BGA, which was conventionally difficult to evaluate.
また、 このテープ回路上の接続端子 2を搭載したソケット 2 5は、 B G Aのバ ーンインをも実施することができる。 バーンインでは、 テープ回路 1 7を含めて 約 1 3 0 °Cに上げ、 約 8時間連続動作をさせた。 この際、 B G Aのはんだボール の熱変形は生じたが、 接続端子 2と B G Aのはんだボールとの接続抵抗値は全て 0 . 5 Ω以下を確保することができた。 これにより、 従来困難であった微細ピッ チ B G Aのバーンインを、 量産レベルで実施できることが可能になる。 また、 こ の接続端子 2は高い耐久性を持ち、 信頼性が高く、 また、 被測定物を取り替え半 永久的に使える接続端子を実現できた。  In addition, the socket 25 on which the connection terminal 2 on the tape circuit is mounted can carry out burn-in of BGA. In the burn-in, the temperature was raised to about 130 ° C including the tape circuit 17, and the operation was continued for about 8 hours. At this time, thermal deformation of the BGA solder ball occurred, but the connection resistance value between the connection terminal 2 and the BGA solder ball could all be maintained at 0.5 Ω or less. This makes it possible to perform burn-in of fine pitch BGA, which was difficult in the past, at the mass production level. In addition, the connection terminal 2 has high durability, high reliability, and a connection terminal that can be used semi-permanently by replacing the device under test.
尚ニッケル粉末の他にコバルト、 鉄粉末を用いても接続端子 2を形成した。 こ れらの場合も上記同様にニッケル粉末の場合と同等の特性を得ることができた。  Note that the connection terminal 2 was formed using cobalt powder or iron powder in addition to nickel powder. In these cases, the same characteristics as those of the nickel powder could be obtained as described above.
(実施の形態 4 )  (Embodiment 4)
図 3のテープ回路 1 7の接続端子 2の部分に更にエポキシ系の榭脂を被覆し更 にその上から加圧 '加熱して接続端子 2を製造した。 この接続端子 2は、 ニッケ ル粒子がはんだの他樹脂でも固定した構造になつている。 ニッケル粒子の頭は加 圧時に樹脂が脇に移動する為表に出現している。 (実施の形態 5 ) The connection terminal 2 portion of the tape circuit 17 in FIG. 3 was further coated with an epoxy resin, and the connection terminal 2 was manufactured by applying pressure and heating from above. The connection terminal 2 has a structure in which nickel particles are fixed with resin in addition to solder. The head of the nickel particles appears in the table because the resin moves to the side during pressurization. (Embodiment 5)
図 4と同様のソケットで、 フレキシブルテープ回路 1 7の下に厚さ 0 . 3 mm の弾性膜を形成したソケットを製造した。 また加圧用パネ 2 1については弾力性 の低いものを適用した。 このソケット中に 1 5 2ピンの B G A半導体パッケージ を入れ、 特性評価を実施した。 B G Aに掛かる総力卩重は 2 0 0 gであった。  A socket similar to that shown in FIG. 4 and having an elastic film having a thickness of 0.3 mm formed under the flexible tape circuit 17 was manufactured. As the pressure panel 21, one having low elasticity was applied. A 152-pin BGA semiconductor package was placed in this socket, and the characteristics were evaluated. The total power of BGA was 200 g.
室温における接続端子 2と B G Aのはんだ端子間の接続抵抗値は最大でも 0 . 2 Ωとすることができた。 B G Aのバーンイン試験では、 テープ回路 1 7、 ソケ ット 2 5を含めて約 1 3 0 °Cに上げ、 約 8時間連続動作をさせた。 この際、 B G Aのはんだボールの熱変形は殆ど無く、 接続端子 2と B G Aはんだボールとの接 続抵抗値は全て 0 . 5 Ω以下を確保することができた。  The connection resistance value between the connection terminal 2 and the BGA solder terminal at room temperature could be at most 0.2 Ω. In the BGA burn-in test, the temperature was raised to about 130 ° C, including the tape circuit 17 and socket 25, and the device was operated continuously for about 8 hours. At this time, there was almost no thermal deformation of the BGA solder ball, and all the connection resistance values between the connection terminal 2 and the BGA solder ball were able to secure 0.5 Ω or less.
これにより、 実施の形態 3と同様、 微細ピッチの B G Aの特性測定が容易にな り、 また、 従来困難であった微細ピッチ B G Aのバーンインを、 量産レベルで実 施できることが可能になった。 また、 この接続端子 2は高い耐久性を持ち、 信頼 性が高く、 また、 被測定物を取り替え半永久的に使える接続端子 2を実現できた。 尚、 上記のソケット 2 5の製造では、 接続端子 2には金めつきしたニッケル粒 子を適用したが、 金めつきの他に、 銀、 錫、 鉛、 インジウム、 ロジユーム、 白金、 及びパラジュ一ムを検討し、 抵抗値の上では金めつきと同程度の値を得ることが できた。 これにより、 めっきとしては、 金めつきに限らず、 銀、 錫、 鉛、 インジ ゥム、 ロジユーム、 白金、 及びパラジュームも十分適用できることを確認した。  As a result, similarly to the third embodiment, the characteristics of fine pitch BGA can be easily measured, and burn-in of fine pitch BGA, which has been conventionally difficult, can be performed at a mass production level. In addition, the connection terminal 2 has high durability and high reliability, and the connection terminal 2 that can be used semi-permanently by replacing an object to be measured can be realized. In addition, in the manufacture of the socket 25 described above, nickel-plated nickel particles were applied to the connection terminals 2, but in addition to gold-plated, silver, tin, lead, indium, rhodium, platinum, and palladium The resistance value was about the same as the gold plating. As a result, it was confirmed that not only gold plating but also silver, tin, lead, indium, rhodium, platinum, and palladium can be applied as plating.
(実施の形態 6 )  (Embodiment 6)
図 5に別の接続端子を持つソケット 2 5の構造を表す断面図と平面図を示す。 断面図は、 平面図中の A— A ' 部分の断面構造を示す。 このソケット 2 5の中に は、 被測定部品である B G Aタイプの半導体パッケージ 6を 4個搭載できる構造 になっている。  FIG. 5 shows a cross-sectional view and a plan view illustrating the structure of a socket 25 having another connection terminal. The cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view. The socket 25 has a structure in which four BGA type semiconductor packages 6 as components to be measured can be mounted.
接続端子 2は約 7 O mm角のフレキシブルテープ回路 1 7の上に形成してある。 形成方法は通常のフレキシブルプリント回路 （F P C ) と同様のフォトリソグラ フィ技術を用いて製造した。 回路の絶縁フィルム材はポリイミ ドであり、 引き出 し配線 9、 引き出し端子 1 0、 及び接続端子 2は銅で形成した。 引き出し端子 1 0は銅の上に更に二ッケル及び金でめっきした。 接続端子 2の銅の上には共晶は んだでロジウムめつきした平均粒径 2 5 /zmのニッケル粒子を固定した。 引き出 し配線 9の上には、 レジスト膜を被覆した。 接続端子 2は、 直径 0. 3mmの大 きさであり、 そのピッチが 0. 5mm、 2列配列で、 1個の BGAで総数 1 5 2 個、 4個の BGAで総数 6 0 8個である。 The connection terminal 2 is formed on a flexible tape circuit 17 of about 70 mm square. Fabrication was performed using the same photolithography technology as that of a normal flexible printed circuit (FPC). The insulating film material of the circuit was polyimide, and the outgoing wiring 9, the outgoing terminal 10, and the connecting terminal 2 were formed of copper. The lead terminal 10 was further plated with nickel and gold on copper. Eutectic is on the copper of connection terminal 2 Nickel particles having an average particle size of 25 / zm attached to rhodium were fixed. A resist film was coated on the lead-out wiring 9. The connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, and are arranged in two rows, with a total of 152 pieces for one BGA and a total of 608 pieces for four BGAs. is there.
この接続端子 2の上には、 0. 5mmピッチで 1 5 2ピンの BGA半導体パッ ケージ 4個のはんだボール端子が接続される。 BGAは、 被測定部品搭載位置 1 6に搭載し、 総加重 800 gを掛けてテープ回路 1 7に固定する。 ソケット蓋 2 2の開閉には、 実施の形態 3と異なり、 パッケージガイド 1 9と蝶つがい 26で 一体化しており、 蓋 2 2を閉じた場合にはロック 2 7で、 蓋 2 2を固定できる構 造になっている。 また、 このソケット 2 5では、 実施の形態 5と同様に、 テープ 回路 1 7の下に弾性膜 28を設置した。  On this connection terminal 2, four solder ball terminals of a 152-pin BGA semiconductor package with a pitch of 0.5 mm are connected. The BGA is mounted on the component to be measured mounting position 16 and fixed to the tape circuit 17 with a total weight of 800 g. Unlike Embodiment 3, the opening and closing of the socket lid 22 is integrated with the package guide 19 and the hinge 26, and the lid 22 can be fixed with the lock 27 when the lid 22 is closed. It has a structure. Further, in this socket 25, an elastic film 28 was provided below the tape circuit 17 as in the fifth embodiment.
このテープ回路上に形成した接続端子 2を用いることにより、 B G Aのはんだ ボール 7と接続端子 2との接続抵抗値は全て確保でき、 その値は最大でも 0. 2 であった。 これにより、 従来特性評価が難しかった微細ピッチの BG Aの特性 測定が容易になった。 また、 このテープ回路上の接続端子 2は、 BGAのバーン インをも実施することができた。 バーンインでは、 テープ回路 1 7を含めて約 1 30°Cに上げ、 約 8時間連続動作をさせた。 この際、 BGAのはんだボール 7の 熱変形はあったが、 接続端子 2と B G Aのはんだボール 7との接続抵抗値は全て 0. 5 Ω以下を確保することができた。 これにより、 従来困難であった微細ピッ チ BG Aのバーンインを、 量産レベルで実施できることが可能になった。 また、 この接続端子 2は高い耐久性を持ち、 信頼性が高く、 また、 被測定物を取り替え 半永久的に使える接続端子 2を実現できた。  By using the connection terminal 2 formed on this tape circuit, all the connection resistance values between the BGA solder ball 7 and the connection terminal 2 could be secured, and the maximum value was 0.2. This has made it easier to measure the characteristics of fine pitch BGA, which was difficult to evaluate in the past. In addition, the connection terminal 2 on this tape circuit was also able to perform BGA burn-in. During burn-in, the temperature was raised to about 130 ° C, including the tape circuit 17, and operation was continued for about 8 hours. At this time, although the solder ball 7 of the BGA was thermally deformed, the connection resistance value between the connection terminal 2 and the solder ball 7 of the BGA could all be kept below 0.5 Ω. This has made it possible to carry out burn-in of fine pitch BGA, which was previously difficult, at the mass production level. In addition, this connection terminal 2 has high durability and high reliability, and has realized a connection terminal 2 that can be used semi-permanently by replacing an object to be measured.
(実施の形態 7)  (Embodiment 7)
図 6に別の接続端子を持つソケットの構造を表す断面図と平面図を示す。 断面 図は、 平面図中の A— A' 部分の断面構造を示す。 このソケット 2 5は 1枚のテ ープ回路 1 7に 4組のパッケージガイド 1 9、 パッケージ押さえ 20、 及ぴソケ ット蓋 22を持った構造で、 これらの各組には、 1個の BGAを搭載できる。 接続端子 2は約 4 5 mm幅で約 2 80 mm長さのフレキシブルテープ回路 1 7 の上に形成している。 形成方法は通常のフレキシブルプリント回路 （F PC) と 同様のフォトリソグラフィ技術を用いて製造した。 回路の絶縁フィルム材はポリ イミ ドであり、 引き出し配線 9、 引き出し端子 1 0、 及び接続端子 2は銅で形成 した。 引き出し端子 1 0は銅の上に更にニッケル及び金でめっきした。 接続端子 2の銅の上には共晶はんだでロジウムめつきした平均粒径 2 5 /x mのニッケル粒 子を固定した。 引き出し配線 9の上には、 レジスト膜を被覆した。 接続端子 2は、 直径 0 . 3 mmの大きさであり、 そのピッチが 0 . 5 mm、 2列配列で、 1個の 8 0八で総数1 5 2個、 4個の B G Aで総数 6 0 8個である。 FIG. 6 shows a cross-sectional view and a plan view illustrating the structure of a socket having another connection terminal. The cross-sectional view shows the cross-sectional structure taken along the line AA ′ in the plan view. The socket 25 has a structure in which one tape circuit 17 has four sets of package guides 19, a package holder 20, and a socket cover 22. BGA can be mounted. The connection terminal 2 is formed on a flexible tape circuit 17 having a width of about 45 mm and a length of about 280 mm. The formation method is the same as a normal flexible printed circuit (FPC). It was manufactured using a similar photolithography technique. The insulating film material of the circuit was polyimide, and the lead wiring 9, the lead terminal 10 and the connection terminal 2 were formed of copper. The lead terminal 10 was further plated with nickel and gold on copper. Nickel particles having an average particle size of 25 / xm fixed to rhodium with eutectic solder were fixed on the copper of the connection terminal 2. The lead film 9 was covered with a resist film. The connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, and are arranged in two rows, a total of 15 2 with one 80, and a total of 60 with 4 BGAs. There are eight.
この接続端子 2の上には、 0 . 5 mmピッチで 1 5 2ピンの B G A半導体パッ ケージのはんだボール端子が接続される。 各 B G Aは、 被測定部品搭載位置 1 6 に搭載し、 加重 2 0 0 gを掛けてテープ回路 1 7に固定する。  On this connection terminal 2, a solder ball terminal of a 152-pin BGA semiconductor package is connected at a pitch of 0.5 mm. Each BGA is mounted on the component to be measured mounting position 16 and fixed to the tape circuit 17 by applying a weight of 200 g.
このテープ回路上に形成した接続端子 2を用いることにより、 B G Aのはんだ ボールと接続端子 2との接続抵抗値は全て確保でき、 その値は最大でも 0 . 2 Ω であった。 これにより、 従来特性評価が難しかった微細ピッチの B G Aの特性測 定が容易になった。 また、 このテープ回路上の接続端子 2は、 B G Aのバーンィ ンをも実施することができた。 バーンインでは、 テープ回路 1 7を含めて約 1 3 に上げ、 約 8時間連続動作をさせた。 この際、 B G Aのはんだボール 7の熱 変形はあったが、 接続端子 2と B G Aのはんだボール 7との接続抵抗値は全て 0 . 5 Ω以下を確保することができた。 これにより、 従来困難であった微細ピッチ B G Aのバーンインを、 量産レベルで実施できることが可能になった。 また、 この 接続端子 2は高い耐久性を持ち、 信頼性が高く、 また、 被測定物を取り替え半永 久的に使える接続端子 2を実現できた。  By using the connection terminals 2 formed on the tape circuit, all the connection resistance values between the BGA solder balls and the connection terminals 2 could be secured, and the maximum value was 0.2 Ω. This makes it easy to measure the characteristics of fine pitch BGA, which was difficult to evaluate in the past. In addition, the connection terminal 2 on this tape circuit was able to carry out BGA burn-in. In the burn-in, it was raised to about 13 including the tape circuit 17 and operated continuously for about 8 hours. At this time, the solder ball 7 of BGA was thermally deformed, but the connection resistance value between the connection terminal 2 and the solder ball 7 of BGA was all less than 0.5 Ω. As a result, burn-in of fine pitch BGA, which was difficult in the past, can be performed at the mass production level. The connection terminal 2 has high durability and high reliability, and the connection terminal 2 that can be used semi-permanently by replacing the device under test can be realized.
(実施の形態 8 )  (Embodiment 8)
図 7に別の接続端子を持つソケット 2 5の構造を表す断面図と平面図を示す。 断面図は、 平面図中の A— A ' 部分の断面構造を示す。 このソケット 2 5の基本 構造は実施の形態 7と類似している。 異なる点は次の 2点。 それは、 テープ回路 1 7を含めたソケット 2 5の外形は約 4 5 mm角で、 1つのソケット 2 5には、 1個の B G Aを搭載できる構造とした点、 及びテープ回路 1 7の引き出し端子 1 0は、 ソケット裏面に曲げ、 そこに固定しており、 更に引き出し端子 1 0の表面 上には接続端子 2と同様の構造を付与している点である。 接続端子 2と引き出し端子 10には、 銅の上に共晶はんだでロジウムめっきし た平均粒径 25 μπιのニッケル粒子を固定した。 引き出し配線 9の上には、 レジ スト膜を被覆した。 接続端子 2は、 直径 0. 3mmの大きさであり、 そのピッチ が 0. 5mm、 2列配列で、 1個の B G Aで総数 1 52個である。 引き出し端子 10は幅が0. 5111111で長さが2111111、 ピッチが 1. 0 mmで総数は接続端子 2 と同様 1 52個である。 この引き出し端子 1 0は、 ボード 29上の同位置のボー ド接続端子 30に重ねて使用する。 FIG. 7 shows a cross-sectional view and a plan view illustrating the structure of a socket 25 having another connection terminal. The cross-sectional view shows a cross-sectional structure taken along the line AA ′ in the plan view. The basic structure of this socket 25 is similar to that of the seventh embodiment. The differences are the following two points. The external shape of the socket 25 including the tape circuit 17 is about 45 mm square, one socket 25 has a structure that can mount one BGA, and the drawer terminal of the tape circuit 17 Reference numeral 10 denotes a point bent and fixed to the back surface of the socket, and a structure similar to that of the connection terminal 2 is provided on the surface of the lead terminal 10. Nickel particles with an average particle size of 25 μπι, which were plated with rhodium on copper with eutectic solder, were fixed to the connection terminal 2 and the lead terminal 10. A resist film was coated on the lead wiring 9. The connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 1 52 BGAs. The number of the lead-out terminals 10 is 0.5111111, the length is 2111111, the pitch is 1.0 mm, and the total number is 152 as in the case of the connection terminal 2. The lead-out terminal 10 is used to overlap the board connection terminal 30 at the same position on the board 29.
この接続端子 2の上には、 0. 5 mmピッチで 1 52ピンの BG Aタイプの半 導体パッケージ 6のはんだボール端子が接続される。 各 BGAは、 被測定部品搭 載位置 1 6に搭載し、 加重 200 gを掛けてテープ回路 1 7に固定する。  A solder ball terminal of a 152-pin BGA type semiconductor package 6 having a 0.5 mm pitch is connected to the connection terminal 2. Each BGA is mounted at the mounting position 16 of the component to be measured, and is fixed to the tape circuit 17 with a weight of 200 g.
このテープ回路上に形成した接続端子 2を用いることにより、 B G Aのはんだ ボール 7と接続端子 2との接続抵抗値は全て確保でき、 その値は最大でも 0. 2 Ωであった。 これにより、 従来特性評価が難しかった、 微細ピッチの BG Aの特 性測定が容易になった。  By using the connection terminals 2 formed on the tape circuit, all the connection resistance values between the BGA solder balls 7 and the connection terminals 2 could be secured, and the maximum value was 0.2 Ω. This has facilitated the measurement of the characteristics of fine pitch BGA, which was difficult to evaluate in the past.
(実施の形態 9)  (Embodiment 9)
図 8にバーンインボード 3 1の構造を表す平面図を示す。 ボード 29の上には、 図 7のソケット 25を 1 6個搭載している。 この他ボード上には、 抵抗体、 コン デンサ、 I C等を搭載しているが、 複雑になるので省略する。 ボード端部にはバ —ンインの際に、 バーンイン装置と接続するためのボード端子 32があり、 その 端子数は約 1 20である。 この各ソケット 25に BGAタイプの半導体パッケ一 ジ 6を入れ固定することにより、 BG Aのはんだボール 7と接続端子 2との接続 抵抗値は全て確保でき、 その値は最大でも 0. 2 Ωであった。 このバーンインポ ード 31を用いてバーンインを実施することができた。 バーンインでは、 テープ 回路 1 7を含めて約 1 30°Cに上げ、 約 8時間連続動作をさせた。 この際、 BG Aのはんだボール 7の熱変形はあったが、 接続端子 2と BG Aのはんだボール 7 との接続抵抗値は全て 0. 5 Ω以下を確保することができた。 これにより、 従来 困難であつた微細ピッチ BGAのバーンインを、 量産レベルで実施できることが 可能になった。 また、 この接続端子 2は高い耐久性を持ち、 信頼性が高く、 また、 被測定物を取り替え半永久的に使える接続端子 2を実現できた。 尚、 上記実施の形態では、 BGAタイプの半導体パッケージ 6として、 0. 5 mmピッチの 1 5 2ピンを実装する例を上げたが、 上記効果はピン数、 部品外形、 ピッチに依存するものではないことは、 明らかである。 FIG. 8 is a plan view showing the structure of the burn-in board 31. On the board 29, 16 sockets 25 of FIG. 7 are mounted. In addition, resistors, capacitors, ICs, etc. are mounted on the board, but they are omitted because they are complicated. At the end of the board, there is a board terminal 32 for connecting to a burn-in device at the time of burn-in, and the number of terminals is about 120. By inserting and fixing the BGA type semiconductor package 6 in each socket 25, all the connection resistance values between the BGA solder ball 7 and the connection terminal 2 can be secured, and the maximum value is 0.2 Ω. there were. Burn-in could be carried out using this burn-in import 31. In the burn-in, the temperature was raised to about 130 ° C including the tape circuit 17, and the operation was continued for about 8 hours. At this time, although the solder ball 7 of BGA was thermally deformed, the connection resistance value between the connection terminal 2 and the solder ball 7 of BGA could all be maintained at 0.5 Ω or less. As a result, burn-in of fine pitch BGA, which has been difficult in the past, can now be performed at the mass production level. In addition, this connection terminal 2 has high durability, high reliability, and has realized a connection terminal 2 that can be used semi-permanently by replacing an object to be measured. In the above-described embodiment, an example is described in which the BGA type semiconductor package 6 is mounted with 0.52 mm pitch 152 pins. However, the above effects are not dependent on the number of pins, component outer shape, and pitch. Clearly not.
(実施の形態 1 0)  (Embodiment 10)
図 9に被接続端子としてはんだボール 7を用いた BG Aタイプの半導体パッケ ージ 6を接続端子 2を介して、 ボード 2 9に接続した断面構造図を示す。  FIG. 9 shows a cross-sectional structure diagram in which a BGA type semiconductor package 6 using a solder ball 7 as a connected terminal is connected to a board 29 via a connection terminal 2.
ボード 29の上面には、 配線の他、 BG Aと接続する為の接続端子 2を対応す る位置に設けている。 接続端子 2は配線と同じ銅の上に共晶はんだでめっきし、 ロジウムめつきした平均粒径 2 5 /xmのニッケル粒子を固定した。 接続端子 2は、 直径 0. 3 mmの大きさであり、 そのピッチが 0. 5 mm、 2列配列で、 1個の BGAで総数 1 5 2個である。 引き出し端子 1 0は幅が 0. 5mmで長さが 2m m、 ピッチが 1. 0 mmで総数は接続端子 2と同様 1 5 2個である。 この引き出 し端子 1 0は、 ボード 2 9上の同位置の接続端子 2に重ねて使用できる。 BGA である半導体パッケージ 6とボード 2 9との仮固定の上で、 BGA上に約 200 gの重りを乗せた。 この状態でボード 2 9の機能を電気的に測定した。 機能測定 で、 所定の機能を確認した場合には、 重りを乗せたまま、 エポキシ系の樹脂 3 3 を半導体パッケージ 6の下面に注入し、 その後 1 5 0°Cで榭脂を固化した。  On the upper surface of the board 29, in addition to the wiring, connection terminals 2 for connecting to the BGA are provided at corresponding positions. The connection terminal 2 was plated with eutectic solder on the same copper as the wiring, and nickel particles having an average particle size of 25 / xm and fixed to rhodium were fixed. The connection terminals 2 have a diameter of 0.3 mm, a pitch of 0.5 mm, a two-row arrangement, and a total of 152 BGAs per BGA. The lead terminals 10 have a width of 0.5 mm, a length of 2 mm, a pitch of 1.0 mm, and a total of 15 2 terminals as with the connection terminal 2. The lead-out terminal 10 can be used by overlapping with the connection terminal 2 at the same position on the board 29. After temporarily fixing the semiconductor package 6 as a BGA and the board 29, a weight of about 200 g was placed on the BGA. In this state, the function of the board 29 was measured electrically. When the predetermined function was confirmed by the function measurement, the epoxy resin 33 was injected into the lower surface of the semiconductor package 6 with the weight placed thereon, and then the resin was solidified at 150 ° C.
この様に、 本発明の接続端子 2を利用することにより、 実装部品の特性を確認 した後に部品の固定を実施するため、 良品のみを実装できる。 これにより、 従来 不良品を実装した場合には、 ボード全体を不良品として、 廃棄あるいは、 部分的 に手直ししていた無駄を省略できるようになった。  In this way, by using the connection terminal 2 of the present invention, the components are fixed after the characteristics of the mounted components are confirmed, so that only non-defective products can be mounted. As a result, when a defective product is mounted in the past, the entire board can be regarded as a defective product, and waste that has been discarded or partially reworked can be eliminated.
(実施の形態 1 1 )  (Embodiment 11)
図 1 0に被接続端子としてはんだボール 7を用いた BG Aである半導体パッケ ージ 6を接続端子 2を介して、 ボード 2 9に接続した断面構造図を示す。  FIG. 10 shows a cross-sectional structure diagram in which a semiconductor package 6 which is a BGA using a solder ball 7 as a connected terminal is connected to a board 29 via a connection terminal 2.
基本構造は実施の形態 9と同じであるが、 BGAである半導体パッケージ 6と ボード 2 9との固定には、 ばね性を持つメタルフレーム 3 6と弾性体 3 5を用い る。 ボード 2 9の BG Aを搭載する部分のコーナー部近傍にメタルフレーム 36 の足を固定するための貫通孔 34を 4力所に設ける。 メタルフレーム 36には、 弾性体 3 5を入れ、 更に BG Aである半導体パッケージ 6を入れる。 これをマウ ンタでメタルフレーム 3 6の足がボード 2 9の貫通孔 3 4に入る様に基板に搭載 する。 メタルフレーム 3 6の足は貫通孔揷入後に先端が開く構造になっており、 この足が固定されていることと、 弾性体 3 5が圧縮されていることで、 半導体パ ッケージ 6がはんだボール 7と接続端子 2を介してボード 2 9と電気的に接続す る。 接続後、 ボード単位で電気的検査を実施し、 この半導体パッケージ 6の機能 不十分である場合は、 メタルフレーム 3 6をボード 2 9から外して半導体パッケ ージ 6を交換し、 それが良品であることを確認する。 この様に、 本発明の接続端 子 2を利用することにより、 実装部品の特性確認や部品交換が容易であるため、 従来、 ボード全体を不良品として、 廃棄あるいは、 部分的に手直ししていた無駄 を省略できるようになった。 The basic structure is the same as that of the ninth embodiment, but a metal frame 36 having elasticity and an elastic body 35 are used for fixing the semiconductor package 6 which is a BGA and the board 29. The through holes 34 for fixing the feet of the metal frame 36 are provided at four places near the corners of the portion of the board 29 where the BGA is mounted. The elastic body 35 is placed in the metal frame 36, and the semiconductor package 6 which is BGA is further placed. This is Mau The metal frame 36 is mounted on the board so that the foot of the metal frame 36 enters the through hole 34 of the board 29. The foot of the metal frame 36 has a structure in which the tip opens after the penetration hole is inserted. The fixed semiconductor foot 6 and the compressed elastic body 35 allow the semiconductor package 6 to have solder balls. 7 is electrically connected to board 29 via connection terminal 2. After the connection, an electrical test is performed for each board. If the function of the semiconductor package 6 is not sufficient, the metal package 36 is removed from the board 29 and the semiconductor package 6 is replaced. Make sure there is. As described above, by using the connection terminal 2 of the present invention, it is easy to confirm the characteristics of the mounted components and to replace the components.Therefore, the entire board is conventionally discarded or partially reworked as a defective product. Waste can be omitted.
(実施の形態 1 2 )  (Embodiment 12)
図 1 1にモジュール 3 7の構造を表す平面図を示す。 ボード 2 9の上には、 図 7のソケット 2 5を 1個搭載している。 この他、 ボード上には、 S R AM 3 8を 6個搭載している。 ボ一ド端部にはパーソナルコンピュータの本体と接続するた めのボード端子 3 2があり、 その端子数は約 5 0である。 このソケット 2 5にマ イク口コンピュータ機能を持つ B G Aタイプの半導体パッケージ 6を入れ固定す ることにより、 B G Aである半導体パッケージ 6のはんだボール 7と接続端子 2 との接続抵抗値は全て確保でき、 その値は最大でも 0 . 2 Ωであった。 このモジ ユール 3 7を用いてパーソナルコンピュータを組み立てることができた。 このモ ジュール 3 7を採用することにより、 モジュール自体の機能検査段階で、 B G A タイプの半導体パッケージ 6が不良品である場合、 ただちに良品に交換すること が容易であり、 従来不良のモジュールを廃棄していた場合と比較して、 コスト低 減になった。 この方式は、 特に半導体パッケージ 6内のマイクロコンピュータチ ップゃ半導体パッケージ 6の開発当初で有効であった。  FIG. 11 is a plan view showing the structure of the module 37. FIG. On the board 29, one socket 25 of FIG. 7 is mounted. In addition, six SRAM38s are mounted on the board. At the end of the board, there are board terminals 32 for connecting to the body of the personal computer, and the number of terminals is about 50. By inserting and fixing a BGA type semiconductor package 6 with a microphone port computer function in this socket 25, all the connection resistance values between the solder balls 7 of the semiconductor package 6 as a BGA and the connection terminals 2 can be secured. Its value was at most 0.2 Ω. Using this module 37, a personal computer could be assembled. By using the module 37, if the BGA type semiconductor package 6 is defective during the function inspection stage of the module itself, it is easy to immediately replace it with a non-defective one. Cost was reduced compared to the case where This method was effective especially at the beginning of the development of the microcomputer chip in the semiconductor package 6 divided by the semiconductor package 6.
(実施の形態 1 3 )  (Embodiment 13)
図 1 2にモジュール 3 7の構造を表す平面図及び A— A， 部の断面図を示す。 モジュール 3 7の機能は実施の形態 1 1に説明したモジュールと同じである。 ボード 2 9の上には、 S R AMチップ 3 8を 6個、 及びマイクロコンピュータ チップ 3 9を 1個搭載している。 各チップにははんだボール 7で形成した被接続 端子を形成してある。 このはんだボール 7はボード 2 9上の接続端子 2に接して おり、 これを保持する為に、 チップとボード 2 9間には榭脂 3 3を充填 ·硬化し てある。 ボード端部にはパーソナルコンピュータの本体と接続するためのボード 端子 3 2があり、 その端子数は約 5 0である。 このモジュール 3 7を用いてパー ソナルコンピュータを組み立てることができた。 このモジュール 3 7を採用する ことにより、 モジュール自体の大きさが、 実施の形態 1 1のモジュールと較して、 約 1ノ 2の面積と小形化できた。 また半導体チップを搭載し、 これに加重を掛け て機能検査する段階で、 半導体チップが不良品である場合、 ただちに良品に交換 することが容易であり、 従来組み立て後、 不良のモジュールを廃棄していた場合 と比較して、 コスト低減になった。 Figure 12 shows a plan view showing the structure of the module 37 and a cross-sectional view of the section A--A. The function of the module 37 is the same as the module described in the embodiment 11. On the board 29, six SRAM chips 38 and one microcomputer chip 39 are mounted. Each chip is connected with solder balls 7 Terminals are formed. The solder balls 7 are in contact with the connection terminals 2 on the board 29, and a resin 33 is filled and cured between the chip and the board 29 in order to hold the connection terminals. At the end of the board, there are board terminals 32 for connecting to the main body of the personal computer, and the number of terminals is about 50. Using this module 37, a personal computer could be assembled. By adopting the module 37, the size of the module itself can be reduced to about 1 to 2 in area as compared with the module of the embodiment 11. At the stage where a semiconductor chip is mounted and a weight is applied to the function test to check the function, if the semiconductor chip is defective, it is easy to immediately replace it with a good one.Conventionally, defective modules are discarded after assembly. The cost was reduced compared to the case where
(実施の形態 1 4 )  (Embodiment 14)
以上の各実施の形態に共通した接触部分の構造及び働き等の詳細を特に図 5又 は図 6に説明されている構造に対応した例を用いて、 より詳しく説明する。  The details of the structure and operation of the contact portion common to the above embodiments will be described in more detail, particularly using an example corresponding to the structure described in FIG. 5 or FIG.
図 1 3において、 半導体チップ （たとえばシリコン単結晶） 又はチップリード 複合体 5 1はその下面にボンディングパッド又はバンプ形成用パッド 5 2を有す る。 このバンプ形成用パッド 5 2上にははんだボール 7 (図 1 2参照） 又ははん だバンプ 5 3 (たとえば直径 0 . 2 5 mmで 0 . 5 mmピッチ） が形成されてい る。 測定器側は比較的剛性のある絶縁基板 5 7上のくぼみ部にエラストマ一等の 弾性部材シート 5 8 (たとえば厚さ 3 0 0 μ πι ) が配置されており、 バーンイン 時の良好なコンタクト （望ましくは接触抵抗 2 Ω以下） を保証している。 配線基 板 5 7上には品種に対応した銅フィルム等 （たとえば厚さ 1 8 μ πι ) の配線バタ ーンを有する配線板 5 6が配置されており、 この配線パターンの測定側パッド部 にははんだ層 5 5が形成されており、 このはんだ層中には一部が突出するように ニッケル等の金属粒子 5 4が埋め込まれている。 バーンイン時にはこの金属粒子 5 4のいくつかが、 はんだバンプ 5 3の表面の酸化膜を突き破り、 良好な電気的 接触を確保する。  In FIG. 13, a semiconductor chip (for example, silicon single crystal) or a chip lead composite 51 has a bonding pad or a bump forming pad 52 on its lower surface. On this bump forming pad 52, a solder ball 7 (see FIG. 12) or a solder bump 53 (for example, a diameter of 0.25 mm and a pitch of 0.5 mm) is formed. On the measuring instrument side, an elastic member sheet 58 (for example, a thickness of 300 μππ) such as an elastomer is disposed in a concave portion on a relatively rigid insulating substrate 57 so that good contact (burn-in) can be obtained during burn-in. (Preferably, contact resistance of 2 Ω or less). A wiring board 56 having a wiring pattern of a copper film or the like (for example, a thickness of 18 μππ) corresponding to the type is arranged on the wiring board 57. Has a solder layer 55 formed therein, and metal particles 54 such as nickel are embedded in the solder layer so as to partially project. At the time of burn-in, some of the metal particles 54 break through the oxide film on the surface of the solder bump 53 to ensure good electrical contact.
図 1 4において、 上記金属粒子 5 4の表面には上記主要領域を構成する金属よ りもバンプのはんだと反応しにくい金属又は合金より成る金属被覆層 5 9が形成 されている。 なお、 この金属被覆層 5 9に上記心材よりも酸化されにくい材料を 用いた場合にはニッケル等の心材の表面酸化等を防止して電気的接触を改善する 効果を持つ。 In FIG. 14, on the surface of the metal particles 54, a metal coating layer 59 made of a metal or an alloy that is less reactive with the solder of the bumps than the metal constituting the main region is formed. The metal coating layer 59 is made of a material that is less oxidizable than the core material. When used, it has the effect of preventing surface oxidation of the core material such as nickel and improving electrical contact.
上記はんだバンプ 5 3形成用のはんだ材料としては、 共晶はんだ （たとえば組 成 6 2 S n Z 9 5 P b、 融点摂氏 1 8 3度） 、 錫銀はんだ （たとえば組成 9 6. 5 S n 3 . 5 A g、 融点摂氏 2 2 1度） 、 又は高温はんだ （たとえば組成 5 S n / 9 5 P b、 融点摂氏約 3 1 0度） 等が最適である。  Examples of the solder material for forming the solder bump 53 include eutectic solder (for example, composition 62 Sn Z95 Pb, melting point of 18 degrees Celsius) and tin silver solder (for example, composition 96.5 Sn The most suitable is 3.5 Ag, melting point of 211 degrees Celsius, or high-temperature solder (for example, composition 5 Sn / 95 Pb, melting point of about 310 degrees Celsius).
上記はんだ層 5 5形成用のはんだ材料としては、 メツキによる錫はんだ （たと えば組成 1 0 0 % S n、 融点摂氏 2 3 2度） 、 高温はんだ （たとえば組成 5 S n 9 5 P b、 融点摂氏約 3 1 0度） 、 錫銀はんだ （たとえば組成 9 6. 5 S n Z 3 . 5A g、 融点摂氏 2 2 1度） 等が最適である。  Examples of the solder material for forming the above solder layer 55 include tin solder by plating (for example, composition 100% Sn, melting point of 23 degrees Celsius), high-temperature solder (for example, composition 5Sn 95 Pb, melting point). Optimum is about 310 degrees Celsius, tin-silver solder (for example, composition 96.5 Sn Z 3.5 Ag, melting point 22 degrees Celsius).
バーンインテストは、 たとえば摂氏 1 2 5度程度の温度で通常よりも 1割程度 高い電源電圧を供給して （ある種のストレスを加えて） 行われる。 また必要に応 じて熱サイクル等も適用される。  The burn-in test is performed at a temperature of about 125 degrees Celsius, for example, by supplying a power supply voltage that is about 10% higher than usual (with some kind of stress). In addition, a heat cycle, etc. may be applied as necessary.
なお、 バーンインテスト後には被検査集積回路パッケージ等と検査装置側パッ ドは機械的に分離される。 すなわち機械的押しつけや一時的接着のための接着剤 を除去することにより、 電気的接触が解除される。 このときバンプの損傷は加熱 して物理的に融合させたときに比較して小さいので、 そのまま又は適切な回復処 理の後、 最終製品等に製品として実装することができる。  After the burn-in test, the integrated circuit package to be inspected and the inspection device side pad are mechanically separated. That is, the electrical contact is released by removing the adhesive for mechanical pressing or temporary bonding. At this time, the damage to the bumps is smaller than when they are physically fused by heating, so that the bumps can be mounted as they are or after a proper recovery process as final products.
上記金属粒子主要領域の金属すなわち、 心材としては、 たとえばニッケル、 チ タン、 クロム、 コノくルト、 鉄、 銅、 タングステン、 又はモリブデン、 或いはこれ らの少なくとも一つを主要成分とする合金等を使用することができる。 また、 金 属被覆層 5 9の材料としてはロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又 はパラジウム、 或いはこれらの少なくとも一つを主要成分とする合金等を使用す ることができる。  As the metal in the main region of the metal particles, that is, as a core material, for example, nickel, titanium, chromium, cono-colt, iron, copper, tungsten, or molybdenum, or an alloy containing at least one of these as a main component is used. can do. Further, as the material of the metal coating layer 59, rhodium, gold, silver, tin, lead, indium, platinum, palladium, or an alloy containing at least one of these as a main component can be used. .
(実施の形態 1 5 )  (Embodiment 15)
以上の各実施の形態において、 製造処理又は測定対象となるパッケージの構造 についてより詳しく説明する。  In each of the above embodiments, the structure of the package to be manufactured or measured will be described in more detail.
図 1 5において、 配線シ一ト 6 2の上面に半導体チップ 6 0が固着されており、 周辺の枠体 6 1で補強された部分には半導体チップ 6 0の各端子と配線シ一ト 6 2を介して電気的に接続されたはんだバンプ 5 3が形成されている。 In FIG. 15, the semiconductor chip 60 is fixed on the upper surface of the wiring sheet 62, and each terminal of the semiconductor chip 60 and the wiring sheet 6 are reinforced by a peripheral frame 61. Solder bumps 53 electrically connected via 2 are formed.
図 1 6において、 半導体チップ 6 0のデバイス形成面上の各端子 6 3はポリイ ミド多層配線 6 4を介して外部パッド 6 5と電気的に接続されており、 その各外 部パッド 6 5上にははんだバンプ 5 3が形成されている。  In FIG. 16, each terminal 63 on the device forming surface of the semiconductor chip 60 is electrically connected to an external pad 65 via a polyimide multilayer wiring 64, and on each external pad 65. Has solder bumps 53 formed thereon.
図 1 7において、 半導体チップ 6 0のデバイス形成面上の各端子 6 6上にはは んだバンプ 5 3が形成されている。  In FIG. 17, a solder bump 53 is formed on each terminal 66 on the device forming surface of the semiconductor chip 60.
図 1 8において、 多層配線基板 6 9の上面には半導体チップ 6 0がデバイス面 を上にして固着されており、 半導体チップ 6 0のデバイス形成面上の各端子 6 6 (図 1 7参照） はボンディングワイヤ 6 8等を介して多層配線基板 6 9と電気的 に接続されており、 更に多層配線基板 6 9を介してその対応する各外部パッド上 に形成されたはんだバンプ 5 3と電気的に接続されている。 上記半導体チップ 6 0とボンディングワイヤ 6 8はレジン 6 7により封止されている。  In FIG. 18, a semiconductor chip 60 is fixed on the upper surface of the multilayer wiring board 69 with the device side up, and each terminal 66 on the device formation surface of the semiconductor chip 60 (see FIG. 17). Are electrically connected to the multilayer wiring board 69 via bonding wires 68 and the like, and further electrically connected to the solder bumps 53 formed on the corresponding external pads via the multilayer wiring board 69. It is connected to the. The semiconductor chip 60 and the bonding wires 68 are sealed with a resin 67.
本発明のバーンィン工程は、 以上のような少なくとも外部端子がはんだバンプ 5 3のごとく酸化されやすいボール状の金属端子で作られた半導体集積回路装置 全般に適用可能である。 更に、 ボールピッチ （バンプピッチ） が l mmから 0 . 5 mm前後又はそれ以下の微細ピッチ製品に適用して特に有効である .  The burn-in process of the present invention is applicable to all semiconductor integrated circuit devices in which at least the external terminals are made of ball-shaped metal terminals that are easily oxidized like solder bumps 53 as described above. Furthermore, it is particularly effective when applied to fine pitch products whose ball pitch (bump pitch) is around lmm to 0.5mm or less.
以上、 本発明者によってなされた発明を発明の実施の形態 1〜1 5に基づき具 体的に説明したが、 本発明は前記発明の実施の形態 1〜1 5に限定されるもので はなく、 その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 たとえば、 図 8に示すバーンインボード 3 1では、 ソケット 2 5が 1 6個搭載 されている場合を説明したが、 その搭載数は 1 6個に限定されるものではなく、 1個または 1 6個以外の複数個であってもよい。 産業上の利用可能性  As described above, the invention made by the inventor has been specifically described based on Embodiments 1 to 15 of the invention.However, the invention is not limited to Embodiments 1 to 15 of the invention. Needless to say, various changes can be made without departing from the gist of the invention. For example, in the burn-in board 31 shown in Fig. 8, the case where 16 sockets 25 are mounted has been described. However, the number of mounted sockets is not limited to 16 but may be 1 or 16 Any number other than the above may be used. Industrial applicability
本発明によれば、 以下の効果が得られる。  According to the present invention, the following effects can be obtained.
( 1 ) 接続端子と拡大回路を一体化し、 従来の測定系の端子とフィルム上導体と が分離していた場合と比較して、 位置合わせ精度が向上する。 これは、 分離して いる場合は各々の位置合わせが必要となるため、 そこで位置ズレが発生する。 ま た、 フィルム等を用いると、 それ自体のズレ、 変形があり、 繰り返し使用により 精度は大幅に低減する。 更にバーンインの様に温度を掛ける場合には、 設定時に 位置ずれが無くても、 構成部品が多い場合は熱膨張の差から位置ズレが生じる。 このためこの構成を採用することにより、 従来限界とされてきた 0. 5mmピッ チ以下の微細ピッチの BGA， CS Pに対応できる。 (1) The connection terminal and the magnifying circuit are integrated, and the positioning accuracy is improved compared to the case where the terminal of the conventional measurement system and the conductor on the film are separated. In this case, when they are separated, they need to be aligned. Also, if a film or the like is used, the film itself may be displaced or deformed. Accuracy is greatly reduced. Furthermore, when temperature is applied like burn-in, even if there is no misalignment at the time of setting, if there are many components, misalignment occurs due to the difference in thermal expansion. Therefore, by adopting this configuration, it is possible to cope with BGA and CSP with a fine pitch of 0.5 mm pitch or less, which has been conventionally regarded as the limit.
(2) このことは、 パッケージ形態、 パッケージの有無に依存しないため、 ベア チップの検査、 バ一ンイン等にも適用できる。  (2) Since this does not depend on the package form and the presence or absence of the package, it can be applied to bare chip inspection, burn-in, and the like.
(3) 接続端子には、 はんだ等より固い金属粒子を用いているため、 はんだボー ルとの接触時に粒子の角がはんだボール表面の酸化膜を破りその新生面と金属粒 子が接触するため、 確実な電気接続を確保することができる。 また、 上記 （1) の理由から、 接続部の位置精度が高いことから、 バーンイン時にオープンあるい はショート等が接続部で発生しにくいため、 はんだボールとの電気的接触を確実 にとれる。  (3) Since metal particles that are harder than solder etc. are used for the connection terminals, the corners of the particles break the oxide film on the solder ball surface when they come into contact with the solder ball, and the new surface and the metal particles come into contact with each other. Reliable electrical connection can be ensured. In addition, because of the high positional accuracy of the connection part for the reason (1) above, an open or short circuit is unlikely to occur at the connection part during burn-in, so that electrical contact with the solder ball can be ensured.
(4) ソケット構成としては、 接続端子と拡大回路を一体化し、 他の加圧部、 ガ イド部を別構成としている。 拡大回路等の電気的部分は、 従来の生産性の高い露 光 ·現像方式で回路を形成できる。 また、 加圧部等は従来の生産性の高いモール ド技術で製造できる。 本発明の接続部分も、 生産性の高い印刷技術で製造できる。 この為、 従来、 電気的部分と機械的部分を混然と複雑な方式で製造していた場合 と比較して、 製造コスト低減が図れる。 また、 端子数、 形状等が異なる場合には 従来、 個々に製造していたソケットを、 例えば端子ピッチが同じであれば、 同じ 拡大回路を使える等の対応が容易であるので、 個々のパッケージに対して個々の ソケットを製造する必要がないため、 ソケットの低コスト化が容易に図れる。 (4) As for the socket configuration, the connection terminals and the expansion circuit are integrated, and the other pressurizing sections and guide sections are configured separately. For the electrical part such as the magnifying circuit, the circuit can be formed by the conventional high exposure and development method with high productivity. In addition, the pressurizing section and the like can be manufactured by the conventional molding technology with high productivity. The connection part of the present invention can also be manufactured by a printing technique with high productivity. For this reason, the manufacturing cost can be reduced as compared with the case where the electrical part and the mechanical part are conventionally manufactured in a complicated manner. If the number of terminals, shape, etc. are different, conventional sockets that have been manufactured individually can be easily accommodated, for example, if the terminal pitch is the same, the same enlarged circuit can be used. On the other hand, since there is no need to manufacture individual sockets, the cost of sockets can be easily reduced.
(5) 上記 （1) 及び （3) の理由により、 確実な検査が実施できることにより、 製品信頼性が向上する。 (5) For the reasons (1) and (3) above, reliable inspections can be performed, which improves product reliability.
(6) 上記 （4) の理由により、 従来方式のソケットで対応した場合には、 非常 に高価なソケットを準備しなければならない点と比較すると、 製品の低コスト化 が図れる。  (6) For the reason of (4) above, if the conventional socket is used, the cost of the product can be reduced compared to the point that an extremely expensive socket must be prepared.
(7) 金属粒子の平均粒径を 3 μπιから 50 μιη (更に望ましくは 10 μ mから 40/zm) とすることにより、 接続信頼性の向上を図ることができる。 即ち、 平 均粒径を 3 /zm未満にすると、 被接続端子に用いるはんだバンプ等の表面の酸化 膜を破る効果が減り、 被接続端子との接続信頼性が悪くなる。 また、 平均粒径が 50 μπιを越えると、 接続端子間の短絡が発生し易くなる。 し力 し、 十分な注意 をすれば平均粒径が 50 μπιを越える金属粒子の使用も可能であることは言うま でもない。 (7) The connection reliability can be improved by setting the average particle size of the metal particles to 3 μπι to 50 μιη (more preferably, 10 μm to 40 / zm). In other words, if the average particle size is less than 3 / zm, oxidation of the surface of the solder bumps etc. used for the connected terminals The effect of breaking the film is reduced, and the connection reliability with the connected terminal deteriorates. If the average particle size exceeds 50 μπι, a short circuit between the connection terminals is likely to occur. It goes without saying that metal particles with an average particle diameter exceeding 50 μπι can be used with great care and care.

Claims

請 求 の 範 囲 The scope of the claims
1 . 以下の工程を含む半導体集積回路装置の製造方法； 1. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部を構成する半導体集積回路チップ又はチップリ 一ド複合体の外部接続バンプ形成部に設けられたはんだバンプを、 配線板の第 1 の主面上に設けられ、 前記はんだバンプよりも硬い金属から成る複数の金属粒子 がはんだ層に埋め込まれた測定側電極パッド部に接触させる工程、 (a) solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are provided on the first main surface of the wiring board; A step of contacting a plurality of metal particles made of a metal harder than the solder bump with the measurement-side electrode pad portion embedded in the solder layer;
(b) 前記はんだバンプを、 前記複数の金属粒子と接触するように前記測定側電極 パッド部に押し当てた状態で前記半導体集積回路チップ又はチップリード複合体 中の半導体集積回路チップに対して、 バーンインテストを実行する工程、  (b) in a state where the solder bump is pressed against the measurement-side electrode pad portion so as to be in contact with the plurality of metal particles, with respect to the semiconductor integrated circuit chip in the semiconductor integrated circuit chip or the chip lead composite; The process of performing a burn-in test,
(c) 前記バーンインテス トの結果に基づいて、 半導体集積回路装置の良否又は等 級を決定する工程。  (c) determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
2 . 請求項 1記載の半導体集積回路装置の製造方法であって、 上記金属粒子は、 その主要領域がニッケル、 チタン、 クロム、 コバルト、 鉄、 銅、 タングステン、 又はモリブデン、 或いはこれらの少なくとも一つを主要成分とする合金からなる ことを特徴とする半導体集積回路装置の製造方法。  2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the main area of the metal particles is nickel, titanium, chromium, cobalt, iron, copper, tungsten, or molybdenum, or at least one of these. A method for manufacturing a semiconductor integrated circuit device, comprising: an alloy containing, as a main component,
3 . 請求項 2記載の半導体集積回路装置の製造方法であって、 上記金属粒子は、 その表面に前記主要領域を構成する成分よりも前記はんだバンプのはんだと反応 しにくい金属被覆層を有することを特徴とする半導体集積回路装置の製造方法。  3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the metal particles have a metal coating layer on the surface thereof, which is less likely to react with the solder of the solder bumps than a component constituting the main region. A method for manufacturing a semiconductor integrated circuit device, comprising:
4 . 請求項 3記載の半導体集積回路装置の製造方法であって、 上記金属被覆層は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又はパラジウム、 或いはこれら の少なくとも一つを主要成分とする合金からなることを特徴とする半導体集積回 路装置の製造方法。 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the metal coating layer comprises rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of these as a main component. A method for manufacturing a semiconductor integrated circuit device, comprising:
5 . 請求項 4記載の半導体集積回路装置の製造方法であって、 上記金属粒子の平 均粒径は 3 μ mから 5 0 μ mであることを特徴とする半導体集積回路装置の製造 方法。  5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the metal particles have an average particle size of 3 μm to 50 μm.
6 . 請求項 5記載の半導体集積回路装置の製造方法であって、 上記チップリード 複合体は C S Pパッケージであることを特徴とする半導体集積回路装置の製造方 法。 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the chip lead is provided. A method of manufacturing a semiconductor integrated circuit device, wherein the composite is a CSP package.
7 . 請求項 5記載の半導体集積回路装置の製造方法であって、 上記配線板はフィ ルム状配線板又はフィルム配線シートであることを特徴とする半導体集積回路装 置の製造方法。  7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the wiring board is a film-shaped wiring board or a film wiring sheet.
8 . 請求項 5記載の半導体集積回路装置の製造方法であって、 上記金属粒子は、 その主要領域がニッケル或いはニッケルを主要成分とする合金からなることを特 徴とする半導体集積回路装置の製造方法。  8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the main area of the metal particles is made of nickel or an alloy containing nickel as a main component. Method.
9 . 請求項 6記載の半導体集積回路装置の製造方法であって、 上記金属被覆層は、 ロジウム或いはロジウムを主要成分とする合金からなることを特徴とする半導体 集積回路装置の製造方法。  9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the metal coating layer is made of rhodium or an alloy containing rhodium as a main component.
1 0 . 請求項 7記載の半導体集積回路装置の製造方法であって、 上記金属粒子の 平均粒径は 1 0 mから 4 0 M mであることを特徴とする半導体集積回路装置の 製造方法。 1 0. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein, the method of manufacturing a semiconductor integrated circuit device an average particle diameter of the metal particles, characterized in that from 1 0 m is 4 0 M m.
1 1 . 以下の工程を含む半導体集積回路装置の製造方法；  11. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部を構成する半導体集積回路チップ又はチップリ 一ド複合体の外部接続バンプ形成部に設けられたはんだバンプを、 フィルム状配 線板の第 1の主面上に設けられ、 前記はんだバンプよりも硬い金属から成る複数 の金属粒子がバインダ層に埋め込まれた測定側電極パッド部に接触させる工程、  (a) Solder bumps provided on the external connection bump forming part of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are placed on the first main surface of the film wiring board. A step of contacting a plurality of metal particles made of a metal harder than the solder bump with the measurement-side electrode pad portion embedded in the binder layer;
(b) 前記はんだバンプを、 前記複数の金属粒子と接触するように前記測定側電極 パッド部に押し当てた状態で前記半導体集積回路チップ又はチップリード複合体 中の半導体集積回路チップに対して、 バーンインテストを実行する工程、 (b) in a state where the solder bump is pressed against the measurement-side electrode pad portion so as to be in contact with the plurality of metal particles, with respect to the semiconductor integrated circuit chip in the semiconductor integrated circuit chip or the chip lead composite; The process of performing a burn-in test,
(c) 前記バーンインテストの結果に基づいて、 半導体集積回路装置の良否又は等 級を決定する工程。  (c) a step of determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
1 2 . 請求項 1 1記載の半導体集積回路装置の製造方法であって、 上記金属粒子 は、 その主要領域がニッケル、 チタン、 クロム、 コバルト、 鉄、 銅、 タンダステ ン、 又はモリブデン、 或いはこれらの少なくとも一つを主要成分とする合金から なることを特徴とする半導体集積回路装置の製造方法。 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the metal particles have a main region of nickel, titanium, chromium, cobalt, iron, copper, tundatin, or molybdenum, or a metal region thereof. A method for manufacturing a semiconductor integrated circuit device, comprising: an alloy containing at least one main component.
1 3 . 請求項 1 2記載の半導体集積回路装置の製造方法であって、 上記金属粒子 は、 その表面に前記主要領域を構成する成分よりも前記はんだバンプのはんだと 反応しにくレ、金属被覆層を有することを特徴とする半導体集積回路装置の製造方 法。 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the metal particles are less reactive with the solder of the solder bumps than the constituents of the main region on the surface thereof. A method for manufacturing a semiconductor integrated circuit device, comprising a coating layer.
1 4 . 請求項 1 3記載の半導体集積回路装置の製造方法であって、 上記金属被覆 層は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又はパラジウム、 或いは これらの少なくとも一つを主要成分とする合金からなることを特徴とする半導体 集積回路装置の製造方法。  14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the metal coating layer is formed of rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of them. A method for manufacturing a semiconductor integrated circuit device comprising an alloy as a main component.
1 5 . 請求項 1 4記載の半導体集積回路装置の製造方法であって、 上記金属粒子 の平均粒径は 3 / mから 5 0 i mであることを特徴とする半導体集積回路装置の 製造方法。  15. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the average particle diameter of the metal particles is 3 / m to 50 im.
1 6 . 請求項 1 5記載の半導体集積回路装置の製造方法であって、 上記チップリ 一ド複合体は C S Pパッケージであることを特徴とする半導体集積回路装置の製 造方法。  16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the chip lead composite is a CSP package.
1 7 . 以下の工程を含む半導体集積回路装置の製造方法；  17. A method for manufacturing a semiconductor integrated circuit device including the following steps;
(a) 半導体集積回路装置の主要部を構成する半導体集積回路チップ又はチップリ 一ド複合体の外部接続バンプ形成部に設けられたはんだバンプを、 配線板の第 1 の主面上に設けられ、 前記はんだバンプよりも硬い金属から成る複数の金属粒子 がはんだ層に埋め込まれた測定側電極パッド部に接触させる工程、  (a) solder bumps provided on the external connection bump forming portion of the semiconductor integrated circuit chip or chip lead composite constituting the main part of the semiconductor integrated circuit device are provided on the first main surface of the wiring board; A step of contacting a plurality of metal particles made of a metal harder than the solder bump with the measurement-side electrode pad portion embedded in the solder layer;
(b) 前記はんだバンプを、 前記複数の金属粒子と接触させた状態で前記半導体集 積回路チップ又はチップリード複合体中の半導体集積回路チップに対して、 バー ンインテストを実行する工程、  (b) performing a burn-in test on the semiconductor integrated circuit chip or the semiconductor integrated circuit chip in the chip-lead composite in a state where the solder bumps are in contact with the plurality of metal particles;
(c) 前記バーンインテス トの結果に基づいて、 半導体集積回路装置の良否又は等 級を決定する工程。  (c) determining the quality or grade of the semiconductor integrated circuit device based on the result of the burn-in test.
1 8 . 請求項 1 7記載の半導体集積回路装置の製造方法であって、 上記金属粒子 は、 その主要領域がニッケル、 チタン、 クロム、 コバルト、 鉄、 銅、 タンダステ ン、 又はモリブデン、 或いはこれらの少なくとも一つを主要成分とする合金から なることを特徴とする半導体集積回路装置の製造方法。  18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the main area of the metal particles is nickel, titanium, chromium, cobalt, iron, copper, tundatin, or molybdenum, or any of these. A method for manufacturing a semiconductor integrated circuit device, comprising: an alloy having at least one as a main component.
1 9 . 請求項 1 8記載の半導体集積回路装置の製造方法であって、 上記金属粒子 は、 その表面に前記主要領域を構成する成分よりも前記はんだバンプのはんだと 反応しにくレ、金属被覆層を有することを特徴とする半導体集積回路装置の製造方 法。 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the metal particles A method of manufacturing a semiconductor integrated circuit device, further comprising a metal coating layer formed on a surface of the semiconductor integrated circuit, the component being less reactive with the solder of the solder bump than a component constituting the main region.
2 0 . 請求項 1 9記載の半導体集積回路装置の製造方法であって、 上記金属被覆 層は、 ロジウム、 金、 銀、 錫、 鉛、 インジウム、 白金、 又はパラジウム、 或いは これらの少なくとも一つを主要成分とする合金からなることを特徴とする半導体 集積回路装置の製造方法。  20. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the metal coating layer is formed of rhodium, gold, silver, tin, lead, indium, platinum, or palladium, or at least one of these. A method for manufacturing a semiconductor integrated circuit device comprising an alloy as a main component.
PCT/JP1998/004226 1997-09-19 1998-09-18 Method for manufacturing semiconductor integrated circuit device WO1999015908A1 (en)

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JP4707910B2 (en) * 1999-08-03 2011-06-22 健一 二宮 Article design support system and method, and medium storing program for article design support
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