WO1998051014A1

WO1998051014A1 - Dual band phase locked loop using independent charge pumps

Info

Publication number: WO1998051014A1
Application number: PCT/US1998/008942
Authority: WO
Inventors: Daniel E. Fague; Theodore L. Tewksbury
Original assignee: Analog Devices, Inc.
Priority date: 1997-05-02
Filing date: 1998-05-01
Publication date: 1998-11-12

Abstract

A dual band PLL circuit having a single VCO divider which is multiplexed between two VCOs by a switch at the VCO input. Two VCOs are used, one for each of the frequency bands. Two separate loop filters are utilized to drive each of the VCOs, and separate charge pumps that drive the loop filters. In this manner, complete isolation of the VCO is achieved. The charge pump which is active drives an optimized loop filter for that VCO charge pump output current. The charge pump that is inactive is placed in a high impedance mode, which preserves the charge of the loop filter in the inactive loop. This feature allows for quick re-acquisition when the inactive loop is re-activated. Also, the VCO gain constants need not have any special relationship. The loops for each of the VCOs can be designed independent of each other.

Description

DUAL BAND PHASE LOCKED LOOP USING INDEPENDENT CHARGE PUMPS

BACKGROUND OF THE INVENTION

The invention relates to a dual band phase locked loop using independent charge pumps.

Dual band PLLs are widely used in data transmission systems. As a specific example, conventional cellular telephony systems typically are configured to use two frequency bands. These frequency bands are offset such that most implementations of radio frequency front ends would use two separate voltage controlled oscillators (VCOs) to cover each frequency band.

The VCOs would normally be controlled by two separate phase locked loop (PLL) divider pairs. The first being a programmable divider that divides the VCO frequency of the first frequency band, and the second being a programmable divider that divides the VCO frequency of the second frequency band. A third and fourth divider would be used to divide a (normally) common crystal reference frequency, one for each VCO divider. However, the two full PLLs would be too expensive of a solution in some systems. The GSM and DCS-1800 systems are examples of dual band systems. Since these systems are becoming a consumer driven market, the use of two PLLs is too expensive a solution. There exists a need for a more efficient implementation of a dual band PLL.

FIG. 1 is a block diagram of a conventional dual band

PLL 100 using a single PLL divider pair 101. The dual band

PLL 100 includes a VCO 102 and a resonator tank 104 associated with the VCO. The resonator tank is an LC circuit configured with an inductor 106 and a capacitor 108 in parallel. A secondary capacitor 110 is switched into the resonator tank via a controlled band switch 109. A first frequency divider (N counter) 116 of the PLL divider pair 101 is connected to both the output of the VCO 102 and the output node 122 of the PLL. A second frequency divider 118 (R counter) is connected to receive a reference signal from a reference signal source 120. The divider pair is coupled to the input of a phase detector 114. The phase detector 5 outputs a difference signal to a low pass loop filter 112, which in turn is connected to the resonator tank 104.

In the implementation of PLL 100, the single VCO 102 is a band switching VCO. The extra secondary capacitor 110 in the resonator tank 104 of the VCO is used to alter the

10 resonance frequency of the VCO, causing it to oscillate at a lower frequency when the capacitor 110 is switched into the tank, and at a higher frequency when the capacitor is switched out of the tank. The PLL 100 can have problems addressing frequency bands that are widely separated. It is

15 typically used in systems that require two narrowband VCOs, one for transmit and one for receive frequencies. In these systems, the transmit and receive frequencies have only a small separation. Also, it requires an extra signal from the baseband circuitry to drive the band switch 109 on the

20 VCO.

FIG. 2 is a block diagram of an alternative implementation of a conventional dual band PLL 200 using a single PLL divider pair 201. The PLL has two VCOs 202 and 204, each having respective outputs 206 and 208. The

25 outputs of the VCOs are both coupled to a first frequency divider 210 (N counter) of the divider pair 201. A second frequency divider 212 (R counter) is connected to receive a reference signal from a reference signal source 214. The divider pair 201 is coupled to the input of a phase detector

30 216. The phase detector outputs a difference signal to a low pass loop filter 218, which in turn is coupled to both the VCOs.

In the PLL 200, a VCO is used for each frequency band of operation. The single divider pair is multiplexed

35 between the two VCOs. The single charge pump (not shown) output is also used for a single loop filter. The loop filter, however, drives two separate VCO tuning varactors (not shown). The advantage of this approach is that the PLL can remain locked at all times, since the charge pump is always driving a single loop filter. However, a disadvantage is that one of the VCOs may be influenced by the other in the form of load pulling or higher phase noise, since they both are connected to the same loop filter. Also, it may be more difficult to optimize the loop filter when driving two VCOs. Finally, the VCOs must have a fixed relationship between their respective gain constants, since the PLL charge pump has only a limited number of output currents.

SUMMARY OF THE INVENTION

Accordingly, the invention provides a dual band PLL circuit having a single VCO divider which is multiplexed between two VCOs by a switch. at the VCO input. Two VCOs are used, one for each of the frequency bands. Two separate loop filters are utilized to drive each of the VCOs, and separate charge pumps that drive the loop filters . In this manner, complete isolation of the VCO is achieved. The charge pump which is active drives an optimized loop filter for that VCO charge pump output current. The charge pump that is inactive is placed in a high impedance mode, which preserves the charge of the loop filter in the inactive loop. This feature allows for quick re-acquisition when the inactive loop is re-activated. Also, the VCO gain constants need not have any special relationship. The loops for each of the VCOs can be designed independent of each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a conventional dual band phase locked loop circuit; FIG. 2 is a schematic block diagram of another conventional dual band phase locked loop circuit;

FIG. 3 is a schematic block diagram of a dual band phase locked loop circuit in accordance with the invention; and FIG. 4 is schematic diagram of a signal interface system utilizing the PLL circuit of the invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 3 is a schematic block diagram of a dual band phase locked loop circuit 300 which utilizes independent charge pumps. The PLL circuit 300 has two VCOs 302 and 304, each having respective outputs 306 and 308. The outputs of the VCOs are both coupled to a first frequency divider 310 (N counter) of a VCO divider pair 301. A second frequency divider 312 (R counter) is connected to receive a reference signal from a reference signal source 314. The divider pair 301 is coupled to the input of a phase detector 316. The phase detector outputs a difference signal which is switched via a switch 318 between a first charge pump 320 and low pass loop filter 322, and a second charge pump 324 and low pass loop filter 326, which in turn are respectively coupled to both the VCOs.

It will be appreciated by those of skill in the art that the frequency dividers 310, 312 and phase detector can be programmed via a serial interface register 330 to implement a desired switching scheme. In the illustrated embodiment, the register 330 receives instructions from an associated CPU or other microcontroller via a three-wire bus . In the dual band PLL circuit 300, the single VCO divider 301 is multiplexed between the two VCOs 302,304 by the switch 318 at the VCO (or pre-scaler) input. Two VCOs are used, one for each of the frequency bands. The invention utilizes two separate loop filters that drive each of the VCOs, and separate charge pumps that drive the loop filters. In this manner, complete isolation of the VCO is achieved. The charge pump which is active drives an optimized loop filter for that VCO charge pump output current. The charge pump that is inactive is placed in a high impedance mode, which preserves the charge of the loop filter in the inactive loop. This feature allows for quick re-acquisition when the inactive loop is re-activated. Also, the VCO gain constants need not have any special relationship. The loops for each of the VCOs can be designed independent of each other. FIG. 4 is a schematic diagram of a signal interface system 400 utilizing the PLL circuit of the invention. The system 400 corresponds to a dual band cellular telephone radio in which two distinct and separate radio frequency bands, GSM and DCS, are used to convey the telephone conversation. At any given moment in time, only one of the frequency bands will be used, i.e., either GSM or DCS. Each of the two frequency bands, GSM and DCS, are further divided into two separate bands, transmit and receive. When using either the GSM or the DCS band, both the transmit and receive band of the chosen band will be used.

Proceeding from right to left in the schematic diagram of FIG. 4, a digitized, compressed, and coded voice signal is sent to a transmit modulator 404 via transmit I,Q DATA lines 402. The modulator is preferably a quadrature modulator, but is represented in the schematic by a simple mixer. The output of this modulator is filtered via a bandpass filter 408 centered at the output carrier frequency. The output carrier frequency is generated by dividing by two the output of an on-chip voltage controlled oscillator (VCO) 406 centered at 596 MHz. The result of the divide-by-2 is a transmit carrier frequency of 298 MHz.

After filtering the modulated signal to remove modulator second harmonics (at twice and thrice the carrier frequency of 298 MHz), the signal is further upconverted in frequency to the transmit band of either the GSM or DCS frequency band. In the schematic, it will be understood that this operation is done by splitting the output signal from the bandpass filter 408 into two signal branches via a splitter 409, each feeding a different integrated circuit, i.e., GSM VCO/Mixer circuit 410 and DCS VCO/Mixer circuit 412, respectively. The outputs of upconverting mixers 411, 413 are then filtered by bandpass filters 414, 416, and amplified by driver amplifiers 417-420 in an IC Dual LNA/Driver circuit 422. The output of the driver amplifiers are then fed to respective power amplifiers 424 and 426. The outputs of the power amplifiers are fed to a quadrapϊexer 428 and from there are fed to an antenna 430 for broadcast.

Similarly, in the receive path, signals are received in the antenna 430, fed through the quadraplexer 428 to receive low noise amplifiers (LNAs) 432-435 in the respective bands (GSM-receive and DCS-receive, respectively). The outputs of the LNAs are fed to bandpass filters 436, 438 to limit the amplitude of out-of-band signals. The outputs of the bandpass filters are fed to downconverting mixers 440, 442 in each of the GSM VCO/Mixer and DCS VCO/Mixer ICs, respectively. The outputs of the downconverting mixers are combined off chip and fed to a single surface acoustic, wave (SAW) filter 444 at the receive first intermediate frequency (IF), in this case 246 MHz. The IF SAW reduces the amplitude of adjacent channel signals. The output of the IF SAW is fed to another downconverting mixer 446, which translates the 246 MHz signal to 52 MHz, where it is filtered by another bandpass filter 448. The output of this bandpass filter is fed to a quadrature demodulator 450, designated by a single mixer in the diagram. The output of the quadrature modulator is sent to the data receiver (not shown) via receive I,Q DATA lines 452 to be decoded, decompressed, and converted to an analog signal suitable for a speaker.

To accomplish the frequency conversions to and from the desired transmit and receive bands of both the GSM and DCS bands, local oscillator (LO) signals must be generated. The mixers multiply the incoming signal with the LO signal and output the result. By proper choice of the LO signal, the proper IF and transmit/receive frequencies can be generated. Phase-locked loop (PLL) frequency synthesizers are known to generate stable LO signals with low noise and good performance. In the system illustrated in FIG. 4, a potential of three frequency synthesizers are needed: one for the 596 MHz oscillator 406, one for a 1200 MHz oscillator 454 of circuit 410, and one for a 2100 MHz oscillator 456 of circuit 412.

When either of the DCS or GSM bands is used, the other is not. This is due to the time division duplex (TDD) nature of the overall system. Thus, the actual required number of synthesizers is only two at any given time. Hence, in a conventional system, each oscillator must be locked by a PLL, but only two would run at a given time. By the use of the PLL circuit of the invention, the number of PLLs can be reduced to two. This is achieved because the dividers in the RF PLL can be re-programmed to generate either the GSM or the DCS frequencies. Since the dividers are programmed routinely anyway, there is no additional overhead in software. In order to keep the GSM LO and the DCS LO as isolated as possible, the output of the PLLs phase detector controls two separate charge pumps . Each of these charge pump outputs are connected to a separate loop filter and VCO tuning port. For ideal separation, the modulus control signal coming from the PLL chip is separated into two output pins, one for the GSM LO and one for the DCS LO. In an alternate embodiment, the modulus control line can be a single output line that is connected to both pre-scaler inputs. For ideal isolation, the outputs of the pre-scalers on the GSM VCO/mixer circuit and the DCS VCO/mixer circuit are connected to separate input pins on the PLL chip. In another alternate embodiment, the input port is a single pin.

Since one PLL is used to lock up two separate VCOs, there is need for only one additional PLL. This additional PLL is used to lock the IF VCO (600 MHz), and it has a dedicated charge pump output and modulus output and frequency/pre-scaler input. Thus, the total number of PLLs needed for the dual band radio system is two: one for the two RF VCOs, and one for the IF VCO.

The foregoing description has been set forth to illustrate the invention and is not intended to be limiting. Since modifications of the described embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the scope of the invention should be limited solely with reference to the appended claims and equivalents thereof. What is claimed is:

Claims

1. A phase locked loop circuit comprising: a first loop circuit having a first charge pump; and a second loop circuit having a second charge pump.

2. The circuit of claim 1, wherein said first loop circuit further comprises a first controlled oscillator with an output, and a first loop filter coupled to drive said first oscillator.

3. The circuit of claim 2, wherein said second loop circuit further comprises a second controlled oscillator with an output, and a second loop filter coupled to drive said second oscillator.

4. The circuit of claim 3 further comprising a frequency divider coupled to the outputs of said first and second oscillators.

5. The circuit of claim 4 further comprising means for selectively coupling said first and second charge pumps to said frequency divider: to drive said first and second loop filters, respectively.

6. The circuit of claim 4 further comprising means for alternately coupling said first and second charge pumps to said frequency divider to activate one of said charge pumps to drive the respective loop filter while holding the other charge pump in a high impedance state.

7. A dual band phase locked loop circuit comprising: ^ΓÇó first and second controlled oscillators having respective outputs; first and second loop filters coupled to drive said first and second oscillators, respectively; a frequency divider coupled to the outputs of said first and second oscillators; and first and second charge pumps selectively coupled to said frequency divider to drive said first and second loop filters, respectively.

8. The circuit of claim 7 further comprising means for alternately coupling said first and second charge pumps to said frequency divider to activate one of said charge pumps to drive the respective loop filter while holding the other charge pump in a high impedance state.

9. A dual band phase locked loop circuit comprising: first and second controlled oscillators having respective outputs coupled to a frequency divider; first and second loop filters coupled to drive said first and second oscillators, respectively; and first and second charge pumps alternately coupled to said frequency divider to activate one of said charge pumps to drive the respective loop filter while holding the other charge pump in a high impedance state.