WO1998044409A1

WO1998044409A1 - Microcomputer, electronic apparatus and information processing method

Info

Publication number: WO1998044409A1
Application number: PCT/JP1998/001392
Authority: WO
Inventors: Makoto Kudo; Yoshiyuki Miyayama; Satoshi Kubota
Original assignee: Seiko Epson Corporation
Priority date: 1997-04-03
Filing date: 1998-03-27
Publication date: 1998-10-08
Also published as: TW421759B

Abstract

A microcomputer, an electronic apparatus and an information processing method which realize various highly functional processings with small scale hardware are provided. An ALU executes an instruction issued by an instruction issuing means under the control of a CPU. When an 8-bit mirror instruction is issued, the bit 7 is transferred to the position of the bit 0, the bit 6 is transferred to the position of the bit 1, the bit 5 is transferred to the position of the bit 2, ..., and the bit 0 is transferred to the position of the bit 7 for the byte 3 - byte 0. When a swapping instruction is issued, the byte 3 is transferred to the position of the byte 0, the byte 2 is transferred to the position of the byte 1, the byte 1 is transferred to the position of the byte 2 and the byte 0 is transferred to the position of the byte 3. If the swapping instruction is executed after the 8-bit mirror instruction is executed, a 32-bit mirror processing is realized. Reversely, an 8-bit mirror instruction may be executed after a swapping instruction is executed. The ALU includes an 8-bit mirror circuit, a swapping circuit and a multiplexer for multiplexing the outputs of the mirror circuit and the swapping circuit.

Description

Description Microcombination, electronic equipment and information processing method

[Technical field]

The present invention relates to a micro combination, an electronic device, and an information processing method. [Background technology]

In recent years, there has been an increasing demand for microcomputers that can be installed in electronic devices such as home game machines, power navigation systems, printers, and portable information terminals, and that can realize advanced information processing.

In such a micro-combination, various processes are performed, such as image processing for image generation, sound processing for sound generation, and data conversion processing during data transfer between memory and a general-purpose registry. There is a demand for high functionality. For example, until now

This is because if a microcomputer can perform image processing and sound processing instead of the DSP (Digital Signal Processor), image processing IC, and sound processing IC, the system can be simplified and the cost of products can be reduced.

On the other hand, in order to reduce the cost, power consumption, and size of electronic devices in which microcomputers are incorporated, or to reduce the cost of microcomputers themselves, microcomputers are required. It is necessary to reduce the size of the hardware in the evening.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a micro computer capable of realizing various high-performance processes on a small hardware scale. An object of the present invention is to provide an electronic device and an information processing method.

[Disclosure of the Invention]

In order to solve the above problems, a microcomputer according to the present invention receives an instruction, A control circuit that analyzes the instruction and performs control for executing the instruction; an arithmetic circuit that executes arithmetic processing corresponding to the instruction under the control of the control circuit; Instruction issuing means for issuing, to the control circuit, an instruction having first data having first to N-th bit strings as operands, wherein the instruction issuing means stores the first bit in the first bit. The process of moving to the bit position of M and the second bit

A process of moving the (M-1) bit to the position of the bit, a process of moving the (M-1) bit to the position of the second bit, and a process of moving the Mth bit to the first bit. Issue an M-bit mirror instruction for performing the process of moving to the position of the unit for each of the first to N-th bit strings in the first data stream. When a Tomira instruction is issued, a bit moving process corresponding to the instruction is performed. According to the present invention, the process is performed as follows, taking M = 8 and N = 4 as an example. That is, the instruction issuing means issues an 8-bit mirror instruction. Then, for example, the first bit of the first bit string is at the eighth bit position, the second bit is at the seventh bit position, and the seventh bit is at the second bit position. Then, the eighth bit moves to the first bit position. The same bit movement is performed on the second, third, and fourth bit strings. This makes it possible to execute 8-bit mirror processing. Usually, according to the realization of the 8-bit Tomira first processing like this in _c present invention need to perform, for example, four zero instructions, can be realized with 8 bits Tomira treated with execution of one instruction, Processing time can be reduced. Also, the memory area for storing instruction codes can be reduced, and the necessity of using a temporary register can be eliminated.

Also, in the present invention, the instruction issuing means may move the first bit string to the position of the N-th bit string, and may shift the second bit string to the (N−1) -th bit string. , The process of moving the (N-1) th bit sequence to the position of the second bit sequence, and the process of moving the Nth bit sequence to the position of the first bit sequence Issue a swap instruction to be applied to the first data, and when the swap instruction is issued, the arithmetic circuit performs a bit string movement process corresponding to the instruction. And

According to the present invention, taking the case of M = 8, N = 4 as an example, the following processing is performed. You. That is, the instruction issuing means issues a swap instruction. Then, for example, the first bit string is at the fourth bit string position, the second bit string is at the third bit string position, and the third bit string is at the second bit string position. , fourth bit string becomes possible to execute the _c Thus swap process of moving to the first bit column position. Normally, such swap processing requires execution of, for example, 10 instructions. According to the present invention, since the swap processing can be realized by executing one instruction, the processing time can be reduced. Also, the memory area for storing instruction codes can be reduced, and the necessity of using a temporary register can be eliminated.

Also, in the present invention, the instruction issuing means may move the first bit to the position of the Mth bit, and may move the second bit to the position of the (M−1) th bit. The processing of moving the (M-1) th bit to the position of the second bit, and the processing of moving the Mth bit to the position of the first bit. Issuing an M-bit mirror instruction for each of the 1st to Nth bit strings in the data stream to move the first bit string to the position of the Nth bit string; Moving the second bit string to the position of the (N-1) th bit string; and moving the (N-1) th bit string to the (N-1) th bit string.

The process of moving the N-th bit sequence to the position of the first bit sequence and the process of moving the N-th bit sequence to the position of the first bit sequence are performed on the first data after the process of the M-bit mirror instruction. The arithmetic circuit issues a swap instruction to be performed overnight, and when the M-bit mirror instruction and the swap instruction are issued, performs a bit moving process and a bit string moving process corresponding to the instruction. It is characterized by the following.

According to the present invention, the process is performed as follows, taking M = 8 and N = 4 as an example. That is, first, an 8-bit mirror instruction is issued. Then, a swap instruction is issued, and the swap processing is performed on the first data after the 8-bit mirror processing is performed. This makes it possible to realize M X N (= 32) bit mirror processing.

Further, in the present invention, the instruction issuing means may include a process of moving the first bit string to a position of the N-th bit string, and a step of shifting the second bit string to the (N−1) -th bit string. Move to position and move the (N-1) th bit string to the position of the second bit string And a process of moving the Nth bit sequence to the position of the first bit sequence by issuing a swap instruction for the first data, and changing the first bit to the Mth bit sequence. The process of moving the second bit to the position of the (M-1) th bit, the process of moving the second bit to the position of the (M-1) th bit, and the process of moving the (M-1) th bit to the position of the second bit. And the process of moving the M-th bit to the position of the first bit, the first to the N-th in the first data after the processing of the swap instruction. The arithmetic circuit issues an M-bit mirror instruction to be applied to each of the bit strings, and when the M-bit mirror instruction and the step instruction are issued, the bit shift processing corresponding to the instruction is performed. It is characterized by performing column moving processing. Even cowpea to thus execute the M bit Bok mirror instruction after executing the swap instruction, _c also present invention can be realized MXN bit Tomira first processing, the arithmetic circuit, the first data and the Suwappu instruction An M-bit mirror circuit that receives any one of the first data having undergone the above-described processing and performs a bit transfer process corresponding to the M-bit mirror instruction, the first data and the M-bit mirror instruction A swap circuit that receives any of the first data that has undergone the above-described processing and performs a bit string movement process corresponding to the swap instruction; and the M-bit mirror when the M-bit mirror instruction is issued, A multiplexer for selecting an output of the mirror circuit and selecting the output of the swap circuit when the swap instruction is issued. This makes it possible to execute the M-bit mirror instruction, the swap instruction, and the MXN bit mirror instruction at high speed. Also, since there is no need to provide an MXN bit mirror circuit and the number of input signals to the multiplexer can be reduced, the circuit size can be significantly reduced.

Further, the microcomputer according to the present invention is characterized in that each of the first to Nth bit strings is composed of 8 bits. This makes it possible to convert little endian into big endian, or vice versa, using a step instruction, for example.

Further, the electronic device according to the present invention includes the microcomputer described above, an input source for data to be processed by the microcomputer, and an output for outputting data processed by the microcomputer. And a device. This In this way, the micromirror can perform various processing such as image mirror inversion processing, which has been performed by DSP, etc., and reduce the cost, size, and power consumption of electronic devices. Can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a microcomputer according to the present invention. FIGS. 2A and 2B are diagrams for explaining the processing and operation of the first embodiment _c . FIGS. 3A to 3H show a method for implementing 8-bit mirror processing without using an 8-bit mirror instruction. It is a figure for explaining.

4A, 4B is a _c Figure 5A is a diagram for explaining the processes and operations Embodiment 2, FIG. 5B is a diagram of the order describes endian, the big endian.

FIGS. 6A to 6H are diagrams for explaining a technique for realizing a swap process without using a swap instruction.

7A, 7B, 7 C is a view a is _c diagram 8A for illustrating the process of Example 3, FIG. 8B, FIG. 8 C are diagrams for explaining operation of the embodiment 3 ₍ 9A and 9B are diagrams for explaining the configuration of the ALU.

FIG. 10 is a diagram illustrating a configuration example of an 8-bit mirror circuit.

FIG. 11 is a diagram illustrating a configuration example of the swap circuit.

FIG. 12 is a configuration example of a microcomputer according to the fourth embodiment.

FIGS. 13A, 13B, and 13C are examples of internal block diagrams of various electronic devices.

FIGS. 14A, 14B, and 14C are examples of external views of various electronic devices. [Best Mode for Carrying Out the Invention]

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

(Example 1)

Embodiment 1 is an embodiment in which 8-bit mirror processing is realized by one instruction. Figure 1 FIG. 2 shows a block diagram of the microcomputer 101 of this embodiment. Note that this block diagram is a block diagram common to the first embodiment and the second and third embodiments described later.

The microcomputer 101 in FIG. 1 includes, for example, a CPU 102 (control circuit) for processing 32-bit data, a BCU (bus control unit) 108 for controlling a bus, and an internal memory 110. And On the other hand, an external memory 114 is provided outside the microcomputer 101.

Here, the CPU 102 receives instructions such as an 8-bit mirror instruction and a swap instruction issued by the instruction issuing means 100, analyzes the received instruction, and performs control for executing the analyzed instruction. In the embodiment, a 16-bit length instruction is used. The CPU 102 also includes a PC (program counter) 120, a general-purpose register 103 including 16 32-bit registers R0 to R15, and a product-sum operation circuit 104 for executing a product-sum operation. And an ALU (arithmetic logical operation unit) 132 that performs logical operations such as addition, subtraction, multiplication and division of data, logical operations such as OR, AND and logical shift, and 8-bit mirror processing and step processing described later. The instruction issuing means 100 may be included in the internal memory 110 or may be included in the external memory 114.

The general-purpose register 103, the product-sum operation circuit 104, and the ALU 132 perform data transfer using P A-BUS and WW-BUS which are internal buses of the CPU 102. The BCU 108 is a bus for reading various instructions and various data required for executing instructions from the internal memory 110 and the external memory 114, and for writing data to the internal memory 110 and the external memory 114. Perform control.

However, the scope of application of the present invention is not limited by whether the memory is built in the microcomputer or provided outside the microphone computer. In addition, it is not limited by the bit length of the data to be processed by the microcomputer, the product-sum operation circuit, the ALU, or the number of general-purpose registers built in the microcomputer.

The feature of this embodiment is that 8-bit mirror processing is realized by executing one instruction. For example, as shown in Figure 2A, 50 bytes (first data) is converted to 4 bytes. It is assumed that the data is divided and the highest byte is defined as byte 3, byte 2, byte 1, byte 0 (first, second, third, and fourth bit strings; N = 4). Each of these bytes 3 to 0 is composed of 8 bits (M bits).

In the present embodiment, as shown in FIG. 2A, mirror processing is performed on each of these bytes 3 to 0 (first to fourth bit strings). That is, the processing shown in the following (1) to (8) is performed on each of the bytes 3 to 0.

(1) Bit 7 (Move first bit to Bit 0 (move to eighth bit)

(2) Bit 6 (moves bit 2 to bit 1 (moves to bit 7

(3) bit 5 (move third bit to bit 2 (move to sixth bit

(4) Bit 4 (Move fourth bit to bit 3 (Move to fifth bit

(5) Bit 3 (Move bit 5 to Bit 4 (move to bit 4

(6) Bit 2 (Move bit 6 to Bit 5 (Move to bit 3

(7) Bit 1 (move bit 7 to bit 6 (move to bit 2)

(8) Bit 0 (Move the 8th bit to Bit 7 (Move to the position of the 1st bit) In this embodiment, such an 8-bit mirror process executes one 8-bit mirror instruction. It is realized just by doing.

Next, the operation of this embodiment will be described with reference to FIG. 2B. First, the instruction issuing means 100 of FIG. 1 issues an 8-bit mirror instruction represented by, for example, the following mnemonic symbol.

MI RROR% R 1,% R 0 The meaning of this instruction is that 8-bit mirror processing is performed on data stored in register R 0 (source register) in general register 110 in FIG. This means that the result is stored in the register R1 (destination register). When the CPU 102 in FIG. 1 receives the 8-bit mirror instruction, the CPU 102 that analyzes the 8-bit mirror instruction performs the following processing. That is, the data stored in the register R0 is first output to the internal bus PA-BUS (step SI in FIG. 2B), and the ALU 132 receives it (step S2). Then, the ALU 132 executes the 8-bit mirror processing described in FIG. 2A and the above (1) to (8) (step S3). When the 8-bit mirror processing is completed, the ALU 132 outputs the processing result to WW-BUS (step S4), and the processing result is stored in the register R1 (step S5).

In this way, 8-bit mirror processing can be performed. As a result, processing such as mirror inversion of images becomes possible, and the processing of microcomputers can be enhanced. The details of the circuit that performs 8-bit mirror processing (see Fig. 10) will be described later.

When there is no 8-bit mirror instruction as in the present embodiment, it is necessary to create a program as shown below to realize the 8-bit mirror processing. Regis evening to store 1 day of Mira (see Figure 3A)

R2 Temporary Regis Evening

R3 evening to store R3 mask pattern

Regis evening to store R5 mirror results

LD.W% R3, 0x80808080 R3 <= 0x80808080 Set mask pattern

(See Fig. 3B)

LD.W ¾R2 ₅ % R1 R2 ku = R1 Copy the data to be mirrored

RL% R2, 0x07 Rotate R2 7 bits left

(See Fig. 3C)

AND% R2,% R3 AND mask pattern with R2

LD.W ¾R5,% R2 R5 <= R2 R2

(See Fig. 3D)

RR% R3, 0x01; R3 2 0x40404040 Mask pattern right by 1 bit (See Figure 3E)

LD.W ¾R2 ₃ % R1 R2 <= Rl Copy mirrored data RL% R2, 0x05 Rotate R2 to left by 5 bits

(See Fig. 3F)

AND% R2,% R3 AND mask pattern with R2 OR ¾R5,% R2 OR R2 with R5 (see Figure 3G)

RR ¾R3, 0x01 R3 = 0x20202020 Rotate mask pattern right by 1 bit

LD.W ¾R2,% R1 R2 <= Rl Copy data to be mirrored

RL ¾R2, 0x03 Rotate R2 left 3 bits

AND% R2,% R3 AND mask pattern with R2

OR ¾R5,% R2 OR R2 with R5

RR% R3, 0x01 R3 = 0xl0101010 Rotate mask pattern right by 1 bit

LD.W% R2, ¾R1 R2 <= Rl

RL ¾R2, 0x01 Rotate R2 one bit to the left

AND% 2,% R3 AND mask pattern with R2

OR% R5,% R2 OR R2 with R5

RR% R3, 0x01 R3 = 0x08080808 Rotate mask pattern right by 1 bit

LD.W% 2,% R1 R2 <= Rl Copy data to be mirrored

RR% R2, 0x01 Rotate R2 1 bit right

AND% 2,% R3 AND mask pattern with R2

OR% R5,% R2 OR R2 with R5 RR% R3, 0x01 R3 = 0x04040404 Mask pattern 1 bit right

t one mouth

LD.W% R2,% R1 R2 <= Rl

RR% R2, 0x03 Rotate R2 right by 3 bits

AND% R2,% R3 AND mask pattern with R2

OR% R5 ₃ % R2 OR R2 to R5

RR% R3, 0x01 R3 = 0x02020202 Rotate mask pattern right by 1 bit

LD.W% R2, ¾R1 R2 <= Rl Copy data to be mirrored

RR% R2, 0x05 Rotate R2 5 bits right

AND% R2, ¾R3 AND mask pattern with R2

OR ¾R5,% R2 OR R2 with R5

RR% R3, 0x01 R3 = 0x01010101 Rotate mask pattern right by 1 bit

LD.W% R2,% R1 R2 <= R1

RR% R2, 0x07 Rotate R2 Ίbit right

AND% R2,% R3 AND mask pattern with R2

OR ¾R5, ¾R2 OR R2 to R5

(See Fig. 3H)

.., 02, 01, and 00 in FIG. 3A to FIG. 3H indicate bit positions in the 32-bit data. On the other hand, “0”,, and 1 in the mask pattern in Fig. 3 and Fig. 3 represent binary numbers.

As described above, 40-instruction execution is required to implement 8-bit mirror processing in the usual way. On the other hand, according to the present embodiment, 8-bit mirror processing can be realized by executing one instruction. Therefore, the processing time can be significantly reduced. In addition, the memory area for storing instruction codes can be reduced, and hardware can be downsized. It is. In addition, it is possible to eliminate the need for a temporary registration evening (R2 above).

(Example 2)

Embodiment 2 is an embodiment in which the swap processing is realized by executing an instruction once. In the present embodiment, as shown in FIG. 4A, a data buffer having bytes 3 to 0 (first to fourth bit strings) each consisting of 8 bits (M bits) is used. Swaps 50 (1st day) in units of bytes. That is, the following processes (9) to (12) are performed.

(9) Move byte 3 (first bit string) to byte 0 (fourth bit string)

(10) Byte 2 (second bit string) is moved to bit 1 (third bit string)

(11) Move byte 1 (third bit string) to byte 2 (second bit string)

(12) Byte 0 (the fourth bit string) is moved to the position of byte 3 (the first bit string). In this embodiment, such byte-by-byte swap processing is executed by executing one swap instruction. Only realized.

Next, the operation of this embodiment will be described with reference to FIG. 4B. First, the instruction issuing means 100 in FIG. 1 issues a swap instruction represented by, for example, the following monic symbol.

SWAP% R 2,% R 1 The meaning of this instruction is to perform swap processing on the data stored in the register R 1 (source register) in the general-purpose register 103, and to store the result in the register. It means that it is stored in R2 (Destination registration).

When the CPU 102 receives this swap instruction, the following processing is performed by the CPU 102 that has analyzed the swap instruction.

That is, the data stored in the register R1 is output to the internal data bus PA-BUS (step T1 in FIG. 4B), and the ALU 132 receives it (step T2). The ALU 132 is connected to the switch described in FIG. 4A and (9) to (12) above. The backup process is executed (step T3). When the swap processing is completed, the ALU 132 outputs the processing result to WW-BUS (step T4), and the processing result is stored in the register R2 (step T5).

By doing so, it becomes possible to perform swap processing in byte units. As a result, for example, little endian data shown in Fig. 5A can be converted to big endian data shown in Fig. 5B, and conversely, big endian data can be converted to little endian data. it can. This makes it possible to effectively use data created on an information processing device with a little endian architecture on an information processing device with a big endian architecture, and vice versa. . The details of the circuit that performs the swap processing (see Fig. 11) will be described later.

If there is no step command as in the present embodiment, it is necessary to create the following program to realize the step processing.

R1 Data to be swapped (see Figure 6A)

R2 Temporary Regis Evening

R3 mask pattern

R5 Step Results

LD.W% R3, OxffOOffOO; R3 <= OxffOOffOO Set mask pattern

(See Fig. 6B)

LD.W% R2, ¾R1; R2 <= R1 Copy data to be swapped

RR% R2, 0x10; R2 8 bits right

(See Fig. 6C)

AND% R2,% R3; AND the mask pattern with R2 LD.W% R5, ¾R2; Copy R2 to the registry of the swap result (see Figure 6D)

RR% R3, 0x10; R3 <= OxOOffOOff Mask pattern right by 8 bits R

Rotate (see Fig. 6E)

LD.W% R R2 5,% R1; R2 <= R1 Copy data to be swapped RL% R2, 0x10; R2 8 bits left

Two

(See Fig. 6F)

AND% R2,% R3; AND mask pattern with R2

(See Fig. 6G)

OR R2 to R5

(See Fig. 6H)

.., -02, 01, and 00 in FIGS. 6A to 6H indicate bit positions in the 32-bit data. On the other hand, “0” and “1” in the mask patterns of FIGS. 6B and 6E represent binary numbers.

As described above, if you try to implement swap processing in the usual way, you need to execute 10 instructions. On the other hand, according to the present embodiment, step processing can be realized by executing an instruction once. Therefore, the processing time can be significantly reduced. Also, the memory area for storing instruction codes can be reduced, and hardware can be downsized. In addition, the need for Temporary Regis evening (R2 above) can be eliminated.

(Example 3)

The third embodiment is an embodiment that realizes a 32-bit mirror process by combining an 8-bit mirror instruction and a step instruction.

In this embodiment, as shown in FIG. 7A, a data block 50 having bytes 3 to 0 (first to fourth bit strings) each having 8 bits (M bits) is provided. First, the 8-bit mirror processing described in the first embodiment is performed on the first data. That is, the processes (1) to (8) described above are performed on each of the bytes 3 to 0.

Next, the swap processing described in the second embodiment is performed on the data 50 after the 8-bit mirror processing. That is, the above-described processes (9) to (12) are performed.

By doing so, a 32-bit mirror process as shown in Fig. 7C is possible. This enables processing such as mirror inversion of the image, —Improve the functionality of evening processing.

In the above, swap processing is performed after 8-bit mirror processing.

As shown in B, even if an 8-bit mirror process is performed after the swap process,

32-bit mirror processing can be realized.

Next, the operation of this embodiment will be described with reference to FIGS. 8A, 8B, and 8C. First, the instruction issuing means 100 of FIG. 1 is represented, for example, by the following mnemonic symbol.

Issue an 8-bit mirror instruction (PC 120 indicates an 8-bit mirror instruction as shown in Figure 8C).

MIRROR% 1,% R 0 When the CPU 102 in FIG. 1 receives the 8-bit mirror instruction, the CPU 102 that analyzes the 8-bit mirror instruction performs the processing shown in FIG. 8A. Note that the processing in steps U1 to U5 in FIG. 8A is the same as the processing in steps S1 to S5 in FIG. 2B, and a description thereof will be omitted.

Next, the instruction issuing means 100 issues a swap instruction represented by, for example, the following mnemonic symbol (PC 120 indicates a swap instruction).

SWAP% R 2,% R 1 When the CPU 102 receives this swap instruction, the CPU 102 that has analyzed the swap instruction performs the processing shown in FIG. 8B. Note that the processing in steps V1 to V5 in FIG. 8B is the same as that in steps T1 to T5 in FIG. However, the data after the 8-bit mirror processing has been performed is stored in the register R1 in step V1 in FIG.

As described above, the data obtained by applying the 32-bit mirror processing (8-bit mirror processing and swap processing) to the data of the register R0 is stored in the register R2. Next, a configuration example of the ALU 132 (arithmetic circuit) will be described. As shown in FIG. 9A, the ALU 132 includes an 8-bit mirror circuit 20, a swap circuit 22, a multiplexer 30, and various circuits (not shown) for arithmetic and logical operations.

Here, the 8-bit mirror circuit 20 receives the 32-bit PA31 to PA0 (the first data or the first data subjected to the swap processing) from the PA—BUS and receives these PA31 to P0. An 8-bit mirror process is performed based on AO, and the resulting 32-bit DA31 to DA0 are output to the multiplexer 30. The swap circuit 22 receives PA31 to PA0 (first data or the first data subjected to 8-bit mirror processing) from PA-BUS, performs a swap process based on these PA31 to PA0, and as a result, And outputs the 32-bit DB 31 to DB 0 to the multiplexer 30. The multiplexer 30 selects one of DA 31 to DA 0 and DB 31 to DB 0 based on the select signal, and outputs the resultant 32-bit WW 31 to WW 0 to WW-BUS. The multiplexer 30 also has a function of multiplexing the outputs of various circuits (not shown) for arithmetic and logical operations.

FIG. 10 shows a configuration example of the 8-bit mirror circuit 20. As shown in FIG. 10, this 8-bit mirror circuit 20 allows? 8 31 to 0 8 24,? 8:30 to 0825,

PA24 is passed on to DA31. P A 23 becomes D A 16,

PA22 is transmitted to DA17, and PA16 is transmitted to DA23. Also, 815 is transmitted to 88, PA14 is transmitted to DA9, and PA8 is transmitted to DA15. PA7 to DA0, PA6 to DA1, PA

0 is transmitted to D A 7. In this way, mirror processing for every 8 bits becomes possible. FIG. 11 shows a configuration example of the swap circuit 22. As shown in FIG. Eighteen-? 24 is transmitted to 087 to 080, PA23 to PA16 is transmitted to 0815 to 088, PA15 to PA8 is transmitted to DB23 to DB16, and PA7 to PA (HiDB31 to DB24. Processing can be performed.

When performing 32-bit mirror processing by ALU 132 with the configuration of Fig. To do. That is, first, DA31 to DA0 are selected by a selector signal, and WW31 to WW0 subjected to 8-bit mirror processing are output to WW-BUS. Then, these WW31 to WW0 are input to the ALU 132 again through the general-purpose register and the PA-BUS. Then, DB 31 to DB 0 may be selected by the selector signal. Or, conversely, first, DB31 to DB0 are selected by the selector signal, and the swapped WW31 to WW0 are output to WW-BUS. Then, these WW31 to WW0 are again input to the ALU 132 via the general-purpose register and the PA-BUS. Then, DA31 to DA0 are selected by the selector signal.

As described above, according to the ALU 132 of FIG. 9A, all of the 8-bit mirror processing, the step processing, and the 32-bit mirror processing can be performed. By enabling the skip processing, for example, the endian conversion described in FIGS. 5A and 5B can be performed. On the other hand, by enabling 8-bit mirror processing and 32-bit mirror processing, it is possible to perform mirror inversion of images in image processing.

Moreover, according to the ALU 132 in FIG. 9A, these processes can be completed in one clock period, so that information processing optimal for a RISC microcomputer can be realized.

FIG. 9B shows the configuration of the ALU of the comparative example of this embodiment. The ALU 134 includes a 32-bit mirror circuit 24 for performing 32-bit mirror processing (see FIG. 7C) in addition to the 8-bit mirror circuit 20 and the step circuit 22. Even with the configuration of FIG. 9B, all of the 8-bit mirror processing, swap processing, and 32-bit mirror processing can be realized. However, according to this configuration, an additional 32-bit mirror circuit 24 is required. In addition, since the multiplexer 31 must multiplex not only DA 31 to DA 0 and DB 31 to DB 0 but also DC 31 to DC 0, the circuit scale of the multiplexer 31 also becomes large. For example, when a mirror circuit requires one gate for one bit input, providing a 32-bit mirror circuit 24 having a 32-bit input increases the circuit scale by only 32 gates. For example, if the multiplexer requires one gate for one bit input, the circuit scale is increased by 32 gates in Fig. 9B because the multiplexer input is increased by 32 bits. growing. Therefore, according to the configuration of Figure 9B, the circuit size of the ALU is at least

This increases only 64 gates, which leads to higher product costs and higher power consumption.

On the other hand, according to the present embodiment, it is possible to realize all the processes of the 8-bit mirror process, the swap process, and the 32-bit mirror process without increasing the circuit scale.

(Example 4)

Embodiment 4 is an embodiment showing a detailed example of the micro combination of the present invention. As shown in FIG. 12, the microcomputer 700 of the second embodiment is a 32-bit microcomputer, and includes a CPU 710, a R〇M720, a RAM730, a high-frequency oscillator 910, a low-frequency oscillator 920, and a reset. Circuit 930, prescaler 940, 16-bit programmable timer 950, 8-bit programmer, timer circuit such as timer 960, clock timer 970, etc., data transfer control circuit such as intelligent DMA 980 and high-speed DMA 990, interrupt controller 800, Serial Inn Yuichi Face 810, BCU (Bus Control Unit)

740, analog interface circuits such as A / D converter 830 and D / A converter 840, I / O circuits such as input port 850, output port 860, I / O port 870, and so on. Includes various buses 750, 760 and various pins 890 to be connected.

This microcomputer 700 formed on a single-chip semiconductor substrate is a RISC microcomputer that can process 32 bits of data. It employs a pipeline and load store architecture, and executes almost all instructions in one cycle. All instructions are described with a fixed length of 16 bits, which results in a very small instruction code size.

As described in the first, second, and third embodiments, the microcomputer 700 performs the 8-bit mirror processing, the step processing, and the 32-bit mirror processing on a small-scale circuit configuration. Can be realized. For this reason, processing that was previously performed by DSPs, ICs dedicated to image processing, ICs dedicated to sound processing, etc. can be substituted, and the cost and size of electronic devices incorporating this microcombiner 700 are reduced. It becomes possible.

(Example 5)

The fifth embodiment is an embodiment relating to an electronic device including the micro-computer described in the first, second, third and fourth embodiments.

For example, Fig. 13A shows an internal block diagram of a power navigation system, which is one of the electronic devices, and Fig. 14A shows its appearance. The operation of the force navigation system is performed using the remote controller 510, and the position detection unit 520 detects the position of the vehicle based on information from the GPS and the gyro. Information such as maps is stored in CDROM 530 (information storage medium). The image memory 540 is a memory serving as a work area for image processing, and the generated image is displayed to the driver using the image output unit 550. The microcomputer 500 receives data from a data input source such as a remote control 510, a position detection unit 520, and a CDROM 530, performs various processes, and outputs the processed data to an image output unit 550. Output using an output device such as. In the conventional navigation system, image processing (graphic processing) is performed by DSP or dedicated image processing IC. For this reason, there were two processors in the electronic equipment, for example, a CISC-type microcomputer and a DSP, and the system became complicated. If the microcomputer described in the first, second, third, and fourth embodiments is used, 8-bit mirror processing, 32-bit mirror processing, and swap processing can be realized with a small circuit scale, without using a DSP or the like. It is possible to realize image processing such as image mirror inversion required by the force navigation system.

FIG. 13B shows an internal block diagram of a game device which is one of the electronic devices, and FIG. 14B shows an external view thereof. In this game device, the image memory 590 is used as a work area based on the player operation information from the game controller 560, the game program from the CDROM 570, the player information from the IC card 580, and the like. A game image and a game sound are generated and output using the image output unit 610 and the sound output unit 600. If the microcomputer 500 described in the first, second, third, and fourth embodiments is adopted, a game image can be obtained by using an 8-bit mirror processing function, a 32-bit mirror processing function, and a swap processing function. It becomes possible to perform various processes required for generation and generation of game sounds.

Figure 13C shows an internal block diagram of one of the electronic devices, the pudding, and Figure 14C shows its external view. In this printing, based on the operation information from the operation panel 620 and the character information from the code memory 630 and the font memory 640, a print image is generated using the bitmap memory 650 as a work area. Output using the print output unit 660. The state of the pudding is indicated to the user using the display panel 670. If the microcomputer 500 described in the first, second, third, and fourth embodiments is adopted, a print image can be generated using the 8-bit mirror processing function, the 32-bit mirror processing function, and the swap processing function. It is possible to perform various processes necessary for the above. In addition, the electronic devices to which the micro combination of the present invention can be applied include, in addition to the above, for example, a mobile phone (cellular phone), a PHS, a pager, an audio device, an electronic organizer, an electronic desk calculator, a POS terminal, and a sunset panel. Devices, projectors, word processors, personal computers, televisions, viewfinder-type or monitor-directed video tape recorders, etc.

It should be noted that the present invention is not limited to the first, second, third, fourth, and fifth embodiments, and various modifications can be made within the scope of the present invention.

For example, in the above embodiment, a description has been given of a case where mirror processing and swap processing are performed on data including the first to fourth bit strings each consisting of 8 bits. It is not limited to. For example, the present invention can be applied to a mirror process or a swap process for the data of the first to Nth bit strings each including M bits. However, if swap processing is used to change the endian, it is desirable that M = 8.

Also, the present invention relates to a micro-computer, especially a RISC-type micro-computer. It is particularly effective when applied in the evening, but other uses are also possible.

Claims

The scope of the claims

(1) a control circuit that receives an instruction, analyzes the instruction, and performs control for executing the instruction;

An operation circuit that executes an operation process corresponding to the instruction under the control of the control circuit, and a first data unit having first to N-th bit strings each including M bits. Instruction issuing means for issuing an instruction to be a peland to the control circuit, wherein the instruction issuing means comprises:

The process of moving the first bit to the position of the Mth bit, the process of moving the second bit to the position of the (M-1) th bit, and the process of moving the first bit to the (M-1) th bit The process of moving the bit to the position of the second bit and the process of moving the Mth bit to the position of the first bit are the first to Nth bit strings of the first data. Issue an M-bit mirror instruction for each of the

The arithmetic circuit includes:

A microcomputer according to claim 1, wherein when the M-bit mirror instruction is issued, a bit move process corresponding to the instruction is performed.

(2) a control circuit that receives the instruction, analyzes the instruction, and performs control for executing the instruction;

An arithmetic circuit that executes arithmetic processing corresponding to the instruction under the control of the control circuit; and first data having first to N-th bit strings, each including M bits, as an operand Instruction issuing means for issuing an instruction to the control circuit, wherein the instruction issuing means comprises:

A process of moving the first bit sequence to the position of the N-th bit sequence, a process of moving the second bit sequence to the position of the (N-1) -th bit sequence, The process of moving the bit sequence of (1) to the position of the second bit sequence and the process of moving the N-th bit sequence to the position of the first bit sequence are performed in the first Issue a swap instruction

The arithmetic circuit includes: When the swap instruction is issued, the microcomputer performs a bit string movement process corresponding to the instruction.

(3) a control circuit that receives the instruction, analyzes the instruction, and performs control for executing the instruction;

An arithmetic circuit that executes arithmetic processing corresponding to the instruction under the control of the control circuit; and first data having first to N-th bit strings, each of which is formed of M bits, as an operand. And an instruction issuing means for issuing an instruction to the control circuit.

A process of moving the first bit to the position of the Mth bit, a process of moving the second bit to the position of the (M−1) th bit, and a process of moving the first bit to the (M−1) th bit. The process of moving the M bit to the position of the first bit and the process of moving the Mth bit to the position of the first bit are the first to Nth bits of the first data. Issue an M-bit mirror instruction for each of the columns,

A process of moving the first bit sequence to the position of the N-th bit sequence, a process of moving the second bit sequence to the position of the (N-1) -th bit sequence, The process of moving the bit sequence of 1) to the position of the second bit sequence and the process of moving the Nth bit sequence to the position of the first bit sequence are performed by the M-bit mirror instruction. Issue a swap instruction to be applied to the processed first data,

The arithmetic circuit includes:

A microcomputer according to claim 1, wherein when the M-bit mirror instruction and the swap instruction are issued, a bit move process and a bit string move process corresponding to the instruction are performed.

(4) a control circuit that receives the instruction, analyzes the instruction, and performs control for executing the instruction;

An arithmetic circuit that executes arithmetic processing corresponding to the instruction under the control of the control circuit; and first data having first to N-th bit strings, each including M bits, as an operand Instruction issuing means for issuing an instruction to the control circuit, wherein the instruction issuing means comprises: A process of moving the first bit sequence to the position of the Nth bit sequence, a process of moving the second bit sequence to the position of the (N-1) th bit sequence, — The process of moving the bit sequence of 1) to the position of the second bit sequence and the process of moving the Nth bit sequence to the position of the first bit sequence are performed in the first Issues a swap instruction for

A process of moving the first bit to the position of the Mth bit, a process of moving the second bit to the position of the (M-1) th bit, and a process of moving the first bit to the (M-1) th bit. The process of moving the bit to the position of the second bit and the process of moving the Mth bit to the position of the first bit are the first data to which the processing of the step instruction has been performed. Issue an M-bit mirror instruction for each of the 1st to Nth bit strings in the evening,

The arithmetic circuit includes:

A micro-computer, wherein when the M-bit mirror instruction and the swap instruction are issued, a bit moving process and a bit string moving process corresponding to the instruction are performed.

(5) In claim 3,

The arithmetic circuit includes:

An M-bit mirror circuit that receives one of the first data and the first data processed by the step instruction and performs a bit moving process corresponding to the M-bit mirror instruction;

A swap circuit that receives one of the first data and the first data that has been processed by the M-bit mirror instruction, and performs a bit string movement process corresponding to the swap instruction;

A multiplexer for selecting an output of the M-bit mirror circuit when the M-bit mirror instruction is issued, and a multiplexer for selecting an output of the swap circuit when the swap instruction is issued. A special feature of a microcomputer.

(6) In claim 4,

The arithmetic circuit includes:

Either the first data or the first data processed by the step instruction Receiving an M-bit mirror instruction, and performing a bit moving process corresponding to the M-bit mirror instruction

—Circuit and

A swap circuit that receives a first data and one of the first data processed by the M-bit mirror instruction and performs a bit string movement process corresponding to the swap instruction;

A multiplexer for selecting an output of the M-bit mirror circuit when the M-bit mirror instruction is issued, and a multiplexer for selecting an output of the swap circuit when the swap instruction is issued. Microcomputer evening to do.

(7) In claim 1,

A microcomputer according to claim 1, wherein each of said first to Nth bit strings is composed of 8 bits.

(8) In claim 2,

A microcomputer, wherein each of the first to Nth bit strings is composed of 8 bits.

(9) In claim 3,

(10) In claim 4,

(11) The microcomputer according to any one of claims 1 to 10,

An input source for data processing to be processed in the micro-viewing process;

An output device for outputting data processed by the microcomputer.

(12) An instruction having an operand of a first data having first to Nth bit strings each composed of M bits is issued, and a process corresponding to the instruction is executed by the first data processor. Information processing method to be applied to

The process of moving the first bit to the position of the Mth bit and the process of moving the second bit to the (M (1) a process of moving the bit position of 1), a process of moving the (M-1) th bit to the position of the second bit, and a process of moving the Mth bit to the position of the first bit. Issuing an M-bit mirror instruction for performing each of the first to N-th bit strings of the first data;

A process of moving the first bit sequence to the position of the N-th bit sequence, a process of moving the second bit sequence to the position of the (N-1) -th bit sequence, — The process of moving the bit sequence of 1) to the position of the second bit sequence and the process of moving the Nth bit sequence to the position of the first bit sequence are performed by the M-bit mirror instruction. Issuing a swap instruction to be applied to the processed first data.

(13) An instruction is issued with the first data as an operand having first to N-th bit strings each composed of M bits, and the processing corresponding to the instruction is executed by the first data processor. Information processing method to be applied to

A process of moving the first bit sequence to the position of the N-th bit sequence, a process of moving the second bit sequence to the position of the (N-1) -th bit sequence, — The process of moving the bit sequence of 1) to the position of the second bit sequence and the process of moving the Nth bit sequence to the position of the first bit sequence are performed on the first data. Issuing a swap instruction to be performed

A process for moving the first bit to the position of the Mth bit, a process for moving the second bit to the position of the (M-1) th bit, and a process for moving the first bit to the (M-1) th bit. The process of moving the bit to the position of the second bit and the process of moving the Mth bit to the position of the first bit are the first data processed by the swap instruction. Issuing an M-bit mirror instruction to be applied to each of the first to N-th bit strings.