WO1998028731A2

WO1998028731A2 - Liquid crystal display signal driver system and method

Info

Publication number: WO1998028731A2
Application number: PCT/US1997/023768
Authority: WO
Inventors: Stephen Bily; Christopher A. Ludden
Original assignee: Cirrus Logic, Inc.
Priority date: 1996-12-20
Filing date: 1997-12-22
Publication date: 1998-07-02
Also published as: WO1998028731A3

Abstract

An LCD signal driver system and circuit are provided. Current sharing may be utilized both at a system level and within the signal driver circuit in order to reduce power consumption. The system and circuit permit the use of a selectable data bus width, for example a single width or double width mode. The decoder architecture utilized allows multiplexing of two channels and eliminates the need for high voltage and low voltage circuitry for each column driver output. The outputs of the driver lines may be precharged to improve power usage and voltage transient characteristics. An improved level shifting circuit having outputs of varying voltage ranges may also be utilized. A decoder architecture is utilized in which the number of decoder cells per channel may be reduced by a factor of two. Improved data gating and feedback gating are also provided through the use of an improved decoder cell. The decoder cell may operate over a wide voltage range and may utilize an inherent level shifting and latch/reset function.

Description

LCD SIGNAL DRIVER CIRCUIT SYSTEM AND METHOD

BACKGROUND OF THE INVENTION

This invention relates to signal driver systems and circuits for a liquid crystal display ("LCD"), and more particularly, to a digital-in/analog-out signal driver system and circuit for controlling the gray levels of LCD pixels in LCD column driving applications.

Signal driver circuits are commonly employed with liquid crystal displays. The driver circuit typically accepts digital video data as an input and provides an analog voltage output to each particular LCD pixel column. Generally, each column in- the LCD must be uniquely addressed by a signal or column driver and given the proper analog voltage in order to achieve the desired transmissivity (i.e., the desired shade of gray or color). Moreover, it is desirable that the output voltage range of a driver circuit be wide to allow for a high pixel contrast ratio. An example signal driver circuit is shown in pending U.S. application Serial No. 08/240,026, filed May 9, 1994, the disclosure of which is expressly incorporated herein by reference.

For color LCDs, each pixel is composed of 3 sub-pixel elements representing the primary colors of red, green and blue. For example, a color VGA panel having a resolution of 640 columns x 480 rows of uniquely addressable pixels will have 3 x 640 columns, or 1,920 columns. Typically, the signal driver circuit has one driver output for each column. Thus controlling an LCD panel requires a large number of driver outputs that consume considerable circuit area. Since circuitry size impacts the costs of a signal driver, it is desirable to reduce the size of signal drivers.

As LCD panel technology has improved, it has become desirable to render images with more continuous gray scales or to have more unique colors available. The voltage control required from signal drivers has, therefore, become more complex. However, it is also desirable to reduce the cost of a driver circuit by decreasing the physical size of the signal driver and to reduce the amount of power dissipated by the driver circuit. Therefore, it is desirable to have a signal driver which balances the need for more discrete analog voltage levels while consuming less area and dissipating less power. Most LCD panel architectures utilize one of two driving methods, Vcom modulation and full range drivers. Vcom modulation refers to the modulation of the common plate of the LCD panel between a positive and negative voltage (or alternatively between two positive voltages, one being higher than the other). In applications utilizing Vcom modulation, the voltage range of the signal column driver need not be as large as the voltage range of full range drivers as modulation of the common plate provides additional voltage swing.

In applications utilizing full range drivers, the LCD common plate is held at a fixed DC potential located at or near the center of the entire voltage range. The full range driver provides voltages which are both positive and negative with respect to the fixed DC potential. Full range drivers may be provided as having a low voltage range, typically 5 to 6 volts with the common plate potential therefore being 2.5 to 3 volts. Alternatively, the full range driver may have a higher voltage range, which typically may be 8 to 12 volts, thus utilizing a 4 to 6 volt DC potential near the center of the entire voltage range. In applications utilizing low voltage full range drivers, standard 5 volt CMOS processes may be used to design and fabricate the column signal drivers. The use of high voltage full range drivers may be accomplished by utilizing high voltage fabrication processes or lower voltage fabrication processes in combination with various circuit techniques to limit the voltages across any given device in order to prevent breakdown from occurring.

SUMMARY OF THE INVENTION

The present invention provides an improved signal driver system and circuit for use with LCD panels. In particular, a variety of system level and circuit level embodiments are provided which may be used together or independently of one another. In one embodiment, power consumption may be reduced through the use of current sharing utilized both at a system level and within a signal driver circuit. At a system level, current sharing may occur in the supply voltage circuit. The system level current sharing within a reference voltage generator may occur between a plurality of sets of buffer amplifiers. In one embodiment a set of buffer amplifiers operating at a low voltage range and a set of buffer amplifiers operating at a high voltage range may be provided. In order to reduce power consumption, the quiescent current through one set of the amplifiers may also be utilized to operate another set of the amplifiers. Within the signal driver circuit itself, current sharing may be accomplished between multiple resistor strings. The high voltage range resistor string and low voltage range resistor string may be configured so that current may be shared between the strings rather than directed towards ground.

In another embodiment, a selectable data bus width may be provided. The digital data bus within the signal driver circuit may be a single pixel wide or wider such as a double pixel wide data bus. The bus width may be selected by the user rather than hardwired at an integrated circuit chip level. An input pin of the signal driver circuit may be utilized so that the user may select as to whether a single wide, double wide, etc. mode is to be used. Thus, a LCD signal driver bus architecture is provided in which the width may be user programmable such that one, two, or more pixels of data may be simultaneously provided across the data bus.

In another embodiment there is provided a decoder channel multiplexing architecture in which decoders may be multiplexed between two columns. In a particular embodiment, a set of high voltage decoders and a set of low voltage decoders may be multiplexed between two adjacent channels. One of the two channels is dedicated for low voltage operation while the other is dedicated for high voltage operation. Using multiplexing, the operation of two adjacent channels (either high voltage or low voltage) can be switched via the muxes on a line by line or frame basis. This eliminates the need for high voltage and low voltage circuitry to exist for each column driver output, thus saving circuitry and chip area. In another embodiment a driver output precharge is provided. Precharging of the output lines is provided to improve power usage and voltage transient characteristics. The use of precharging driver outputs is particularly advantageous with dot inversion or column inversion panels where approximately one-half of the outputs would be driven to the high polarity while the other half of the outputs would be driven to the low polarity. When the outputs need to switch polarity, rather than dumping all charge to ground, charge from the high polarity outputs is dumped to the other polarity outputs so that approximately 50% power savings may be obtained. Furthermore, by precharging the lines prior to switching from high to low or vice versa, the voltage transients that the circuitry will be exposed to will be lessened.

In another embodiment, an improved level shifting circuit is provided. The level shifting circuit allows for multiple outputs. These outputs may include both translation of the input voltage and expansion of the input voltage range. Thus, a standard digital logic level input may be shifted to a high voltage range such as, for example, between 8 and 4 volts (other voltage ranges may be used, for example, 10 to 5 volts or 12 to 6 volts). Further, the level shifting circuit provides a low voltage range output, from a mid-level voltage to ground, for example, 4 volts to 0 volts. Finally, the level shifting circuit provides a full range output which may operate from the high voltage level to ground, for example between 8 volts to ground.

In yet another embodiment, an improved decoder architecture and layout is provided. Chip area and circuit performance characteristics may be improved by reducing the number of decoder cells per channel by a factor of two (for example from 64 to 32) and providing a single bit (for example the LSB) selection through switches at the output lines. The reduction in the number of decoder cells allows for an improved decoder column layout in which decoders from two channels may be interleaved within one column of decoder cells.

In yet another embodiment, an improved decoder cell is provided. One embodiment of the decoder cell allows the decoders to operate from 0 volts to a high voltage such as 10 volts. This cell also utilizes inherent level shifting and latch/reset function. Improved data gating and feedback inverter gating is also provided. Rather than having data enabled for a long period of time, the data that is presented to the decoders is only enabled during a data enable interval and the latching function of the cell will hold the cell in the proper condition until the next reset. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a liquid crystal display system.

FIG. 1 A is a block diagram showing the data, control, and power signals utilized by an LCD module.

FIG. IB is a typical timing diagram for the signals of FIG. 1 A.

FIG. IC is a block diagram overview of an LCD module.

FIG. 2 is another block diagram of the circuitry of an LCD module.

FIG. 3 is a block diagram of a signal driver circuit.

FIG. 3A illustrates a decoder circuit for use in a signal driver circuit.

FIG. 3B illustrates a decoder circuit for a signal driver circuit.

FIG. 4 is a block diagram of an LCD module.

FIG. 5 illustrates a reference voltage generator circuit.

FIG. 5B illustrates multiple resistor strings for use with current sharing within a signal driver circuit.

FIG. 5C illustrates a weighted resistor voltage divider for use in a signal driver circuit.

FIG. 6 illustrates one conventional prior art embodiment for implementing a single width data bus for a signal driver circuit.

FIG. 6 A illustrates the addressing circuit utilized in the circuit of FIG. 6. FIG. 7 illustrates a circuit for use with implementing a user selectable data bus width.

FIG. 7 A illustrates address circuitry for use with the circuit of FIG. 7.

FIG. 7B illustrates another address circuitry for use with the circuit of FIG. 7.

FIG. 8 illustrates a block diagram for a decoder channel architecture for decoder channel multiplexing.

FIG. 8A illustrates a decoder channel multiplexing architecture utilizing a driver output precharge.

FIG. 8B illustrates a decoder channel multiplexing architecture utilizing level shifting inherently within the high voltage decoders.

FIG. 9 is a circuit diagram for a multiplexer for use with the circuits shown in FIGS. 8 - 8B.

FIG. 10 is a graph of the column output voltage for a signal driver circuit column output utilizing precharge.

FIG. 10A is a graph of a gate voltage for use with a precharge circuit.

FIG. 10B illustrates an example circuit for generating the gate control signals for use in a precharge circuit.

FIG. 11 is a block diagram of a signal driver circuit utilizing level shifting circuits.

FIG. 12 is a prior art level shifting circuit.

FIG. 13 is a level shifting circuit according to the present invention.

lo FIG. 13 A is a functional diagram of the circuit of FIG. 13.

FIG. 14 is another embodiment of a level shifting circuit according to the present invention.

FIG. 15 is a decoder architecture for a signal driver circuit according to the prior art.

FIG. 16 is a decoder architecture for use with a signal driver circuit according to the present invention.

FIGS. 17 and 18 are circuit diagrams of illustrative switching mechanisms for use with the decoder architecture of FIG. 16.

FIG. 19 illustrates a physical circuit layout for a signal driver circuit according to the prior art.

FIG. 20 is a physical circuit layout interleaving multiple channels within a single decoder column according to the present invention.

FIG. 20A is a block diagram illustrating the gating of data for the low and high voltage decoders.

FIGS. 21-23 are illustrative embodiments of circuits for use as decoder cells.

FIGS. 24 and 25 are timing diagrams of control signals for decoder cells.

FIG. 26 illustrates a block diagram of an embodiment in which storage registers are incorporated within the high voltage decoders.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

System Overview FIG. 1 illustrates a typical LCD application. Generally, a host computer 3 having a central processing unit 2 and a graphics controller 4 provides digital data to an LCD module 6 in order to visually display data for a user. FIG. 1 A and FIG. IB illustrate typical data, control and power signals provided from a host computer 3 to an LCD module 6 and their associated timing diagrams.

FIG. IC and FIG. 2 provide an overview of the circuitry typically contained within LCD module 6. For example, LCD module 6 may contain an LCD control ASIC 8, a voltage supply circuit 10, a gate-driver interface 17, a DC-DC converter 19 and color LCD panel 12. LCD panel 12 may be, for example, a thin-film transistor LCD ("TFT-LCD"). LCD panel 12 is generally driven by column and row drivers. For example, columns may be driven by signal drivers 14 and rows driven by gate drivers 16. FIG. 2 illustrates that the column signal drivers 14 and the gate drivers 16 may be composed of a number of separate integrated circuits. Generally, signal drivers 14 receive digital video data from LCD control ASIC 8 via bus 9, control signals via bus 7 and analog supply voltages from supply voltage circuit 10 via bus 11. The present invention is not limited, though, to the specific LCD module shown in FIG. 2. For example, though shown with signal drivers located on only one side of the panel 12, signal drivers may drive the panel from both the top and bottom of the panel.

Signal drivers 14 provide an analog voltage output signal to each column. Furthermore, signal drivers 14 provide a varying analog output voltage such that a desired gray scale may be obtained for the pixels within LCD panel 12. Generally, a plurality of signal driver units are used to drive the columns of an LCD panel. For example, an LCD panel having 1,920 columns may be driven by five signal drivers 14 if each signal driver 14 is capable of driving 384 columns.

As shown in FIGS. 2 and 3, the digital data bus 9 may be 18 bits wide (six bits for each of the three sub-pixels). Typically the data bus width may be as wide as necessary to transmit a pixel of data and in such cases the data bus width may be designated as a single-wide bus. Thus as shown in FIGS 2 and 3, a single wide data bus is provided for a pixel having 18 bits of data. As will be discussed below, the data bus 9 may also be implemented in a double-wide (or more) mode of operation. In a double- wide mode of operation, the data bus may carry data for two pixels. Thus for an 18-bit pixel, the data bus 9 would be 36 bits wide for a double-wide mode of operation.

FIG. 3 shows an overview of an example driver circuit embodiment. Each channel of each signal driver 14 (also called a source, data or column driver) generates and outputs a highly accurate analog voltage to LCD 12. The output voltage level is based upon the corresponding sub-pixel data from the graphics controller 4. A channel refers to a signal driver output (or physical LCD pixel) and its associated circuitry. For LCDs with color filters, a channel corresponds to a sub-pixel — red, green or blue. For monochrome LCDs, a channel corresponds to a pixel.

The block diagram in FIG. 3 shows the internal architecture of signal driver 14, which comprises eight major sections: control logic unit 20, address shift register 21; data registers 22 including input registers 24 and storage registers 25; resistor string 26; level shifters 28; decoder/output voltage drivers 30; and output muxes.

The control logic unit 20 coordinates the signal drivers input and output functions, generates internal timing signals, and provides an automatic standby mode. During the standby mode, the majority of the internal circuitry of signal driver 14 is powered down to minimize power dissipation.

The address shift register 21 contains an N-bit shift register, where N is the number of uniquely addressable channels within signal driver 14. The direction of shift of shift register 21 is determined by the logical state of the DIR pin. The shift register 21 is clocked with the DCLK.

In a first embodiment of signal driver 14, there are 384 input registers 24, each comprising three sets of 128 latch circuits which latch 201 six-bit words of input display data. In a second embodiment, there are 192 input registers 24, each comprising three sets of 64 latch circuits which latch 192 six-bit words of display data. Each latch circuit contains three six-bit planes, where each plane corresponds to the significance of the input display data. (Note: D₁₅ is the most significant bit (MSB) and D₁₀ is the least significant bit (LSB)).

3 In first embodiment, storage registers 25 store 384 channels of six-bit display data for one line period (192 channels of six-bit data for the second embodiment), enabling the decoder 30 to use the display data from line time x while the next line of data (from line time x+1) is loaded into the input registers 24. The contents of the storage registers 25 are over- written with the next line of 384 (or 192) six-bit words of display data from the input registers 24 after a low- to-high transition occurs on HSYNC at the end of line time x+1.

An internal resistor string 26 used for voltage dividing, which may comprise a string of 64 resistors, produces 64 distinct voltage levels from 9 low voltage reference inputs (V₀-V₈). A second internal resistor string procures 64 distinct voltage levels from 9 high voltage reference inputs (V₉ - V₁₇H). Interpretated voltage levels are generated between each pair of adjacent reference voltage inputs, utilizing a string of 8 resistors between the reference voltages.

Decoder 30 selects the desired output voltage based upon the data in the storage register 25 for each of the 384 (or 192) channels. As the display data for line x+1 is loaded into the input registers 24, the decoder 30 uses the data for line x stored in the storage registers 25. The high voltage decoder selects the desired high voltage output voltage for the 192 high voltage channels and the low voltage decoder selects low voltage output voltages for the 192 low voltage channels.

Each of the decoders outputs one of the analog voltages (64 high voltage, 64 low voltage) based upon the corresponding decode of the display data. The first embodiment contains 384 decoders, the second embodiment has 192.

POL signal selects which channels are low voltage and which are high voltage. Adjacent channels are of opposite polarities. Output voltages are routed to the output channels by the output mux.

The analog voltage outputs are simultaneously applied from all channels of all signal drivers to the current row on the LCD 12 when a low-to-high transition occurs on HSYNC.

As seen in Figures 2 and 3, the graphics controller 4 outputs three channels of pixel data P_]7~P₀₀ (six-bits per channel for a total of eighteen-bits) in parallel along with the horizontal sync (HSYNC), vertical sync (VSYNC), pixel clock (PCLK) and data enable (Data Enable) signals to a Control ASIC 8 in the LCD module 6. The LCD control ASIC 8 re-formats the pixel data and outputs three channels of data in parallel to each signal driver 14.

The present invention supports a variety of LCD pixel resolutions, Simulscan^™ of CRT and LCD displays and various frame frequencies. Additionally, the invention may be used in a single bank or dual bank configuration to drive the LCD's channels (pixels).

The LCD control ASIC 8 outputs three six-bit words in parallel (eighteen-bits ~ each for the Red, Green and Blue sub-pixels) to each bank of signal drivers 14. If two banks of signal drivers 14 are used, the LCD control ASIC 8 divides the input data into separate data streams for each bank, such that the data rate is one-half the input pixel data rate. If a single bank of signal drivers 14 is used (as shown in FIG. 2), the data rate is equal to the input pixel data rate. The LCD control ASIC 8 generates the HSYNC and DCLK signals to the signal drivers 14.

Signal driver 14 receives the following signals as inputs: Enable In/Out (EI01 and EI02) signals; data shift direction control (DIR) signal; Data Clock (DCLK); Data (D₂₅~D₂₀, D₁₅~D₁₀, D₀₅~D₀₀); and Horizontal Sync (HSYNC) signal and POL (polarity).

The Enable Input/Output signals (EI01 and EI02) provide two functions. First EI01 and

EI02 "enables" the signal driver 14. The signal driver 14 is normally in a low power standby mode and is activated by the low-to-high transition of the EIOx (Enable In) input. The low-to- high transition on EIOx is detected after the rising edge of DCLK (and the standby mode is exited), the signal begins to latch the input data on the following rising edge of DCLK. Second, EI01 and EI02 allows the currently active signal driver 14 to enable the next signal driver 14 by pulsing the EIOx (Enable Out) output high, once 384 channels have been loaded.

When the DIR signal is tied to V_DDD (DIR=1), display data input is enabled by a high- going signal on the EI01 input. Three channels of data (eighteen-bits) are input into the driver 14 on the rising edge of every DCLK. After the display data for all channels are latched into the input registers 24, the signal driver 14 automatically enters a low-power standby mode.

n Each of the 384 (or 192) channels' output voltage is simultaneously output to the LCD 12 after the HSYNC rising edge. The voltage level decoded by the first data word (DO) of display data is output from pin V, (or V_S192), and the level decoded by the last word (D2) of display data is output on pin V₃₈₄

When the DIR signal is tied to GND (DIR = 0), display data input is enabled by a low- going signal on the EI02 input. After the display data for 384 (or 192) channels are latched into the input registers, the signal driver 14 automatically enters a low-power standby mode and the EI01 signal is pulsed high on the rising edge of the 128* (or 64^th) DCLK. The output voltage level selected by the first data word (D2) of display data is output from pin V₃₈₄. and the level selected by last word (DO) of display data is output in pin V, (or V_S192).

The signal driver 14 samples the data signals on the rising edge of the DCLK signal. DCLK must remain continuously running to provide timing control to the output muxes.

Each time the signal driver 14 is enabled (EIOx, Enable In, is pulsed high), three six-bit words Data (D25-D20, D15-D10, D05-D00) of display data for three channels are latched in parallel into the input registers 24 on the rising edge of DCLK. After 128 transitions of the DCLK, data for all 384 (or 192) channels (3 x 128 or 3 x 64) have been input. After the 128 (or 64^th) DCLK pulse, the signal driver 14 returns to the standby mode to minimize power consumption.

Each low-to-high transition on HSYNC causes the following. The contents of the 384 (or 192) input registers 24 are transferred to the storage registers 25, enabling the input registers 24 to be filled with the next line of display data during the next line time. The decoders 30 update the output voltage to the output mux. The POL signal is sampled to control the output muxes. The decoder output voltage is steered to the proper output by the output mux.

The Enable Out pin is pulsed high with the rising edge of the 128th (or 64th) DCLK. The Enable Out may be connected to an adjacent signal drive Enable In pin such that subsequent data may be loaded in the adjacent drivers 14. After the 128th (or 64th) DCLK pulse, the signal driver 14 returns to the standby mode to minimize power consumption. Each output voltage driver 30 generates a number of precise analog voltages (for example, 64). Each output voltage driver 30 begins to output one of a number of voltages to the LCD panel 12 simultaneously for all 384 (or 192) channels after the rising edge of HSYNC.

The decoder 30 selects the desired output voltage level based upon the data in the storage register 25 for each of the 384 (or 192) channels.

An internal resistive DAC 26, which may comprise two strings of 64 resistors, each produces interpolated voltage levels between any pair of adjacent reference voltages.

The supply voltage circuit 10 shown in FIG. 2 generate all the voltages required by the LCD panel 12. Signal driver 14 requires the following power supplies and reference voltages: one digital supply voltage (V_DDD); one analog supply voltage (V_DDA); eight reference voltages

(VL₈ - V₂₀; V_H8-V_H0).

Signal driver circuit 14 shown in FIG. 3 provides up to two sets of sixty for voltage levels on each of 384 LCD columns. It will be recognized, though, that more or less voltages or columns may be utilized. Within signal driver 14, decoder/output drivers 30 are used to provide a specific voltage output to each column. The interaction between decoder/output voltage drivers 30 and resistive string 26 may be seen more clearly in FIG. 3A. FIG. 3A functionally illustrates a decoder circuit for one column and full digital decoder architecture that may be utilized by the decoder. For illustrative purposes, FIG. 3A presents only eight voltage levels. Thus, three data bits are needed to select the eight voltage levels. It is recognized that any number of voltage levels may be selected, for example, signal driver 14 may utilize sixty-four voltage levels which would require six data bits to select the desired levels. In general, 2^N voltage levels may be used, where N is the number of data bits.

In FIG. 3 A, digital data bit lines 40 and their compliments are supplied to a series of NAND gates 41. Each NAND gate 41 is connected to select one of the eight possible digital states. Connected to NAND gates 41 are analog switches 42. Analog switches 42 are also connected to resistive string 43. One analog switch 42 is provided for each desired voltage output, for example, as shown in FIG. 3 A, eight switches 42 are for eight possible voltage outputs. Thus, the circuit shown in FIG. 3 A uses full digital decoding logic to convert digital

»2> data on data bit lines 40 to an analog voltage output 44. Though not shown in FIG. 3A, switches 42 may utilize both the output of NAND gates 41 and the inverted output of NAND gates 41.

FIG. 3B is the full digital decoder logic used to select one of the sixty- four analog output voltages V_in0V_in63. Sixty-four NAND gates 41 are connected to six-bit lines 40, each NAND gate 41 being connected to select one of the sixty- four possible digital states. The inverted output of each NAND gate 41 is also provided to switch 42 as shown in FIG. 3B. As shown in FIG. 3B, inverter 45 and NAND gates 41 may be together considered decoder cell 46. Thus, for sixty- four possible analog outputs, sixty-four decoder cells (cells 0-63), sixty-four analog switches and sixty- four analog voltages are used. It will be recognized, though, that as used herein a decoder cell may also include switch 42. In general, a cell is simply a repeated structure used to decode a specific decode state to provide a voltage to an output of the signal driver.

POL signal is used to select which decoder output is routed to the appropriate output.

As with reference to FIGS. 3 A and 3B and as discussed above, resistor strings or resistor voltage dividers may be used for supplying the voltage levels that may be switched to a column output. In one embodiment of the present invention, sixty- four different voltage levels are utilized by placing in series eight resistors between each of nine voltage reference voltages supplied to the signal driver chip bonding pads. This arrangement serves to provide a plurality of analog voltages to generate a digital code-output voltage curve that is tailored to match the non-linear characteristics of a particular LCD panel's transmissivity- voltage response. Thus, the approach of this resistor string digital to analog converter (DAC) architecture requires at least 64 individual resistors of moderate electrical value (of approximately 40 ohms each in one embodiment). One set of sixty- four voltage levels has been discussed above. However, because a full range utilizes both negative and positive polarities, a second resister string is used to form a second set of sixty-four reference voltages. Thus, sixty- four high polarity reference voltages and sixty-four low polarity voltage references are provided.

Current Sharing

In order to reduce power consumption, current sharing may be utilized both at a system level and at within a signal driver circuit. At a system level, current sharing may occur in the supply voltage circuit (also called the reference voltage generator). For example, the reference voltage generator may contain a plurality of sets of buffer amplifiers, each set operating at a different voltage range. In one embodiment, a set of buffer amplifiers operating at a low voltage range and a set of buffer amplifiers operating at a high voltage range may be provided. In order to reduce power consumption, the quiescent current through one set of amplifiers may also be utilized to operate another set of amplifiers.

Likewise current may be shared within the column signal driver itself. As will be discussed below, multiple resistor strings may be utilized with the signal driver circuit. A high voltage range resistor string and a low voltage range resistor string may be configured so that current may be shared between the strings rather than be directed to ground.

System level current sharing may be seen with reference to FIGS. 4 and 5. FIG. 4 is a system level schematic similar to that of FIG. 2 except containing more details with regards to the supply voltage circuit (or reference voltage generator) 10 and the reference voltages. As shown in FIG. 4, two sets of reference voltages may be generated from the reference voltage generator 10. The reference voltage generator 10 has supply voltage inputs including Vddh (Vdd high voltage) input 406, Vssl (Vss low voltage) input 408, and Midi input 410. Typically, Vddh may be a high supply voltage at 12, 10, or 8 volts and Vssl may be ground while the Midi supply voltage falls between the Vddh and Vssl voltage levels (for example halfway between Vddh and Vssl). The Midi supply voltage level may be the Vssh (Vss high voltage) and Vddl (Vdd low voltage) levels. Alternatively, if Vssh and Vddl are not at the same voltage level, a Midi supply voltage and a Mid2 supply voltage may be provided to the voltage generator, wherein Vssh is the Midi voltage level and Vddl is the Mid2 voltage level. A Vcom output 412 may provide the dc potential for the common back plane of the panel 12.

The output of the voltage generator 10 may include multiple sets of reference voltages on reference voltage bus lines 402 and 404. Multiple sets of reference voltages may be advantageous in a full range column driver architecture as described in more detail below. In one example, the reference voltage bus 402 provides 9 voltages between Vddh and Vssh (for example 10 to 5 volts) and the reference voltages bus 404 provides 9 voltages between Vddl and Vssl (for example between 5 to 0 volts). A polarity signal 420 may be provided from the control ASIC 8 to each signal driver circuit 14. The polarity signal sets whether the even column outputs are driven to the high voltage range and the odd columns to the negative voltage range or vice-versa (as discussed below in more detail).

FIG. 5 illustrates the reference voltage generator 10 in more detail. The reference voltage generator 10 may include the resistor voltage divider having a series of resistors 500 between the Vddh supply voltage and the Vssl supply voltage. The first 9 taps from the resistor voltage divider are provided to 9 buffer amplifiers 502 which provide as outputs the voltage levels for the reference voltage bus 402. The last 9 taps of the voltage divider are provided to the buffer amplifiers 504 which provide the voltage levels for the reference voltage bus 404. The buffer amplifiers 502 which provide the reference voltages in the Vddh to Vssh range each operate from supply voltages Vddh and Vssh as shown. The buffer amplifiers 504 which provide the output voltages in the Vddl to Vssl range likewise operate from supply voltages Vddl and Vssl as shown. The buffer amplifier coupled to the Vcom output may be tied to either set of supply voltages depending upon which voltage range the Vcom dc voltage falls between.

The quiescent current through each amplifier 502 is represented as Iddh and the total quiescent current for the buffer amplifiers 502 would be approximately nine times that value (for the example of nine buffer amplifiers). The total quiescent current (Idq) through the high voltage buffer amplifiers may be also utilized for the quiescent current through the low voltage amplifiers. Thus, the total current used through both the high voltage and low voltage buffer amplifiers may be reduced. In one case, where the Vssh and the Vddl levels are the same voltage (which may be obtained by being connected to the same supply node either on chip or off chip) then the quiescent current that is flowing out of the negative supply of the high voltage references is shunted to each of the positive supply terminals for the low voltage amplifiers. The benefits of the current sharing may also be obtained even if Vssh and Vddl are not the same voltage level. For instance, if the Vssh level is set at some value above Vddl, then a shunt resister may be placed between the Vssh and the Vddl nodes through which the quiescent current may be shunted. The resister placed between the nodes would then be appropriately sized such that the proper voltage drop from one node to the next node would occur given the total current Idq which is generated. Thus though two blocks of buffer amplifiers (a low voltage block and a high voltage block) may be utilized, the quiescent current through those blocks may be nearly the total quiescent current of just one of the blocks of buffer amplifiers. The current sharing may also be accomplished on the load side of the buffer amplifiers. The loads connected to the voltage bus 402 and voltage bus 404 may also be configured such that current may be shared between a high voltage load and a low voltage load so as to reduce the sum total current supplied from the reference voltage generator 10. As shown in FIG. 5B a load 520 is connected to each of the voltage buses 402 and 404. The specific load illustrated in FIG. 5Bis a resistor voltage divider column driver architecture. In such an application, a string of resistors is provided between the reference voltages supplied from the reference voltage generator 10 to generate a complete set of voltages which may be utilized within the LCD signal driver circuit. As shown in FIG. 5B between each of the reference voltages of the voltage bus lines 402 (V8h, V7h, ... VOh, which are the 9 voltages supplied from the high voltage amplifiers) there is provided a series of resistors such that a total of 64 load voltages (VL64h, VL63h....VL0h) are generated. Likewise, 64 load voltages for the low voltage circuitry (VL641, VL631... VL01) are also provided.

Thus, a high voltage resistor string 522 and a low voltage resistor string 524 are provided. As with the quiescent current of the buffer amplifiers, by sharing the current which is flowing through the high voltage resistor string 522 and the low voltage resistor string 524, the total current being sourced may be reduced. In particular, if the voltage level VLOh and VL641 are the same, then the same current flowing through node VLOh may be reused as the source current for the top of the low voltage resistor divider. Alternatively, if those voltages are not the same, then a shunt resistor may be applied between the high voltage string and the low voltage string to achieve the current sharing.

The sharing of current utilized through the high voltage resistor and the low voltage resistor string may be particularly advantageous if the net current flowing through the resistor string is primarily composed of current flowing from the uppermost buffer amplifier and current flowing into the lowermost buffer amplifier as indicated by currents 18 and 10 of FIG. 5B In particular, this may be obtained by utilizing a weighted resistor voltage divider as shown in FIG. 5C In FIG. 5C the buffer amplifiers 502 are shown connected to the load resistor string 522. For simplicity, the resistor values shown between each buffer amplifier are a sum of all the resistors between the outputs of each buffer amplifier. By weighting the resistor values, the output current of the center buffer amplifiers, V₃, V₄, and V₅, may be 0 while a current of 5 mA flows into the resistor string at the uppermost buffer amplifier and a current of 5 mA flows out π of the resistor string at the lowermost buffer amplifier. If such a configuration was utilized for both the high voltage and low voltage resistor strings, then the 5 mA current through the lowermost buffer amplifier 502 may be utilized either directly or through a shunt resistor as the source for the current at the uppermost end of the low voltage resistor string. It will be recognized that the values for the various current levels and resistors shown herein are utilized for illustrative purposes and the invention is not limited to a specific values but rather other values may also be utilized

Pin Selectable Single Width/Double Width Mode

As mentioned above with reference to FIGS. 2 and 3, the digital data bus may be as wide as a single pixel of data (for example three sub-pixels) or alternatively may be wide enough to carry multiple pixels of information at a time. Thus, for the case of an 18 bit pixel (3 sub-pixels of 6 bits each) a single width data bus would include 18 bits, a double width data bus would include 36 bits, etc.

Though the width of the data bus may be hardwired within the signal driver integrated circuit to a specific single, double, triple, etc. width, it is desirable that the signal driver chip data bus width be selectable by a user. For example, a double width data bus may be provided having 36 data inputs to the signal driver integrated circuit. An input pin of the signal driver circuit may then be utilized so that the user may select as to whether 36 bits of data will be presented to the circuit at a given clock cycle or whether only 18 data bits will be presented to the signal driver circuit. As used herein, the pin selectability may be obtained at the integrated circuit pad level or at the level of the package input/output pins level of the package that the integrated circuit is bonded to. For example, one integrated circuit design may be utilized independent of a user's desire for a single or double width bus, and the selection of the desired bus width may be accomplished by wire bonding the appropriate bond pads of the integrated circuit to the chip package. In this case one of the integrated circuit level pin sites (i.e., die bonding pads) may be tied high or low to indicate the appropriate data bus width.

The implementation of a user selectable data bus width may best be understood by first considering the operation of a single pixel wide data bus circuit. FIG. 6 illustrates one conventional embodiment for implementing a single width data bus. In FIG. 6, the 18 bit wide

IS data bus 9 is comprised of six bits each of red, green, and blue data for the red, green, and blue sub-pixels respectively. As discussed with relation to FIG. 3, a series of input registers 24 may receive the data from the data bus. The data is then provided to storage registers 25 and decoders 30 for ultimately providing a red, green, and blue analog output voltage for each pixel. As shown in FIG. 6, outputs for two channels of pixels, pixel 1 and pixel 2, are illustrated. In a single width data bus, for each clock cycle data is provided for one pixel. For a next clock cycle data may be provided for the next pixel and so on until data for each pixel is provided.

Depending upon a users specific implementation of a LCD panel, pixels may be loaded from left to right or right to left, thus it is desirable that the input registers 24 may be controlled in a bi-directional manner such that the appropriate input registers read data from the data bus 9 in the appropriate sequence. An addressing circuit 610 which provides such bi-directional sequencing is shown in FIG. 6 and FIG. 6A. The addressing circuit 610 provides a read signal 605 for the sets of input registers for each pixel. In the embodiment shown in FIGS. 6 and 6A, a shift register is provided in which a read bit (or token) such as a digital 1 may be sequenced or walked through the shift register so that the read signal 605 may be sequentially enabled in the desired left to right or right to left sequence. The specific implementation shown for the address circuitry 610 includes a shift register comprised of a series of D flip flops 615 and multiplexers 620. As shown, each adjacent multiplexer receives as an input the output of an adjacent D flip flop 615. A direction signal 625 is provided to each multiplexer so that a left to right "walking" enable signal may be provided or alternatively a right to left "walking" enable signal may be provided.

A circuit similar to that shown in FIG. 6 and 6A may be utilized in order to implement a dedicated double-wide bus embodiment. In such an embodiment, the data bus 9 may carry data for two pixels, typically adjacent pixels though not necessarily. Typically the data may be arranged such that of the 36 bit lines, one set of 18 bit lines would carry data for odd numbered pixels and the other 18 bit lines would carry data for even numbered pixels. Thus, the input registers for even numbered pixels would be connected to the even bit lines and the input registers for odd numbered pixels would be connected to the odd bit lines. The addressing circuitry 610 would in such a case be modified to allow a sequential reading of two pixels at a time, for example such as the reading of pixels 3 and 4 on one clock cycle and then on the next clock cycle the reading the of pixels 5 and 6. In order to implement the addressing circuitry 610 for a double width bus, a circuit similar to that as shown in 6A may be utilized except rather than having the output of each D flip flop 615 connected to the multiplexer 620 of the adjacent channel, the output of each D flip flop would be connected to the multiplexer of the channels that are two channels apart. For example, as shown in FIG. 6A, the read signal 605 for the third pixel, READ 3, would be connected to the input to the multiplexer associated with pixel 5 and the input of the multiplexer associated with pixel 1. Likewise, the output of the flip flop associated with pixel 4 would be connected to the input of the multiplexer associated with pixel 6 and the input of the multiplexer associated with pixel 2. In this manner, an address circuitry similar to that shown in 610 may be composed of a shift register in which an even channel and an odd channel may be enabled for each clock cycle and the next even channel and next odd channel would be enabled for the next clock cycle.

FIGS. 7 and 7 A illustrate circuitry for implementing a user selectable data bus width. As shown in FIG. 7, the data bus 9 may include 36 bit lines, including bits for even channels for the red, green, and blue data (RE, GE and BE) and bits for the red, green, and blue data for the odd channels (RO, GO and BO). The input registers for even pixels are connected to the RE, GE and DE bit lines while the input registers for the odd pixels are connected to the RO, GO and BO lines as indicated in FIG. 7. Each pixel has a corresponding enable signal line 605 provided to the input registers. The enable signals 605 may be generated from an address circuitry such as shown in FIG. 7A. Though not shown, the 36 data bus lines 9 may be provided to input pins of the LCD signal driver integrated circuit for receiving the digital data. An additional pin may also be provided at which the user selects the width of the data bus. If a user selects a single width mode, the bus lines RE and RO, GE and GO, and BE and BO may be tied together so that data presented on each set of the red, green, and blue bus lines is the same.

FIG. 7A illustrates an example address circuitry for use in generating the enabled signal 605 to be provided to enable a sequential selection of data from the data bus 9 in either a single width or double width mode. In particular, a shift register type operation is provided through a series of D flip flops 615 and multiplexers 720. The multiplexers 720 each receive an input signal 625 to indicate as to whether the shifting operation is to be performed in a left to right or right to left manner. In order to allow the selection of either a single width or double width bus mode, a dual/single mode signal 725 is also provided to each multiplexer. The dual/single signal 725 may be generated from the integrated circuit pin which designates which mode the user has

TV selected. In the single mode, the multiplexer will provide as an output the signal which is at the output of the D flip flop for the immediately adjacent pixel. In the double width mode, the multiplexer will pass the signal which is generated at the output of the D flip flop which is two channels away from the multiplexer. For example with reference to FIG. 7A, the multiplexer 720-4 may receive as an input the outputs of the D flip flops associated with pixel 2, pixel 3, pixel 5, or pixel 6. If the mode of operation is a left to right shifting of data and the single width mode is selected, then the output of the multiplexer 720-4 is the output of the D flip flop associated with pixel 3. Likewise, if the left to right shifting mode and the double width mode is selected, then the output of the multiplexer 720-4 will be the output provided at the D flip flop associated with pixel 2. Similarly, in the right to left mode of operation, the output of the multiplexer 720-4 may be either the output of the D flip flop associated with pixel 5 in a single width mode or the output of the D flip flop associated with pixel 6 in the double width mode. Thus, the addressing circuitry 710 shown in FIG. 7 A may respond to a user selection of either dual or single width mode to provide the appropriate enable signals on signal lines 605 so as to sequentially enable either a single pixel of data or enable sequential pairs of pixels of data.

In the double- width mode, the addressing circuitry 710 shown in FIG. 7 A operates by passing two tokens simultaneously to the appropriate enable signals on signal lines 605, enabling two pixels at a time. For example, if the left to right shifting mode is enabled, one token sequentially enables pixel 1, pixel 3, pixel 5, and so on, while the second token sequentially enables pixel 2, pixel 4, pixel 6, and so on. By initially enabling pixel 1 and pixel 2, the two tokens sequentially enable adjacent pairs of pixels. Recognizing that the two tokens are redundant in the double-width mode, the addressing circuitry may be simplified. As shown in FIG. 7B, one simplified addressing circuitry is provided. In the circuit of FIG. 7B, it is recognized that in double- width mode the output of two adjacent flip flops is the same. Thus, only one of those two outputs need be utilized. For example, in double width mode (left to right shifting mode) the input to mux 720-3 from single lines 605 for pixels 1 and 2 may be provided to mux by only using the output from pixel 2 since the pixel 1 and pixel 2 from outputs are identical.

Though the illustrations with respect to FIG. 7, 7A, and 7B have been shown herein with regard to a double width data bus, it will be recognized that the data bus may be even wider than two pixels of data. Likewise, though the examples shown herein have been utilized in which the

1Λ data bus carries data for adjacent pixels of data at any one given clock cycle, it will be recognized that the data on the data bus may be some other arrangement so that the pairs of data on the clock at one time need not be adjacent pixels, but rather maybe some other defined scheme.

Thus, an LCD signal driver bus architecture is provided in which the bus need not be hardwired to any specific width but rather may be user programmable such that one, two, or more pixels of data may be simultaneously provided across the data bus.

Decoder Channel Multiplexing

As discussed in the background section above, full range drivers may be utilized in LCD panel architectures in which the LCD common backplane is held at a fixed DC potential located at or near the center of the entire voltage range. Full range drivers may be utilized even in situations where a high voltage range, typically 8 to 12 volts is desired. In order to implement a high voltage range full range driver with typical integrated circuit CMOS processing techniques (such as standard 5 to 6 volt CMOS processing techniques), the LCD signal driver circuit may operate with sections of the circuitry operating in the lower portion of the full range of voltages (for example 0 to 6 volts) and another section of the circuitry operating in the upper ranges of the full range of voltages (for example 6 to 12 volts). In this manner, the LCD signal driver output may range from 0 to 12 volts, however, any given portion of the circuitry may operate within the typical CMOS processing breakdown limits.

One typical approach for splitting the circuitry between the lower ranges and upper ranges of voltages is to provide a set of high voltage decoders and a set of low voltage decoders. In such techniques, each column (or subpixel) is provided with a high voltage decoder and a low voltage decoder. If the output of a specific column is to be in the high voltage range, then the digital data representing the desired output is provided to the high voltage decoders so that an analog voltage in the upper portion of the voltage range may be provided to the output channel. Likewise, if the digital data represents a voltage in the lower voltage range, then the low voltage decoders are utilized to provide a signal to the output channel in that lower voltage range. In this manner, standard CMOS process techniques may be utilized even though the voltage which may be presented at any given output column may have a wide voltage range, for example 0 to 8 volts or 0 to 12 volts. However, to implement this technique requires two sets of decoders, a high voltage decoder circuitry and a low voltage decoder circuitry, for each output channel. Thus, the use of the standard CMOS fabrication techniques comes at the expense of added circuit area (i.e., the doubling of the decoder circuits).

FIG. 8 provides a driver architecture for use with a full range LCD signal driver which may be implemented with standard CMOS processing techniques and still not require the doubling of the decoder circuits as described above. The architecture shown in FIG. 8 is of particular use with LCD panels which are operated in column inversion or dot inversion modes. In both column inversion and dot inversion modes, it is recognized that any two adjacent columns will not be driven to high voltages at the same time. Thus, one high voltage decoder and one low voltage decoder need only be provided for two adjacent columns and the decoders may be multiplexed back and forth between whichever column would require either the high voltage or low voltage signals at a given time.

FIG. 8 shows such an architecture in which the high voltage and low voltage decoders may be multiplexed between two adjacent columns. As shown in FIG. 8, a data bus 801 provides the digital data for the red, green, and blue subpixels. For illustrative purposes, the data bus 801 is shown as a single width data bus, however, it will be recognized that as discussed above, the data bus may be wider. A series of signal outputs, S0-S7 are shown in FIG. 8. Each signal output provides the analog data for one column. As shown in FIG. 8, three adjacent columns may be utilized to provide the red, green, and blue subpixel data for one pixel such as pixels 802, 804, and 806. As shown, signal outputs SO, SI, and S2 provide the red, green, and blue subpixels respectively of pixel 802 and signal lines S3, S4, and S5 provide the three subpixels for pixel 804 and so on.

A plurality of high voltage decoders 810 and low voltage decoders 812 are also provided. One high voltage decoder 810 is provided for every two column outputs and likewise one low voltage decoder 812 is provided for every two column outputs. Because in dot inversion and column inversion LCD panel modes, any two adjacent columns will not both be operating in high voltage modes or in low voltage modes, one high voltage decoder and one low voltage decoder may be multiplexed back and forth as needed between two adjacent columns. A polarity signal 816 may be provided to indicate which columns are operating in the high voltage mode and which columns are operating in a low voltage mode at any given time. For example, a high signal on polarity signal 816 may indicate that the even outputs (SO, S2, S4...) are operating in a high voltage mode and the odd signal outputs are operating in a low voltage mode or vice versa.

The digital data is provided from the data bus 801 to a series of multiplexers 820. Depending upon the polarity signal 816, the multiplexers 820 provide the digital red, green, or blue data to the appropriate D latches which then latch the data to the appropriate high voltage or low voltage decoder circuit as desired. A token signal 830 may be provided to the D latches 822. The token signal 830 may be a walking one signal which successively indicates which pixel of data is currently on the digital data bus 801. For example, circuitry such as discussed above with reference to FIGS. 6-7 A to indicate which pixel(s) will pull data from the data bus. Because the digital data generally will be operating at normal voltage ranges, level shifters 824 may be utilized to shift the voltage level from a standard operating voltage level (such as 0 to 5 volts or 0 to 3.3 volts) to the higher voltages of the high voltage decoders.

The decoders 810 and 812 convert the digital data to analog voltage signals utilizing the voltage reference signals 832 which may be provided from a resistor string voltage divider. The outputs of the decoders are then provided to a series of multiplexers 836. The multiplexers 836 also receive the polarity signal 816. The multiplexers 836 may be utilized to provide the red, green, or blue analog signals from the decoders to the appropriate SO, SI, and S2 output which would correspond to the red, green, or blue subpixel output respectively.

An alternative LCD signal driver architecture that is similar to that shown in FIG. 8 is illustrated in FIG. 8 A. The circuitry of FIG. 8 A is identical to that FIG. 8 except for the addition of pre-charge circuitry 850. The advantages and implementation of pre-charge circuitry 850 is discussed in more detail below. Yet another embodiment of the LCD signal driver architecture utilizing the sharing of decoders between output columns is illustrated in FIG. 8B. The circuitry of FIG. 8B is identical to that shown in FIG. 8 A except the level shifters 824 are not utilized. In one embodiment, the circuitry of FIG. 8B may utilize high voltage decoders 810 which contain inherent level shifting within the decoder cells. Such decoder cells having level shifting characteristics are disclosed in more detail below. Many types and designs of multiplexers may be utilized for the multiplexers shown in FIGS. 8, 8A, and 8B. For example, one design for use as multiplexers 836 is shown in FIG. 9. In FIG. 9, the multiplexers receive an input from the high voltage decoders 810 (input dechv and an input from the low voltage decoders 812 (input declv). The multiplexers also receive supply voltage inputs Vddh (Vdd high voltage) 900 and Vddl 902 (Vdd low voltage). Also provided to the multiplexer is a series of selection signals (selhv, selhvb, sel, selb, selv, selvb, selfv, and selfvb). The logic levels for the Sel and Selb signals operate at the standard digital voltage level such as 5 volts or 3.3 volts (0 to Vddd). The Sellv and Selfvb signals operate from 0 to VDDL. The Selhv and Selhvb signals operate from Vsshto Vddh. The Selfv and SelfVb signals operate from 0 to Vddh. The multiplexer itself includes complimentary transistor switch pairs as shown which enable a rail to rail voltage range. The outputs of the multiplexer 836 are provided to the pre-charge circuitry 850 (shown by the dashed lines in FIG. 9). As shown in FIG. 9, the multiplexer 836 includes an odd column output 904 and an even column output 906 which are provided to the pre-charge circuitry 850. The operation of the pre-charge circuitry is discussed in more detail below.

Thus, the principles of sharing high voltage and low voltage decoder cells between column outputs may be utilized with a variety of architectures. It will be recognized that the concept of multiplexing and sharing decoders between multiple output columns may be utilized in a wide variety of manners. For example, the sharing of decoders is not limited to the specific architectures disclosed herein. A wide variety of multiplexing, latching, level shifting, and/or pre-charging circuits may or may not be utilized, while the advantages of the present invention may be still obtained. Further, many of the variety of data bus width selection techniques, level shifting techniques, decoder cells and associated techniques, and other embodiments disclosed herein may be utilized with the decoder sharing embodiments disclosed or alternatively the decoder sharing embodiments may be utilized independent of any of these other embodiments.

Z.^ Precharging

When using a dot inversion mode or column inversion mode LCD panel, at any given time approximately one-half of the outputs will be driven to a high polarity while the other half of the outputs will be driven to the low polarity. Furthermore, each output will repeatedly switch back and forth from the high polarity to the low polarity. When the outputs need to switch polarity, rather than dumping all of the charge on any one given output to ground, charge from the high polarity outputs may be dumped to the low polarity outputs so that significant power savings may be obtained. Thus, a precharging step may be added to the sequence of switching one column from high to low or low to high polarities. For example, if an even column is at a high polarity state and its adjacent odd column is at a low polarity state, then the switching sequence may include a precharging step in which charge from the high polarity even column is moved to the add column such that each column would now be at a voltage level somewhere between the high polarity voltage and the low polarity voltage (such as approximately Vcom). Then, the switching of the column voltages may proceed such that the odd column may be brought up to the high polarity state and the even column brought down to the low polarity state. In this manner on average across all the columns an approximately fifty percent power savings may be achieved.

Graphically, the behavior of one column output is illustrated in FIG. 10. FIG. 10 shows an example column output voltage versus time. As shown in the figure, rather than having the column output voltage merely switch from a high voltage level to a low voltage level an intermediate period is provided in which the column output voltage level is brought to the precharge level. Thus, as shown in the figure the column is brought to a precharge level in time intervals T1-T2, T3-T4, and T5-T6. In time intervals T1-T2 charge is being removed from the column as the column was previously at the high voltage state and this charge would be provided to some other column which is at the low voltage state during time T0-T1. As shown in FIG. 10, when the column output voltage level is at a low polarity state and is to be switched to the high polarity state, the column output voltage is also brought to the precharge level such as shown in time intervals T3 and T4. During the transitions from the low to the high polarity state the charge utilized to bring the column output to the precharge level may come from other columns which are at the high polarity state. Thus, in this manner the column outputs may be switched back and forth from high polarity to low polarity utilizing an intermediate precharging step in which charge is shared between columns to ultimately conserve power.

As shown in FIGS. 8 A, 8B, and 9 a shared precharge circuitry between two adjacent columns may be utilized. In this manner the charge may be simply swapped back and forth between two adjacent columns in order to achieve the desired power conservation. However, it will be recognized that the precharge concepts disclosed herein need not be utilized solely between adjacent columns. Rather, for example, a common bus may be provided in which charge from all the high polarity columns is dumped onto and from where the charge for low polarity columns is obtained from. Alternatively some other scheme (in addition to the adjacent column scheme) for matching high polarity columns with low polarity columns may also be utilized. Furthermore, the precharging of the column outputs need not be limited solely to on chip charge sharing between columns but rather the charge sharing between column outputs may also be accomplished off the signal driver circuit chip.

One example of the precharging circuitry utilized to achieve charge conservation between two adjacent column outputs is shown in FIG. 9. In particular precharging circuitry 850 receives the decoder voltage outputs (after muxing) at signal lines 904 and 906 for providing an output to the column outputs 924 and 922 respectively. The precharging circuitry 850 also receives as an input the voltage refpc which may be at the digital logic voltage level such as 5 volts. The precharge circuitry 850 also includes transistors 930 and 932 which are controlled by gate voltage prechgfvl and gate voltage prechgfv2 respectively. As shown in FIG. 9, the transistors 930 and 932 are connected such that when properly switched by their control gates, charge may be transferred from one column output to the adjacent column output. In order to achieve the desired function of the transistor switches 930 and 932 the gate control signals prechgfvl and prechgfV2 have three control voltage levels, Vddh, Vssh, and Vssl (0 volts). For example, as shown in FIG. 10A the gate voltage for transistor 930 is illustrated if one is to achieve at the column output 920 the column output voltages as shown in FIG. 10. Thus as shown in FIG. 10A, during periods in which the column output voltage is to be precharged (for example T1-T2, T3-T4, and T5-T6) the gate voltage for the associated switch is brought high to

Vddh. Furthermore, during periods in which the column is being driven low, (T2-T3 and T6-

T7) the gate voltage is also brought low to Vssl. Finally, during periods in which the column output voltage is at a high polarity (T0-T1 and T4-T5) the gate voltage is brought to a mid- 2.7 voltage level such as Vssh. Using control signals operating in this manner, the two transistor switches within the precharge circuitry 850 may be sequentially switched such that charge may be shared from the column output having a high voltage level with the column output having a low voltage level to achieve a precharging of the column output which is switching from low to high such that power may be conserved.

FIG. 10B illustrates an example of circuitry for generating the gate control signals prechgfvl and prechgfV2. Though shown with respect only to prechgfvl, a circuit such as shown in FIG. 10B may be symmetrically utilized to also generate the signal prechgfV2. As shown in FIG. 10B, three input signals precharge, drive 1, and drive 2 are provided. Each of the input signals may generally be at standard digital logic voltage levels and thus a series of level shifters 1000 may be utilized to convert the input signals to the appropriate desired voltage levels. A high precharged signal indicates that the columns should be in a precharging mode, a high drive 1 signal indicates that column 1 (such as the output column 920 of FIG. 9) should be driven high and a high drive 2 signal indicates that the column 2 (the output column 922 of FIG. 9) should be driven high. As utilized in FIG. 10B, high voltage, low voltage, and inverted versions of the input signals to the level shifters may be indicated with the additions of "hv", "lv", and "b" on the appropriate output signal label name. Thus, as shown in FIG. 10B the precharge signal is shifted by the level shifter to be a high voltage version of the precharge signal and indicated as "prechargehv". Likewise, high voltage, low voltage inverted, and low voltage versions of the drive 1 signal are provided as drivelhv, drivellvb, and drivellv. Similarly designated signals for the drive 2 signal are indicated. Thus, the circuitry of FIG. 10B may provide an output prechgfvl which may switch between Vssl, Vssh, and Vddh as indicated in FIGS. 10 and 10A during the appropriate times that the associated column is driven high, being precharged or driven low. A symmetrical circuit to that shown in FIG. 10B may be utilized to generate the prechgfV2 signal by utilizing the drivellv, drive2hv, and drive21vb signals provided from the level shifting outputs. In this manner, the precharging circuitry 850 as shown in FIG. 9 may be controlled in accordance with the descriptions of FIG. 10, 10 A, and 10B to provide precharging of the LCD signal driver column outputs.

It will be recognized that the concept of precharging the column outputs may be implemented in a wide variety of manners and that the invention herein need not be limited to

1$ the specific circuitry utilized for implementing the precharging but rather a wide variety of circuit techniques may accomplish the precharging function.

The precharging of the output columns provides advantages in addition to the precharging power conservation. In particular, by providing an intermediate voltage level when the columns are switching from high to low and low to high, voltage transient characteristics in the multiplexing circuitry 836 may be improved.

Level Shifting Circuitry Because the output voltages needed to be driven to an LCD panel are generally higher than the digital logic utilized in an LCD signal driver, level shifting circuitry is commonly employed in LCD signal drivers. For example, typical digital logic voltages of 2.8, 3.3, or 5 volts may be employed in signal drivers which have 0-8 volts or 0-12 volt outputs. For example, the use of level shifting circuitry is shown above with reference to FIGS. 3, 8, 8 A, and 10B. Further, FIG. 11 illustrates the use of level shifters for an LCD signal driver circuit. FIG. 11 illustrates decoder channel multiplexing similar to that discussed above with references to FIGS. 8, 8A, and 8B. The specific level shifting circuitry disclosed herein however, may be utilized in many different LCD signal driver architectures and is not limited to those shown.

As shown in FIG. 11, the LCD signal driver circuit may include inputs which include the data input bus 1105 and a variety of control inputs 1110 which may be any of the various control inputs such as the clocks, sync signals, enable signals, polarity signals, etc. The control inputs 1110 are provided to the control logic 1115. The control logic typically operates at a standard digital logic level such as 3.3 volts. At least some of the control logic outputs may require level shifting, particularly if they are to control high voltage signals. Thus, level shifting circuitry 120 may be utilized for shifting some of the control signals of the LCD signal driver circuit.

In the improved level shifting circuits disclosed herein, the level shifting circuit may provide multiple output ranges. Typical level shifting circuits may operate to merely shift an voltage such as for example a 0 - 5 volt voltage to a 5 - 10 or l0 - 15 volt voltage range.

However, as disclosed herein, improved level shifting circuits may provide multiple voltage ranges some of which may be expanded voltage ranges. For example, as shown in FIG. 11 the level shift circuit 1120 may include outputs having voltage ranges of 0 - 4 volts, 4 - 8 volts, and a full range of 0 - 8 volts. These voltage ranges are shown as illustrative embodiments, and other ranges such as 10 volt maximum or 12 volt maximum voltage ranges may also be commonly implemented. Because the data on the data bus 1105 generally is also presented at standard digital logic voltage levels, level shifting may also be employed in the data decoding path between the data input bus and the LCD signal driver output channels. As shown in FIG. 11, two output channels which utilize multiplexing between the high voltage and low voltage decoders is provided. Similar to that discussed above with references to FIGS. 8, 8 A, and 8B, FIG. 11 includes input registers 1125 which are multiplexed to storage registers 1130. A low voltage decoder 1135 is provided and a high voltage decoder 1140 is provided. The outputs of the decoders may then be muxed to the appropriate output channel. In the high voltage path, level shifting circuitry may be provided to shift the data voltage level as needed. As shown in FIG. 11 this may be accomplished by inserting a level shifter 1121 between the storage register and the high voltage decoder 1140. Alternatively, rather than using separate storage registers and level shifters, a combination storage register and level shifter may be provided such as shown by the dashed line 1122. Such a combination may be provided through the use of a level shifting circuit which also provides a latching function. By providing both a latching function and level shifting function a single circuit 1122 may be employed in place of the storage register 1130 and the level shifting circuit 1121. In yet another embodiment, the level shifting block prior to the high voltage decoding block 1140 may be eliminated by utilizing decoder cells which also provide inherent level shifting features. Thus, any level shifting necessary for the high voltage outputs may be performed inherently within the decoder cell.

A typical prior art level shifter is shown in FIG. 12. The level shifter of FIG. 12 is a high voltage level shifter. For example, Vddh may be 8, 10, 12, or some other high voltage while the input 1201 may be the standard digital logic level. Four P channel transistors, PI, P2, P3, and P4 and four N channel transistors Nl, N2, N3, and N4 are provided. Output 1202 and inverted output 1203 are also provided. It is desirable that none of the voltages across any of the transistors exceed safe operating requirements of the devices, typically 5 or 6 volts. Devices P3, P4, N3, and N4 provide voltage standoff to achieve this.

As can be seen from FIG. 12, as the input goes high, transistor Nl will turn on whereas transistor N2 will turn off. Turning on transistor Nl will take the gate of transistor P2 low which in turn turns on transistor P2 and which thus takes the gate of transistor PI high and turns

3D transistor PI off. In this manner, we see that as the input goes high, the output will also go high to Vddh and likewise vice versa for a low input.

A level shifter according to the present disclosure is shown in FIG. 13. As shown in FIG. 13, the level shifter includes a pair of cross coupled P channel transistors PI and P2 and a pair of N channel input transistors Nl and N2. Voltage standoff transistors P3, P4, N3, and N4 are also provided similar to that as shown in FIG. 12. As shown in FIG. 13, the gates of transistors P3 and P4 are controlled by Vssh and the gates of transistors N3 and N4 are controlled by Vddl. It will be recognized that if Vssh and Vddl are the same voltage levels, then the gates of transistors N3, N4, P3, and P4 may be tied together similar to that as shown in FIG. 12. Additional N channel transistors N5 and N6 are provided as shown. The gate of transistor N6 is tied to the gate of transistor P2 and the gate of transistor N5 is tied to the gate of transistor PI. The drains and sources of transistors N5 and N6 are tied to the output nodes and Vssh as shown.

The circuit of FIG. 13 operates similar to the circuit shown in FIG. 12 since as the input (at the digital logic level) goes high output 1301 likewise goes high (to the Vddh level) and as the input 1300 goes low, the output 1301 is pulled to Vssh.

The functional effect of the addition of transistors N5 and N6 may be seen in FIG. 13 A. Functionally, the transistors PI and P2 may be viewed as an inverter and the transistors N5 and N6 may also be viewed as an inverter. As shown in FIG. 13A this circuit may thus be characterized as two cross coupled inverters 1310 and 1320 which latch each other in one state or another. Thus, a level shifting circuit also having latching characteristics is provided.

Further, the output 1301 may vary between Vddh and Vssh as a function of the digital voltage level at input 1300.

As may be seen from FIGS. 13 and 13 A the level shifter may be viewed as having two legs, the first leg 1330 and a second leg 1340. As the input 1300 goes high transistor N2 will be turned off and there will be no static current through leg 1340 and transistors PI and N6 will be turned off also assuring no static current in leg 1330 or through transistor N6. Similarly in an opposite manner, no static current will exist when the input 1300 goes low.

3\ The circuit shown in FIGS. 13 and 13 A operates between Vddh and Vssh. This circuit may be modified to provide a level shifter which may provide three output voltage ranges. For example, it is desirable that the level shifter provide an output between Vddh and Vssh, between Vddh and ground, and between Vddl and ground. FIG. 14 illustrates a modification to the level shifter of FIG. 13 which provides the three desirable output ranges. As shown in FIG. 14 outputs OUTHV, OUTLV, and OUTFR are provided. Thus, for example using voltage levels of 0, 4, and 8 volts, OUTHV may operate from 4 to 8 volts, OUTLV may operate from 0 to 4 volts, and OUTFR may operate from 0 to 8 volts.

The circuit of FIG. 14 is similar to that as shown in FIG. 13 with the addition of several circuit elements. Two cross coupled P channel transistors P5 and P6 which are tied to Vddl are provided as shown. Further, the separate high voltage output 1400 (OUTHV) and a low voltage output 1402 (OUTLV) are provided. The addition of transistors P5 and P6 tied to Vddl allows the output 1402 to swing between Vddl and ground. As the input 1300 goes high the gate of cross coupled transistor P6 goes low thus shutting off P6 while turning on transistor P5. Likewise in the opposite manner when the input 1300 goes low, the P5 transistor will be turned on and P6 transistor turned off. The output 1400 (OUTHV) operates similar to the output of FIG. 13. The level shifter of FIG. 14 further includes a third circuit leg 1420. Circuit 1420 is tied between Vddh and ground and includes P channel transistors P8 and P9 and N channel transistors N8 and N9 tied in series. An output 1430 is provided (OUTFR) at which the voltage may vary between Vddh and ground. The gate of transistor P8 is tied to OUTHV and the gate of transistor N8 is tied to the low voltage output OUTLV. The transistors P9 and N9 provide voltage standoff effects and are tied to the Vssh and Vddl voltages (which may be one in the same voltage level).

DAC Decoder Architecture and Layout

As discussed above with reference to FIG. 3A and 3B, a typical LCD signal driver circuit includes one decoder cell for each voltage level which may be output to a given channel. Thus, as discussed above with references to FIG. 3A and 3B, 64 decoder cells will be provided for an output channel which has 64 different voltage levels. Further, one switch connected to each voltage level is generally associated with each decoder cell as shown in FIG. 3B. FIG. 15 provides a further illustration of this typical decoder cell architecture. As shown in FIG. 15, a data bus (in this example 6 bits) is connected to each of a series of decoder cells 1502. The output of each decoder cell is connected to a switch 1504 which also receives as an input one of the reference voltage levels. The output of the switch which is connected to the specific decode cell which matches the data on the data bus 1500 is then provided to the channel output 1510.

According to the present invention improved chip area and circuit performance may be obtained by reducing the number of decoder cells per channel by a factor of 2 (e.g. for 64 possible voltage output levels utilizing 32 decoder cells) and providing a single bit selection through switches located at the output line. Such a circuit arrangement further provides an improved decoder column layout in which the decoders from two channels may be interleaved within one column of cells on the signal driver integrated circuit. More particularly with reference to FIG. 16, a data bus 1500 is provided which may include one bit on line 1500A and the remaining bits on a bus 1500B. As shown in this example, the data is arranged such that the five MSBs are provided through bus 1500B to each decoder cell 1600 and the remaining LSB bit is provided along line 1500A. For 64 separate output voltages, 32 decoder cells 1600 will be provided. Voltages V₀, V„ ... V₆₃ are provided to a series of switches 1504. The switches 1504 also receive the output of the decoder cell 1600. As shown in FIG. 16, the output of each decoder cell 1600 is provided to two switches 1504. Thus as can be seen in the figure, the number of decoder cells has been reduced by a factor of two versus the number of reference voltages which may be switched to the output 1510. As can be seen, switch output lines 1604 and 1605 are provided from the switches 1504. Each associated pair of switches 1504 will have one switch connected to switch output line 1604 and one switch connected to switch output line 1605. Additional switches 1610 are provided at the end of the switch output lines 1604 and 1605. The additional switches 1610 operate to perform the final LSB selection so that the desired reference voltage may be switched to the output 1510. Thus as may be seen from the figure, the data is decoded by first decoding the 5 MSBs through the use of the decoder cells and providing two switches at the end of each output line for decoding the one LSB of data. In this manner, the number of decoder cells for any given number of reference voltages per channel may be decreased by a factor of 2. The implementation of the switches 1610 may be performed in a variety of manners. For example as shown in FIG. 17 one implementation of the switches 1610 in combination with the decoder channel multiplexing discussed above is shown. FIG. 17 illustrates two adjacent channels, one utilizing 32 high voltage decoders 1700 and the other utilizing 32 low voltage decoders 1702. Switches 1610 are provided at the output of the decoders to perform the LSB decoding as discussed above with reference to FIG. 16. The decoded output of the switches 1610 on lines 1510 are then provided to the multiplexer 1720 which may be illustrated as eight switches as shown in FIG. 17. A more detailed circuit schematic for the multiplexer 1720 may be a circuit such as shown in FIG. 9.

An alternative embodiment in which the LSB switches and the multiplexing functions are combined is shown in FIG. 18. As shown in FIG. 18 the decoders 1700 and 1702 have outputs which are provided to a series of switches 1800. Switches 1800 also receive as inputs the LSB data bit. Switches 1802 are then utilized to provide the final outputs at output lines 1810 and 1820.

The reduction of decoder cells and the use of a single bit decode at the end of a channel output line provides for a particularly advantageous arrangement of the physical layout of the decoder cells and switches within the signal driver integrated circuit. As shown in FIG. 19, the typical physical layout of the decoders and switches on a signal driver chip is illustrated. As shown in FIG. 19, a resistor string may provide a series of reference voltages V₀, V,, V₂....V₆₄. The reference voltages may then be bused across multiple columns of channels such as channel 1, channel 2, .... channel N, so as to provide the reference voltages to the decoders. Typically, the 64 decoders associated with each reference voltage and the corresponding switches are generally arranged in columns as shown in FIG. 19. The reduction by a factor of two of the number of decoder cells according to the decoder schemes illustrated above with reference to FIG. 16-18 is particularly suited for a physical layout such as shown in FIG. 20. As shown in FIG. 20 any given column of decoders includes the decoders for two channels. Thus, a single column of decoders may contain 32 high voltage decoders and 32 low voltage decoders for an adjacent channel. The interleaving of the decoders from two adjacent channels thus provides a column of substantially the same height as in the prior art, 64 decoders. As shown in FIG. 20, the decoder cells are indicated as CHl-0, CH2-0, CHl-1, CH2-1....CH1-31, CH2-32 to indicate channel one or channel two and decoder cells 0 - 31. As discussed with reference to FIG. 16, each decoder cell is tied to two switches. Thus, as shown in FIG. 20 each decoder cell may include two associated switches for switching reference voltages. For example decoder cell CHl-0 is associated with switches CH1-V₀ and CH1-V, for switching reference voltages V₀ and V] respectively. The physical interleaving of decoder cells for multiple channels within a single column of decoder cells provides an advantageous layout and efficient use of space. Though described with reference to multiplexed decoder channels, the decoder architecture and layout disclosed herein which provides a factor of two reduction of decoder cells and the interleaving layout may be utilized independently of the other features of the signal driver circuit and system according to the disclosure herein.

Decoder Cell

The various embodiments described above may be utilized with a number of decoder cells. The decoder cells may be utilized for the high voltage decoders 810 and low voltage decoders 812 such as shown in FIGS. 8 - 8B. FIG. 20A illustrates one possible arrangement for the inputs provided to the high voltage decoders 810 and low voltage decoders 812. As shown in the example of FIG. 20A, 6 bits of data are decoded in each set of decoders. The high voltage decoders may operate between Vddh and a low voltage Vs. In one embodiment, Vs may be Vssh. In a preferred embodiment, Vs may be ground. The low voltage decoders may operate between Vddl and ground. The decoder cells within the high voltage decoders 810 and low voltage decoders 812 may be configured in a latch/reset manner. A decoder cell having a latch/reset configuration is shown in pending U. S. Application Serial No. 08/240,026 filed May 9, 1994.

As shown in FIG. 20A, the digital data may be inverted prior to being utilized within the decoders. In one embodiment disclosed herein, one bit of the digital data for each set of decoders may be input through a NOR gate which also receives a data enable signal input. As shown in FIG. 20A, a data enable signal 2008 (denhb) is utilized for the high voltage decoders and a data enable signal 2010 (denlb) is utilized with the low voltage decoders. Prior to the digital data being provided at inputs 2004, the data may be level shifted. As used herein, inverted signals of control signals are indicated through the use of "b" at the end the signal name. The data enable signals will be discussed in more detail below.

As shown in FIG. 21, a sample decoder cell for use with either the high voltage decoders or low voltage decoders of FIG. 20 A is illustrated. The example decoder cell in FIG. 21 may operate between Vddh and Vssh for the high voltage decoders and Vddl or ground for the low voltage decoders. The data enable signal (DENB) may be utilized to obtain a gated data input for one of the bits of the six N channel decoding transistors. A resetb signal is also provided as shown in order to reset the inherent latch of the decoder cell and to turn off the switch 2030. For a high voltage decoder, the data enable signal may be level shifted to the high voltage range whereas for the low voltage decoder, the data enable signal does not need level shifting. By gating at least one data bit, the signal path through the six N channel decoding transistors may be broken thus allowing the reset transistor 2040 to reset the inherent latch within the decoder cell (transistors 2041, 2042, and 2043) to prevent undue rush through current flowing through the six N channel decoding transistors and to insure that the latch is reset.

As shown in FIG. 21, the decoder cell may be utilized for both the high voltage decoder cells and the low voltage decoder cells. It may be desirable to utilize different decoder cells for the low voltage decoders as opposed to what is utilized for the high voltage decoders. FIGS. 22 and 23 show two alternative embodiments for use with the high voltage decoder cells. In these embodiments, the decoder cells still utilize the gated data concepts and latching/reset decoder cells.

For example, as shown in FIG. 22, the decoder cell may operate between Vddh and ground. The six N channel decoding transistors are provided in series and one of those transistors may be gated data such as shown through the use of the norgate and the data enable signal (DENB). In addition to the 6 N channel decoding transistors, a P channel transistor 2200 and an N channel transistor 2201 are also provided. The gate of transistor 2200 may be tied to Vssh and the gate of transistor 2201 may be tied to Vddl. It will be recognized that if Vssh and Vddl are the same voltage levels, these gates may be tied together. As shown in FIG. 22, a reset transistor 2040 is provided similar to that as shown in FIG. 21. The latching aspect of the decoder cell (transistors 2041 , 2042, 2043, and 2202) has been improved over the latching features of the cell as shown in FIG. 21 by the addition of transistor 2202. The addition of transistors 2200 and 2201 operate as voltage standoff transistors to enable the decoder to operate from Vddh to ground at the end of the string of 6 N channel decoding transistors. However, because voltage standoff transistor 2200 has its gate at Vssh, this forces node X to be unable to be pulled to Vssh. The addition of transistor 2202 provides a latching mechanism to pull node X to Vssh. Transistor 2200 prevents node X from pulling below Vssh. Likewise, voltage standoff transistor 2201 prevents node Y from pulling above Vddl.

FIG. 23 illustrates yet another embodiment for use of a high voltage decoder cell. As shown in FIG. 23, the decoder cell is similar to that as shown in FIG. 22 with the deletion of transistor 2200. By deleting transistor 220, circuit area is conserved. However, a deletion of transistor 220 would now allow node X to pull below Vssh when the 6 N channel decoding transistors are turned on. To address this problem, the timing of the data enable signal may be adjusted to minimize the time that this occurs. Timing diagrams for the control signals will be discussed in more detail below. In addition to the difference discussed above, FIG. 23 also varies from FIG. 22 in that the source of transistor 2202 is not tied directly to Vssh. Rather, as shown in FIG. 23, the source is tied to node Z. Each decoder cell contains a node Z which is tied to a circuit outside of the decoder cell which allows Vssh to be gated. As shown in the dashed line, the gating circuit 2300 allows node Z to be a gated Vssh that is gated by the resetb signal. The gating of node Z allows the reset transistor 2040 to reset the latch of the decoder cell without having to pull against the transistor 2202. This speeds up reset of the latch and eliminates rush through current through transistor 2202 and 2040.

The gating of at least one of the data bits which are utilized to control the six N channel decoding transistors makes the path through the six N channel decoding transistors to help prevent rush through current through those transistors and to speed up the reset. Figures 24 and 25 illustrate possible timing diagrams for use with the various decoder cells shown. For example, FIG. 24 illustrates a timing diagram which may be utilized with the decoder cells of FIG. 21 and 22 if those decoder cells are implemented in combination with storage registers between the decoder cells and the data mux. For example, such storage registers are shown in FIGS. 3 and as D latches 822 in FIGS. 8 - 8B. The timing diagram shown in FIG. 25 may be utilized with the alternative high voltage embodiment decoder cells shown in FIGS. 22 and 23. This timing diagram of FIG. 25 is utilized with these high voltage decoder cells when no additional latch, such as storage registers 822 is provided. Thus, with utilization of the high voltage decoder cells shown in FIG. 22 and 23 and the timing diagram of FIG. 25, additional storage register latches for the high voltage decoders are not utilized and thus storage registers may only be needed for use with the low voltage decoders. FIG. 26 illustrates such a use. As shown in FIG. 26, the input registers 2600 receive 6 bits of data from the digital data bus and provide that data to the data mux 820. The data mux then utilizes the data polarity signal to provide the data to the appropriate channel. From the data mux, the data for the low voltage decoders proceeds to storage registers 822, whereas the data for the high voltage decoders proceeds directly to the high voltage decoder. Thus, it can be seen from FIG. 26 that the high voltage decoder channel may be implemented without the use of a level shifter or the additional storage register latch.

As shown in FIG. 24, while the resetb signal is low, the decoder is reset. It can be noted that during the entire period that the decoder is being reset, the denb signal is high and thus the gated date is forced low through the NOR gate. Thus, during the entire reset period, the six N channel decoding transistors are non-conductive. Except during the time period where the decoder is being reset, it can be seen in FIG. 24 that all data is valid and a conductive path exists through the one decoder cell which is currently being addressed by the data.

The timing diagram shown in FIG. 25 has been modified from the timing as described above with relation to FIG. 24 so that the latching mechanism of the decoder cell may be utilized to perform the function of the storage register. Thus, the storage register is not necessary for use with the decoder cells of FIG. 22 and 23. Referring again to FIG. 25, it can be seen that data is only enabled for a short period in which the denb signal is low.

Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the shape, size and arrangement and types of components or devices. For example, equivalent elements or materials may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.

35

Claims

WHAT IS CLAIMED IS:

1. A method of reducing power consumption in an LCD signal driver system, comprising:

providing a column voltage for an LCD panel;

circuit, said reference voltage supply circuit including a first set of buffer amplifiers and a second set of buffer amplifiers;

resistor strings being formed in said column signal driver circuit;

second set of buffer amplifiers; and

one other of said resistor strings.

2. An LCD signal driver integrated circuit for driving columns of an LCD panel, said signal driver circuit comprising:

a digital data bus, data on said bus being a digital representation of a voltage level to be provided on at least one column output of said signal driver circuit, said digital data bus being wide enough to carry multiple pixels of data ; and

a data bus width signal coupled to at least one bonding pad of said signal driver integrated circuit, said data bus width signal providing selectable operation of the width of said digital data bus so that said digital data bus may be operating at least two different data bus widths.

3. A method of driving the output columns of an LCD signal driver circuit, comprising:

providing a plurality of column outputs of said LCD signal driver circuit;

providing a plurality of sets of high voltage decoders and a plurality of sets of low voltage decoders; *1 multiplexing at least one of said high voltage decoder sets and at least one of said low voltage decoder sets between two separate column outputs so that two of said decoder sets are not required for each of said column outputs.

4. A method of driving the output columns of an LCD signal driver circuit, comprising:

providing a plurality of column outputs of said LCD signal driver circuit;

providing a plurality of sets of high voltage decoders and a plurality of sets of low voltage decoders including at least a first high voltage decoder seta and a first low voltage decoder set;

switching said first high voltage decoder set and said first low voltage decoder set between first and second column outputs in an alternating manner; and

precharging said first and second column outputs during said switching by sharing charge between said first and second column outputs.

5. A level shifting circuit for use with an LCD system, comprising:

an input for receiving an input signal, said input signals having an voltage range between a first input voltage level and a second input voltage level;

a first, second, and third outputs for providing first, second, and third output signals, said outputs being coupled to said input, said output signals being indicative of said input signal, said output signals being at different voltages than said input signal, at least one of said output signals having a voltage higher than either said first input voltage level and said second input voltage level and at least one of said output signals have a voltage range that is wider than said first input voltage range; and

HO at least two pairs of cross couple transistors, said cross coupled transistors pairs acting as cross coupled inverters latching each other.

6. A decoder architecture for an LCD signal driver circuit, comprising:

an n-bit wide digital data bus, data on said data bus being a digital representation of voltage levels to be applied at column outputs of said signal driver circuit;

a plurality of reference voltages for being provided through a first plurality of switches, said plurality of switches provided voltage outputs on at least two output lines, said at least two output lines being coupled to one of said column outputs;

a plurality of decoder cells for decoder a portion of said data on said digital data bus, said portion being less than all of said bits of said n-bit wide digital data bus; and

at least two additional switches coupled between to said output lines between said first plurality of switches and said one of said column outputs, said additional switches receiving at least one bit of said data on said data bus to complete a decode of said data.

7. A method of operating decoder cells for use with an LCD signal driver circuit comprising:

providing digital data representing a voltage to be applied to an output of said signal driver circuit, said digital data having a maximum voltage level and a minimum voltage level;

providing a set of high voltage decoder cells and a set of low voltage decoder cells;

inputting said digital data to said high voltage decoder cells at a voltage range between said maximum voltage level and said minimum voltage level; and

*╧äl operating said high voltage decoder cells over a voltage range having a high voltage level greater than said maximum voltage level and a low voltage level at said minimum voltage level.

A decoder cell within an LCD driver comprising:

a plurality of data input lines connected to gates of a plurality of decoder transistors connected in series, at least one of said data input lines being gated so that said series connection may be opened even when said decoder cell is addressed;

a latch circuit connected to said data input lines; and

a reset circuit connected to said latch circuit;

wherein said latch circuit holds a decoded state of said decoder cell and said reset circuit resets said latch circuit.

L